1 /* 2 * PWM driver for Rockchip SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * Copyright (C) 2014 ROCKCHIP, Inc. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/time.h> 20 21 #define PWM_CTRL_TIMER_EN (1 << 0) 22 #define PWM_CTRL_OUTPUT_EN (1 << 3) 23 24 #define PWM_ENABLE (1 << 0) 25 #define PWM_CONTINUOUS (1 << 1) 26 #define PWM_DUTY_POSITIVE (1 << 3) 27 #define PWM_DUTY_NEGATIVE (0 << 3) 28 #define PWM_INACTIVE_NEGATIVE (0 << 4) 29 #define PWM_INACTIVE_POSITIVE (1 << 4) 30 #define PWM_OUTPUT_LEFT (0 << 5) 31 #define PWM_LP_DISABLE (0 << 8) 32 33 struct rockchip_pwm_chip { 34 struct pwm_chip chip; 35 struct clk *clk; 36 const struct rockchip_pwm_data *data; 37 void __iomem *base; 38 }; 39 40 struct rockchip_pwm_regs { 41 unsigned long duty; 42 unsigned long period; 43 unsigned long cntr; 44 unsigned long ctrl; 45 }; 46 47 struct rockchip_pwm_data { 48 struct rockchip_pwm_regs regs; 49 unsigned int prescaler; 50 const struct pwm_ops *ops; 51 52 void (*set_enable)(struct pwm_chip *chip, 53 struct pwm_device *pwm, bool enable); 54 }; 55 56 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) 57 { 58 return container_of(c, struct rockchip_pwm_chip, chip); 59 } 60 61 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, 62 struct pwm_device *pwm, bool enable) 63 { 64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 65 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 66 u32 val; 67 68 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 69 70 if (enable) 71 val |= enable_conf; 72 else 73 val &= ~enable_conf; 74 75 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 76 } 77 78 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, 79 struct pwm_device *pwm, bool enable) 80 { 81 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 82 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 83 PWM_CONTINUOUS; 84 u32 val; 85 86 if (pwm->polarity == PWM_POLARITY_INVERSED) 87 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 88 else 89 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 90 91 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 92 93 if (enable) 94 val |= enable_conf; 95 else 96 val &= ~enable_conf; 97 98 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 99 } 100 101 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 102 int duty_ns, int period_ns) 103 { 104 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 105 unsigned long period, duty; 106 u64 clk_rate, div; 107 int ret; 108 109 clk_rate = clk_get_rate(pc->clk); 110 111 /* 112 * Since period and duty cycle registers have a width of 32 113 * bits, every possible input period can be obtained using the 114 * default prescaler value for all practical clock rate values. 115 */ 116 div = clk_rate * period_ns; 117 do_div(div, pc->data->prescaler * NSEC_PER_SEC); 118 period = div; 119 120 div = clk_rate * duty_ns; 121 do_div(div, pc->data->prescaler * NSEC_PER_SEC); 122 duty = div; 123 124 ret = clk_enable(pc->clk); 125 if (ret) 126 return ret; 127 128 writel(period, pc->base + pc->data->regs.period); 129 writel(duty, pc->base + pc->data->regs.duty); 130 writel(0, pc->base + pc->data->regs.cntr); 131 132 clk_disable(pc->clk); 133 134 return 0; 135 } 136 137 static int rockchip_pwm_set_polarity(struct pwm_chip *chip, 138 struct pwm_device *pwm, 139 enum pwm_polarity polarity) 140 { 141 /* 142 * No action needed here because pwm->polarity will be set by the core 143 * and the core will only change polarity when the PWM is not enabled. 144 * We'll handle things in set_enable(). 145 */ 146 147 return 0; 148 } 149 150 static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 151 { 152 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 153 int ret; 154 155 ret = clk_enable(pc->clk); 156 if (ret) 157 return ret; 158 159 pc->data->set_enable(chip, pwm, true); 160 161 return 0; 162 } 163 164 static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 165 { 166 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 167 168 pc->data->set_enable(chip, pwm, false); 169 170 clk_disable(pc->clk); 171 } 172 173 static const struct pwm_ops rockchip_pwm_ops_v1 = { 174 .config = rockchip_pwm_config, 175 .enable = rockchip_pwm_enable, 176 .disable = rockchip_pwm_disable, 177 .owner = THIS_MODULE, 178 }; 179 180 static const struct pwm_ops rockchip_pwm_ops_v2 = { 181 .config = rockchip_pwm_config, 182 .set_polarity = rockchip_pwm_set_polarity, 183 .enable = rockchip_pwm_enable, 184 .disable = rockchip_pwm_disable, 185 .owner = THIS_MODULE, 186 }; 187 188 static const struct rockchip_pwm_data pwm_data_v1 = { 189 .regs = { 190 .duty = 0x04, 191 .period = 0x08, 192 .cntr = 0x00, 193 .ctrl = 0x0c, 194 }, 195 .prescaler = 2, 196 .ops = &rockchip_pwm_ops_v1, 197 .set_enable = rockchip_pwm_set_enable_v1, 198 }; 199 200 static const struct rockchip_pwm_data pwm_data_v2 = { 201 .regs = { 202 .duty = 0x08, 203 .period = 0x04, 204 .cntr = 0x00, 205 .ctrl = 0x0c, 206 }, 207 .prescaler = 1, 208 .ops = &rockchip_pwm_ops_v2, 209 .set_enable = rockchip_pwm_set_enable_v2, 210 }; 211 212 static const struct rockchip_pwm_data pwm_data_vop = { 213 .regs = { 214 .duty = 0x08, 215 .period = 0x04, 216 .cntr = 0x0c, 217 .ctrl = 0x00, 218 }, 219 .prescaler = 1, 220 .ops = &rockchip_pwm_ops_v2, 221 .set_enable = rockchip_pwm_set_enable_v2, 222 }; 223 224 static const struct of_device_id rockchip_pwm_dt_ids[] = { 225 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 226 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 227 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 228 { /* sentinel */ } 229 }; 230 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); 231 232 static int rockchip_pwm_probe(struct platform_device *pdev) 233 { 234 const struct of_device_id *id; 235 struct rockchip_pwm_chip *pc; 236 struct resource *r; 237 int ret; 238 239 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 240 if (!id) 241 return -EINVAL; 242 243 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 244 if (!pc) 245 return -ENOMEM; 246 247 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 248 pc->base = devm_ioremap_resource(&pdev->dev, r); 249 if (IS_ERR(pc->base)) 250 return PTR_ERR(pc->base); 251 252 pc->clk = devm_clk_get(&pdev->dev, NULL); 253 if (IS_ERR(pc->clk)) 254 return PTR_ERR(pc->clk); 255 256 ret = clk_prepare(pc->clk); 257 if (ret) 258 return ret; 259 260 platform_set_drvdata(pdev, pc); 261 262 pc->data = id->data; 263 pc->chip.dev = &pdev->dev; 264 pc->chip.ops = pc->data->ops; 265 pc->chip.base = -1; 266 pc->chip.npwm = 1; 267 268 if (pc->data->ops->set_polarity) { 269 pc->chip.of_xlate = of_pwm_xlate_with_flags; 270 pc->chip.of_pwm_n_cells = 3; 271 } 272 273 ret = pwmchip_add(&pc->chip); 274 if (ret < 0) { 275 clk_unprepare(pc->clk); 276 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 277 } 278 279 return ret; 280 } 281 282 static int rockchip_pwm_remove(struct platform_device *pdev) 283 { 284 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); 285 286 clk_unprepare(pc->clk); 287 288 return pwmchip_remove(&pc->chip); 289 } 290 291 static struct platform_driver rockchip_pwm_driver = { 292 .driver = { 293 .name = "rockchip-pwm", 294 .of_match_table = rockchip_pwm_dt_ids, 295 }, 296 .probe = rockchip_pwm_probe, 297 .remove = rockchip_pwm_remove, 298 }; 299 module_platform_driver(rockchip_pwm_driver); 300 301 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 302 MODULE_DESCRIPTION("Rockchip SoC PWM driver"); 303 MODULE_LICENSE("GPL v2"); 304