1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R-Mobile TPU PWM driver 4 * 5 * Copyright (C) 2012 Renesas Solutions Corp. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/init.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pwm.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 21 #define TPU_CHANNEL_MAX 4 22 23 #define TPU_TSTR 0x00 /* Timer start register (shared) */ 24 25 #define TPU_TCRn 0x00 /* Timer control register */ 26 #define TPU_TCR_CCLR_NONE (0 << 5) 27 #define TPU_TCR_CCLR_TGRA (1 << 5) 28 #define TPU_TCR_CCLR_TGRB (2 << 5) 29 #define TPU_TCR_CCLR_TGRC (5 << 5) 30 #define TPU_TCR_CCLR_TGRD (6 << 5) 31 #define TPU_TCR_CKEG_RISING (0 << 3) 32 #define TPU_TCR_CKEG_FALLING (1 << 3) 33 #define TPU_TCR_CKEG_BOTH (2 << 3) 34 #define TPU_TMDRn 0x04 /* Timer mode register */ 35 #define TPU_TMDR_BFWT (1 << 6) 36 #define TPU_TMDR_BFB (1 << 5) 37 #define TPU_TMDR_BFA (1 << 4) 38 #define TPU_TMDR_MD_NORMAL (0 << 0) 39 #define TPU_TMDR_MD_PWM (2 << 0) 40 #define TPU_TIORn 0x08 /* Timer I/O control register */ 41 #define TPU_TIOR_IOA_0 (0 << 0) 42 #define TPU_TIOR_IOA_0_CLR (1 << 0) 43 #define TPU_TIOR_IOA_0_SET (2 << 0) 44 #define TPU_TIOR_IOA_0_TOGGLE (3 << 0) 45 #define TPU_TIOR_IOA_1 (4 << 0) 46 #define TPU_TIOR_IOA_1_CLR (5 << 0) 47 #define TPU_TIOR_IOA_1_SET (6 << 0) 48 #define TPU_TIOR_IOA_1_TOGGLE (7 << 0) 49 #define TPU_TIERn 0x0c /* Timer interrupt enable register */ 50 #define TPU_TSRn 0x10 /* Timer status register */ 51 #define TPU_TCNTn 0x14 /* Timer counter */ 52 #define TPU_TGRAn 0x18 /* Timer general register A */ 53 #define TPU_TGRBn 0x1c /* Timer general register B */ 54 #define TPU_TGRCn 0x20 /* Timer general register C */ 55 #define TPU_TGRDn 0x24 /* Timer general register D */ 56 57 #define TPU_CHANNEL_OFFSET 0x10 58 #define TPU_CHANNEL_SIZE 0x40 59 60 enum tpu_pin_state { 61 TPU_PIN_INACTIVE, /* Pin is driven inactive */ 62 TPU_PIN_PWM, /* Pin is driven by PWM */ 63 TPU_PIN_ACTIVE, /* Pin is driven active */ 64 }; 65 66 struct tpu_device; 67 68 struct tpu_pwm_device { 69 bool timer_on; /* Whether the timer is running */ 70 71 struct tpu_device *tpu; 72 unsigned int channel; /* Channel number in the TPU */ 73 74 enum pwm_polarity polarity; 75 unsigned int prescaler; 76 u16 period; 77 u16 duty; 78 }; 79 80 struct tpu_device { 81 struct platform_device *pdev; 82 struct pwm_chip chip; 83 spinlock_t lock; 84 85 void __iomem *base; 86 struct clk *clk; 87 struct tpu_pwm_device tpd[TPU_CHANNEL_MAX]; 88 }; 89 90 #define to_tpu_device(c) container_of(c, struct tpu_device, chip) 91 92 static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value) 93 { 94 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET 95 + tpd->channel * TPU_CHANNEL_SIZE; 96 97 iowrite16(value, base + reg_nr); 98 } 99 100 static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd, 101 enum tpu_pin_state state) 102 { 103 static const char * const states[] = { "inactive", "PWM", "active" }; 104 105 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", 106 tpd->channel, states[state]); 107 108 switch (state) { 109 case TPU_PIN_INACTIVE: 110 tpu_pwm_write(tpd, TPU_TIORn, 111 tpd->polarity == PWM_POLARITY_INVERSED ? 112 TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0); 113 break; 114 case TPU_PIN_PWM: 115 tpu_pwm_write(tpd, TPU_TIORn, 116 tpd->polarity == PWM_POLARITY_INVERSED ? 117 TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR); 118 break; 119 case TPU_PIN_ACTIVE: 120 tpu_pwm_write(tpd, TPU_TIORn, 121 tpd->polarity == PWM_POLARITY_INVERSED ? 122 TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1); 123 break; 124 } 125 } 126 127 static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start) 128 { 129 unsigned long flags; 130 u16 value; 131 132 spin_lock_irqsave(&tpd->tpu->lock, flags); 133 value = ioread16(tpd->tpu->base + TPU_TSTR); 134 135 if (start) 136 value |= 1 << tpd->channel; 137 else 138 value &= ~(1 << tpd->channel); 139 140 iowrite16(value, tpd->tpu->base + TPU_TSTR); 141 spin_unlock_irqrestore(&tpd->tpu->lock, flags); 142 } 143 144 static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd) 145 { 146 int ret; 147 148 if (!tpd->timer_on) { 149 /* Wake up device and enable clock. */ 150 pm_runtime_get_sync(&tpd->tpu->pdev->dev); 151 ret = clk_prepare_enable(tpd->tpu->clk); 152 if (ret) { 153 dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n"); 154 return ret; 155 } 156 tpd->timer_on = true; 157 } 158 159 /* 160 * Make sure the channel is stopped, as we need to reconfigure it 161 * completely. First drive the pin to the inactive state to avoid 162 * glitches. 163 */ 164 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE); 165 tpu_pwm_start_stop(tpd, false); 166 167 /* 168 * - Clear TCNT on TGRB match 169 * - Count on rising edge 170 * - Set prescaler 171 * - Output 0 until TGRA, output 1 until TGRB (active low polarity) 172 * - Output 1 until TGRA, output 0 until TGRB (active high polarity 173 * - PWM mode 174 */ 175 tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING | 176 tpd->prescaler); 177 tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM); 178 tpu_pwm_set_pin(tpd, TPU_PIN_PWM); 179 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); 180 tpu_pwm_write(tpd, TPU_TGRBn, tpd->period); 181 182 dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n", 183 tpd->channel, tpd->duty, tpd->period); 184 185 /* Start the channel. */ 186 tpu_pwm_start_stop(tpd, true); 187 188 return 0; 189 } 190 191 static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd) 192 { 193 if (!tpd->timer_on) 194 return; 195 196 /* Disable channel. */ 197 tpu_pwm_start_stop(tpd, false); 198 199 /* Stop clock and mark device as idle. */ 200 clk_disable_unprepare(tpd->tpu->clk); 201 pm_runtime_put(&tpd->tpu->pdev->dev); 202 203 tpd->timer_on = false; 204 } 205 206 /* ----------------------------------------------------------------------------- 207 * PWM API 208 */ 209 210 static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 211 { 212 struct tpu_device *tpu = to_tpu_device(chip); 213 struct tpu_pwm_device *tpd; 214 215 if (pwm->hwpwm >= TPU_CHANNEL_MAX) 216 return -EINVAL; 217 218 tpd = &tpu->tpd[pwm->hwpwm]; 219 220 tpd->tpu = tpu; 221 tpd->channel = pwm->hwpwm; 222 tpd->polarity = PWM_POLARITY_NORMAL; 223 tpd->prescaler = 0; 224 tpd->period = 0; 225 tpd->duty = 0; 226 227 tpd->timer_on = false; 228 229 return 0; 230 } 231 232 static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 233 { 234 struct tpu_device *tpu = to_tpu_device(chip); 235 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 236 237 tpu_pwm_timer_stop(tpd); 238 } 239 240 static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 241 u64 duty_ns, u64 period_ns, bool enabled) 242 { 243 struct tpu_device *tpu = to_tpu_device(chip); 244 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 245 unsigned int prescaler; 246 bool duty_only = false; 247 u32 clk_rate; 248 u64 period; 249 u32 duty; 250 int ret; 251 252 clk_rate = clk_get_rate(tpu->clk); 253 if (unlikely(clk_rate > NSEC_PER_SEC)) { 254 /* 255 * This won't happen in the nearer future, so this is only a 256 * safeguard to prevent the following calculation from 257 * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is 258 * not greater than period_ns and so fits into an u64. 259 */ 260 return -EINVAL; 261 } 262 263 period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC); 264 265 /* 266 * Find the minimal prescaler in [0..3] such that 267 * 268 * period >> (2 * prescaler) < 0x10000 269 * 270 * This could be calculated using something like: 271 * 272 * prescaler = max(ilog2(period) / 2, 7) - 7; 273 * 274 * but given there are only four allowed results and that ilog2 isn't 275 * cheap on all platforms using a switch statement is more effective. 276 */ 277 switch (period) { 278 case 1 ... 0xffff: 279 prescaler = 0; 280 break; 281 282 case 0x10000 ... 0x3ffff: 283 prescaler = 1; 284 break; 285 286 case 0x40000 ... 0xfffff: 287 prescaler = 2; 288 break; 289 290 case 0x100000 ... 0x3fffff: 291 prescaler = 3; 292 break; 293 294 default: 295 return -EINVAL; 296 } 297 298 period >>= 2 * prescaler; 299 300 if (duty_ns) 301 duty = mul_u64_u64_div_u64(clk_rate, duty_ns, 302 (u64)NSEC_PER_SEC << (2 * prescaler)); 303 else 304 duty = 0; 305 306 dev_dbg(&tpu->pdev->dev, 307 "rate %u, prescaler %u, period %u, duty %u\n", 308 clk_rate, 1 << (2 * prescaler), (u32)period, duty); 309 310 if (tpd->prescaler == prescaler && tpd->period == period) 311 duty_only = true; 312 313 tpd->prescaler = prescaler; 314 tpd->period = period; 315 tpd->duty = duty; 316 317 /* If the channel is disabled we're done. */ 318 if (!enabled) 319 return 0; 320 321 if (duty_only && tpd->timer_on) { 322 /* 323 * If only the duty cycle changed and the timer is already 324 * running, there's no need to reconfigure it completely, Just 325 * modify the duty cycle. 326 */ 327 tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty); 328 dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel, 329 tpd->duty); 330 } else { 331 /* Otherwise perform a full reconfiguration. */ 332 ret = tpu_pwm_timer_start(tpd); 333 if (ret < 0) 334 return ret; 335 } 336 337 if (duty == 0 || duty == period) { 338 /* 339 * To avoid running the timer when not strictly required, handle 340 * 0% and 100% duty cycles as fixed levels and stop the timer. 341 */ 342 tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); 343 tpu_pwm_timer_stop(tpd); 344 } 345 346 return 0; 347 } 348 349 static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, 350 enum pwm_polarity polarity) 351 { 352 struct tpu_device *tpu = to_tpu_device(chip); 353 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 354 355 tpd->polarity = polarity; 356 357 return 0; 358 } 359 360 static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 361 { 362 struct tpu_device *tpu = to_tpu_device(chip); 363 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 364 int ret; 365 366 ret = tpu_pwm_timer_start(tpd); 367 if (ret < 0) 368 return ret; 369 370 /* 371 * To avoid running the timer when not strictly required, handle 0% and 372 * 100% duty cycles as fixed levels and stop the timer. 373 */ 374 if (tpd->duty == 0 || tpd->duty == tpd->period) { 375 tpu_pwm_set_pin(tpd, tpd->duty ? 376 TPU_PIN_ACTIVE : TPU_PIN_INACTIVE); 377 tpu_pwm_timer_stop(tpd); 378 } 379 380 return 0; 381 } 382 383 static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 384 { 385 struct tpu_device *tpu = to_tpu_device(chip); 386 struct tpu_pwm_device *tpd = &tpu->tpd[pwm->hwpwm]; 387 388 /* The timer must be running to modify the pin output configuration. */ 389 tpu_pwm_timer_start(tpd); 390 tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE); 391 tpu_pwm_timer_stop(tpd); 392 } 393 394 static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 395 const struct pwm_state *state) 396 { 397 int err; 398 bool enabled = pwm->state.enabled; 399 400 if (state->polarity != pwm->state.polarity) { 401 if (enabled) { 402 tpu_pwm_disable(chip, pwm); 403 enabled = false; 404 } 405 406 err = tpu_pwm_set_polarity(chip, pwm, state->polarity); 407 if (err) 408 return err; 409 } 410 411 if (!state->enabled) { 412 if (enabled) 413 tpu_pwm_disable(chip, pwm); 414 415 return 0; 416 } 417 418 err = tpu_pwm_config(chip, pwm, 419 state->duty_cycle, state->period, enabled); 420 if (err) 421 return err; 422 423 if (!enabled) 424 err = tpu_pwm_enable(chip, pwm); 425 426 return err; 427 } 428 429 static const struct pwm_ops tpu_pwm_ops = { 430 .request = tpu_pwm_request, 431 .free = tpu_pwm_free, 432 .apply = tpu_pwm_apply, 433 }; 434 435 /* ----------------------------------------------------------------------------- 436 * Probe and remove 437 */ 438 439 static int tpu_probe(struct platform_device *pdev) 440 { 441 struct tpu_device *tpu; 442 int ret; 443 444 tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL); 445 if (tpu == NULL) 446 return -ENOMEM; 447 448 spin_lock_init(&tpu->lock); 449 tpu->pdev = pdev; 450 451 /* Map memory, get clock and pin control. */ 452 tpu->base = devm_platform_ioremap_resource(pdev, 0); 453 if (IS_ERR(tpu->base)) 454 return PTR_ERR(tpu->base); 455 456 tpu->clk = devm_clk_get(&pdev->dev, NULL); 457 if (IS_ERR(tpu->clk)) 458 return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n"); 459 460 /* Initialize and register the device. */ 461 platform_set_drvdata(pdev, tpu); 462 463 tpu->chip.dev = &pdev->dev; 464 tpu->chip.ops = &tpu_pwm_ops; 465 tpu->chip.npwm = TPU_CHANNEL_MAX; 466 467 ret = devm_pm_runtime_enable(&pdev->dev); 468 if (ret < 0) 469 return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n"); 470 471 ret = devm_pwmchip_add(&pdev->dev, &tpu->chip); 472 if (ret < 0) 473 return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n"); 474 475 return 0; 476 } 477 478 #ifdef CONFIG_OF 479 static const struct of_device_id tpu_of_table[] = { 480 { .compatible = "renesas,tpu-r8a73a4", }, 481 { .compatible = "renesas,tpu-r8a7740", }, 482 { .compatible = "renesas,tpu-r8a7790", }, 483 { .compatible = "renesas,tpu", }, 484 { }, 485 }; 486 487 MODULE_DEVICE_TABLE(of, tpu_of_table); 488 #endif 489 490 static struct platform_driver tpu_driver = { 491 .probe = tpu_probe, 492 .driver = { 493 .name = "renesas-tpu-pwm", 494 .of_match_table = of_match_ptr(tpu_of_table), 495 } 496 }; 497 498 module_platform_driver(tpu_driver); 499 500 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 501 MODULE_DESCRIPTION("Renesas TPU PWM Driver"); 502 MODULE_LICENSE("GPL v2"); 503 MODULE_ALIAS("platform:renesas-tpu-pwm"); 504