1 /* 2 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com> 3 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com> 4 * Copyright (c) 2012 NeilBrown <neilb@suse.de> 5 * Heavily based on earlier code which is: 6 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com> 7 * 8 * Also based on pwm-samsung.c 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License 12 * version 2 as published by the Free Software Foundation. 13 * 14 * Description: 15 * This file is the core OMAP support for the generic, Linux 16 * PWM driver / controller, using the OMAP's dual-mode timers. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_data/dmtimer-omap.h> 27 #include <linux/platform_data/pwm_omap_dmtimer.h> 28 #include <linux/platform_device.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/pwm.h> 31 #include <linux/slab.h> 32 #include <linux/time.h> 33 34 #define DM_TIMER_LOAD_MIN 0xfffffffe 35 #define DM_TIMER_MAX 0xffffffff 36 37 struct pwm_omap_dmtimer_chip { 38 struct pwm_chip chip; 39 struct mutex mutex; 40 pwm_omap_dmtimer *dm_timer; 41 const struct omap_dm_timer_ops *pdata; 42 struct platform_device *dm_timer_pdev; 43 }; 44 45 static inline struct pwm_omap_dmtimer_chip * 46 to_pwm_omap_dmtimer_chip(struct pwm_chip *chip) 47 { 48 return container_of(chip, struct pwm_omap_dmtimer_chip, chip); 49 } 50 51 static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns) 52 { 53 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC); 54 } 55 56 static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap) 57 { 58 /* 59 * According to OMAP 4 TRM section 22.2.4.10 the counter should be 60 * started at 0xFFFFFFFE when overflow and match is used to ensure 61 * that the PWM line is toggled on the first event. 62 * 63 * Note that omap_dm_timer_enable/disable is for register access and 64 * not the timer counter itself. 65 */ 66 omap->pdata->enable(omap->dm_timer); 67 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN); 68 omap->pdata->disable(omap->dm_timer); 69 70 omap->pdata->start(omap->dm_timer); 71 } 72 73 static int pwm_omap_dmtimer_enable(struct pwm_chip *chip, 74 struct pwm_device *pwm) 75 { 76 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip); 77 78 mutex_lock(&omap->mutex); 79 pwm_omap_dmtimer_start(omap); 80 mutex_unlock(&omap->mutex); 81 82 return 0; 83 } 84 85 static void pwm_omap_dmtimer_disable(struct pwm_chip *chip, 86 struct pwm_device *pwm) 87 { 88 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip); 89 90 mutex_lock(&omap->mutex); 91 omap->pdata->stop(omap->dm_timer); 92 mutex_unlock(&omap->mutex); 93 } 94 95 static int pwm_omap_dmtimer_config(struct pwm_chip *chip, 96 struct pwm_device *pwm, 97 int duty_ns, int period_ns) 98 { 99 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip); 100 u32 period_cycles, duty_cycles; 101 u32 load_value, match_value; 102 struct clk *fclk; 103 unsigned long clk_rate; 104 bool timer_active; 105 106 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n", 107 duty_ns, period_ns); 108 109 mutex_lock(&omap->mutex); 110 if (duty_ns == pwm_get_duty_cycle(pwm) && 111 period_ns == pwm_get_period(pwm)) { 112 /* No change - don't cause any transients. */ 113 mutex_unlock(&omap->mutex); 114 return 0; 115 } 116 117 fclk = omap->pdata->get_fclk(omap->dm_timer); 118 if (!fclk) { 119 dev_err(chip->dev, "invalid pmtimer fclk\n"); 120 goto err_einval; 121 } 122 123 clk_rate = clk_get_rate(fclk); 124 if (!clk_rate) { 125 dev_err(chip->dev, "invalid pmtimer fclk rate\n"); 126 goto err_einval; 127 } 128 129 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate); 130 131 /* 132 * Calculate the appropriate load and match values based on the 133 * specified period and duty cycle. The load value determines the 134 * period time and the match value determines the duty time. 135 * 136 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles. 137 * Similarly, the active time lasts (match_value-load_value+1) cycles. 138 * The non-active time is the remainder: (DM_TIMER_MAX-match_value) 139 * clock cycles. 140 * 141 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX 142 * 143 * References: 144 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11 145 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6 146 */ 147 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns); 148 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns); 149 150 if (period_cycles < 2) { 151 dev_info(chip->dev, 152 "period %d ns too short for clock rate %lu Hz\n", 153 period_ns, clk_rate); 154 goto err_einval; 155 } 156 157 if (duty_cycles < 1) { 158 dev_dbg(chip->dev, 159 "duty cycle %d ns is too short for clock rate %lu Hz\n", 160 duty_ns, clk_rate); 161 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n"); 162 duty_cycles = 1; 163 } else if (duty_cycles >= period_cycles) { 164 dev_dbg(chip->dev, 165 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n", 166 duty_ns, period_ns, clk_rate); 167 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n"); 168 duty_cycles = period_cycles - 1; 169 } 170 171 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n", 172 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles, 173 clk_rate), 174 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles, 175 clk_rate)); 176 177 load_value = (DM_TIMER_MAX - period_cycles) + 1; 178 match_value = load_value + duty_cycles - 1; 179 180 /* 181 * We MUST stop the associated dual-mode timer before attempting to 182 * write its registers, but calls to omap_dm_timer_start/stop must 183 * be balanced so check if timer is active before calling timer_stop. 184 */ 185 timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev); 186 if (timer_active) 187 omap->pdata->stop(omap->dm_timer); 188 189 omap->pdata->set_load(omap->dm_timer, true, load_value); 190 omap->pdata->set_match(omap->dm_timer, true, match_value); 191 192 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n", 193 load_value, load_value, match_value, match_value); 194 195 omap->pdata->set_pwm(omap->dm_timer, 196 pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED, 197 true, 198 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE); 199 200 /* If config was called while timer was running it must be reenabled. */ 201 if (timer_active) 202 pwm_omap_dmtimer_start(omap); 203 204 mutex_unlock(&omap->mutex); 205 206 return 0; 207 208 err_einval: 209 mutex_unlock(&omap->mutex); 210 211 return -EINVAL; 212 } 213 214 static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip, 215 struct pwm_device *pwm, 216 enum pwm_polarity polarity) 217 { 218 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip); 219 220 /* 221 * PWM core will not call set_polarity while PWM is enabled so it's 222 * safe to reconfigure the timer here without stopping it first. 223 */ 224 mutex_lock(&omap->mutex); 225 omap->pdata->set_pwm(omap->dm_timer, 226 polarity == PWM_POLARITY_INVERSED, 227 true, 228 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE); 229 mutex_unlock(&omap->mutex); 230 231 return 0; 232 } 233 234 static const struct pwm_ops pwm_omap_dmtimer_ops = { 235 .enable = pwm_omap_dmtimer_enable, 236 .disable = pwm_omap_dmtimer_disable, 237 .config = pwm_omap_dmtimer_config, 238 .set_polarity = pwm_omap_dmtimer_set_polarity, 239 .owner = THIS_MODULE, 240 }; 241 242 static int pwm_omap_dmtimer_probe(struct platform_device *pdev) 243 { 244 struct device_node *np = pdev->dev.of_node; 245 struct device_node *timer; 246 struct platform_device *timer_pdev; 247 struct pwm_omap_dmtimer_chip *omap; 248 struct dmtimer_platform_data *timer_pdata; 249 const struct omap_dm_timer_ops *pdata; 250 pwm_omap_dmtimer *dm_timer; 251 u32 v; 252 int ret = 0; 253 254 timer = of_parse_phandle(np, "ti,timers", 0); 255 if (!timer) 256 return -ENODEV; 257 258 timer_pdev = of_find_device_by_node(timer); 259 if (!timer_pdev) { 260 dev_err(&pdev->dev, "Unable to find Timer pdev\n"); 261 ret = -ENODEV; 262 goto put; 263 } 264 265 timer_pdata = dev_get_platdata(&timer_pdev->dev); 266 if (!timer_pdata) { 267 dev_dbg(&pdev->dev, 268 "dmtimer pdata structure NULL, deferring probe\n"); 269 ret = -EPROBE_DEFER; 270 goto put; 271 } 272 273 pdata = timer_pdata->timer_ops; 274 275 if (!pdata || !pdata->request_by_node || 276 !pdata->free || 277 !pdata->enable || 278 !pdata->disable || 279 !pdata->get_fclk || 280 !pdata->start || 281 !pdata->stop || 282 !pdata->set_load || 283 !pdata->set_match || 284 !pdata->set_pwm || 285 !pdata->set_prescaler || 286 !pdata->write_counter) { 287 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n"); 288 ret = -EINVAL; 289 goto put; 290 } 291 292 if (!of_get_property(timer, "ti,timer-pwm", NULL)) { 293 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n"); 294 ret = -ENODEV; 295 goto put; 296 } 297 298 dm_timer = pdata->request_by_node(timer); 299 if (!dm_timer) { 300 ret = -EPROBE_DEFER; 301 goto put; 302 } 303 304 put: 305 of_node_put(timer); 306 if (ret < 0) 307 return ret; 308 309 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL); 310 if (!omap) { 311 pdata->free(dm_timer); 312 return -ENOMEM; 313 } 314 315 omap->pdata = pdata; 316 omap->dm_timer = dm_timer; 317 omap->dm_timer_pdev = timer_pdev; 318 319 /* 320 * Ensure that the timer is stopped before we allow PWM core to call 321 * pwm_enable. 322 */ 323 if (pm_runtime_active(&omap->dm_timer_pdev->dev)) 324 omap->pdata->stop(omap->dm_timer); 325 326 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v)) 327 omap->pdata->set_prescaler(omap->dm_timer, v); 328 329 /* setup dmtimer clock source */ 330 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v)) 331 omap->pdata->set_source(omap->dm_timer, v); 332 333 omap->chip.dev = &pdev->dev; 334 omap->chip.ops = &pwm_omap_dmtimer_ops; 335 omap->chip.base = -1; 336 omap->chip.npwm = 1; 337 omap->chip.of_xlate = of_pwm_xlate_with_flags; 338 omap->chip.of_pwm_n_cells = 3; 339 340 mutex_init(&omap->mutex); 341 342 ret = pwmchip_add(&omap->chip); 343 if (ret < 0) { 344 dev_err(&pdev->dev, "failed to register PWM\n"); 345 omap->pdata->free(omap->dm_timer); 346 return ret; 347 } 348 349 platform_set_drvdata(pdev, omap); 350 351 return 0; 352 } 353 354 static int pwm_omap_dmtimer_remove(struct platform_device *pdev) 355 { 356 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev); 357 358 if (pm_runtime_active(&omap->dm_timer_pdev->dev)) 359 omap->pdata->stop(omap->dm_timer); 360 361 omap->pdata->free(omap->dm_timer); 362 363 mutex_destroy(&omap->mutex); 364 365 return pwmchip_remove(&omap->chip); 366 } 367 368 static const struct of_device_id pwm_omap_dmtimer_of_match[] = { 369 {.compatible = "ti,omap-dmtimer-pwm"}, 370 {} 371 }; 372 MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match); 373 374 static struct platform_driver pwm_omap_dmtimer_driver = { 375 .driver = { 376 .name = "omap-dmtimer-pwm", 377 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match), 378 }, 379 .probe = pwm_omap_dmtimer_probe, 380 .remove = pwm_omap_dmtimer_remove, 381 }; 382 module_platform_driver(pwm_omap_dmtimer_driver); 383 384 MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>"); 385 MODULE_AUTHOR("NeilBrown <neilb@suse.de>"); 386 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 387 MODULE_LICENSE("GPL v2"); 388 MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers"); 389