1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/err.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pwm.h> 14 #include <linux/slab.h> 15 #include <linux/stmp_device.h> 16 17 #define SET 0x4 18 #define CLR 0x8 19 #define TOG 0xc 20 21 #define PWM_CTRL 0x0 22 #define PWM_ACTIVE0 0x10 23 #define PWM_PERIOD0 0x20 24 #define PERIOD_PERIOD(p) ((p) & 0xffff) 25 #define PERIOD_PERIOD_MAX 0x10000 26 #define PERIOD_ACTIVE_HIGH (3 << 16) 27 #define PERIOD_ACTIVE_LOW (2 << 16) 28 #define PERIOD_INACTIVE_HIGH (3 << 18) 29 #define PERIOD_INACTIVE_LOW (2 << 18) 30 #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW) 31 #define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH) 32 #define PERIOD_CDIV(div) (((div) & 0x7) << 20) 33 #define PERIOD_CDIV_MAX 8 34 35 static const u8 cdiv_shift[PERIOD_CDIV_MAX] = { 36 0, 1, 2, 3, 4, 6, 8, 10 37 }; 38 39 struct mxs_pwm_chip { 40 struct pwm_chip chip; 41 struct clk *clk; 42 void __iomem *base; 43 }; 44 45 #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip) 46 47 static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 48 const struct pwm_state *state) 49 { 50 struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip); 51 int ret, div = 0; 52 unsigned int period_cycles, duty_cycles; 53 unsigned long rate; 54 unsigned long long c; 55 unsigned int pol_bits; 56 57 /* 58 * If the PWM channel is disabled, make sure to turn on the 59 * clock before calling clk_get_rate() and writing to the 60 * registers. Otherwise, just keep it enabled. 61 */ 62 if (!pwm_is_enabled(pwm)) { 63 ret = clk_prepare_enable(mxs->clk); 64 if (ret) 65 return ret; 66 } 67 68 if (!state->enabled && pwm_is_enabled(pwm)) 69 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); 70 71 rate = clk_get_rate(mxs->clk); 72 while (1) { 73 c = rate >> cdiv_shift[div]; 74 c = c * state->period; 75 do_div(c, 1000000000); 76 if (c < PERIOD_PERIOD_MAX) 77 break; 78 div++; 79 if (div >= PERIOD_CDIV_MAX) 80 return -EINVAL; 81 } 82 83 period_cycles = c; 84 c *= state->duty_cycle; 85 do_div(c, state->period); 86 duty_cycles = c; 87 88 /* 89 * The data sheet the says registers must be written to in 90 * this order (ACTIVEn, then PERIODn). Also, the new settings 91 * only take effect at the beginning of a new period, avoiding 92 * glitches. 93 */ 94 95 pol_bits = state->polarity == PWM_POLARITY_NORMAL ? 96 PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; 97 writel(duty_cycles << 16, 98 mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); 99 writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), 100 mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); 101 102 if (state->enabled) { 103 if (!pwm_is_enabled(pwm)) { 104 /* 105 * The clock was enabled above. Just enable 106 * the channel in the control register. 107 */ 108 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); 109 } 110 } else { 111 clk_disable_unprepare(mxs->clk); 112 } 113 return 0; 114 } 115 116 static const struct pwm_ops mxs_pwm_ops = { 117 .apply = mxs_pwm_apply, 118 }; 119 120 static int mxs_pwm_probe(struct platform_device *pdev) 121 { 122 struct device_node *np = pdev->dev.of_node; 123 struct mxs_pwm_chip *mxs; 124 int ret; 125 126 mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL); 127 if (!mxs) 128 return -ENOMEM; 129 130 mxs->base = devm_platform_ioremap_resource(pdev, 0); 131 if (IS_ERR(mxs->base)) 132 return PTR_ERR(mxs->base); 133 134 mxs->clk = devm_clk_get(&pdev->dev, NULL); 135 if (IS_ERR(mxs->clk)) 136 return PTR_ERR(mxs->clk); 137 138 mxs->chip.dev = &pdev->dev; 139 mxs->chip.ops = &mxs_pwm_ops; 140 141 ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm); 142 if (ret < 0) { 143 dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret); 144 return ret; 145 } 146 147 /* FIXME: Only do this if the PWM isn't already running */ 148 ret = stmp_reset_block(mxs->base); 149 if (ret) 150 return dev_err_probe(&pdev->dev, ret, "failed to reset PWM\n"); 151 152 ret = devm_pwmchip_add(&pdev->dev, &mxs->chip); 153 if (ret < 0) { 154 dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); 155 return ret; 156 } 157 158 return 0; 159 } 160 161 static const struct of_device_id mxs_pwm_dt_ids[] = { 162 { .compatible = "fsl,imx23-pwm", }, 163 { /* sentinel */ } 164 }; 165 MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); 166 167 static struct platform_driver mxs_pwm_driver = { 168 .driver = { 169 .name = "mxs-pwm", 170 .of_match_table = mxs_pwm_dt_ids, 171 }, 172 .probe = mxs_pwm_probe, 173 }; 174 module_platform_driver(mxs_pwm_driver); 175 176 MODULE_ALIAS("platform:mxs-pwm"); 177 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 178 MODULE_DESCRIPTION("Freescale MXS PWM Driver"); 179 MODULE_LICENSE("GPL v2"); 180