1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pulse Width Modulator driver 4 * 5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 7 * 8 */ 9 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/slab.h> 20 #include <linux/types.h> 21 22 /* PWM registers and bits definitions */ 23 #define PWMCON 0x00 24 #define PWMHDUR 0x04 25 #define PWMLDUR 0x08 26 #define PWMGDUR 0x0c 27 #define PWMWAVENUM 0x28 28 #define PWMDWIDTH 0x2c 29 #define PWM45DWIDTH_FIXUP 0x30 30 #define PWMTHRES 0x30 31 #define PWM45THRES_FIXUP 0x34 32 #define PWM_CK_26M_SEL 0x210 33 34 #define PWM_CLK_DIV_MAX 7 35 36 struct pwm_mediatek_of_data { 37 unsigned int num_pwms; 38 bool pwm45_fixup; 39 bool has_ck_26m_sel; 40 const unsigned int *reg_offset; 41 }; 42 43 /** 44 * struct pwm_mediatek_chip - struct representing PWM chip 45 * @regs: base address of PWM chip 46 * @clk_top: the top clock generator 47 * @clk_main: the clock used by PWM core 48 * @clk_pwms: the clock used by each PWM channel 49 * @soc: pointer to chip's platform data 50 */ 51 struct pwm_mediatek_chip { 52 void __iomem *regs; 53 struct clk *clk_top; 54 struct clk *clk_main; 55 struct clk **clk_pwms; 56 const struct pwm_mediatek_of_data *soc; 57 }; 58 59 static const unsigned int mtk_pwm_reg_offset_v1[] = { 60 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 61 }; 62 63 static const unsigned int mtk_pwm_reg_offset_v2[] = { 64 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 65 }; 66 67 static inline struct pwm_mediatek_chip * 68 to_pwm_mediatek_chip(struct pwm_chip *chip) 69 { 70 return pwmchip_get_drvdata(chip); 71 } 72 73 static int pwm_mediatek_clk_enable(struct pwm_chip *chip, 74 struct pwm_device *pwm) 75 { 76 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 77 int ret; 78 79 ret = clk_prepare_enable(pc->clk_top); 80 if (ret < 0) 81 return ret; 82 83 ret = clk_prepare_enable(pc->clk_main); 84 if (ret < 0) 85 goto disable_clk_top; 86 87 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); 88 if (ret < 0) 89 goto disable_clk_main; 90 91 return 0; 92 93 disable_clk_main: 94 clk_disable_unprepare(pc->clk_main); 95 disable_clk_top: 96 clk_disable_unprepare(pc->clk_top); 97 98 return ret; 99 } 100 101 static void pwm_mediatek_clk_disable(struct pwm_chip *chip, 102 struct pwm_device *pwm) 103 { 104 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 105 106 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); 107 clk_disable_unprepare(pc->clk_main); 108 clk_disable_unprepare(pc->clk_top); 109 } 110 111 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, 112 unsigned int num, unsigned int offset, 113 u32 value) 114 { 115 writel(value, chip->regs + chip->soc->reg_offset[num] + offset); 116 } 117 118 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 119 int duty_ns, int period_ns) 120 { 121 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 122 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, 123 reg_thres = PWMTHRES; 124 unsigned long clk_rate; 125 u64 resolution; 126 int ret; 127 128 ret = pwm_mediatek_clk_enable(chip, pwm); 129 if (ret < 0) 130 return ret; 131 132 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); 133 if (!clk_rate) { 134 ret = -EINVAL; 135 goto out; 136 } 137 138 /* Make sure we use the bus clock and not the 26MHz clock */ 139 if (pc->soc->has_ck_26m_sel) 140 writel(0, pc->regs + PWM_CK_26M_SEL); 141 142 /* Using resolution in picosecond gets accuracy higher */ 143 resolution = (u64)NSEC_PER_SEC * 1000; 144 do_div(resolution, clk_rate); 145 146 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 147 while (cnt_period > 8191) { 148 resolution *= 2; 149 clkdiv++; 150 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 151 resolution); 152 } 153 154 if (clkdiv > PWM_CLK_DIV_MAX) { 155 dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns); 156 ret = -EINVAL; 157 goto out; 158 } 159 160 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 161 /* 162 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 163 * from the other PWMs on MT7623. 164 */ 165 reg_width = PWM45DWIDTH_FIXUP; 166 reg_thres = PWM45THRES_FIXUP; 167 } 168 169 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 170 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 171 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 172 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 173 174 out: 175 pwm_mediatek_clk_disable(chip, pwm); 176 177 return ret; 178 } 179 180 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) 181 { 182 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 183 u32 value; 184 int ret; 185 186 ret = pwm_mediatek_clk_enable(chip, pwm); 187 if (ret < 0) 188 return ret; 189 190 value = readl(pc->regs); 191 value |= BIT(pwm->hwpwm); 192 writel(value, pc->regs); 193 194 return 0; 195 } 196 197 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) 198 { 199 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 200 u32 value; 201 202 value = readl(pc->regs); 203 value &= ~BIT(pwm->hwpwm); 204 writel(value, pc->regs); 205 206 pwm_mediatek_clk_disable(chip, pwm); 207 } 208 209 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, 210 const struct pwm_state *state) 211 { 212 int err; 213 214 if (state->polarity != PWM_POLARITY_NORMAL) 215 return -EINVAL; 216 217 if (!state->enabled) { 218 if (pwm->state.enabled) 219 pwm_mediatek_disable(chip, pwm); 220 221 return 0; 222 } 223 224 err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period); 225 if (err) 226 return err; 227 228 if (!pwm->state.enabled) 229 err = pwm_mediatek_enable(chip, pwm); 230 231 return err; 232 } 233 234 static const struct pwm_ops pwm_mediatek_ops = { 235 .apply = pwm_mediatek_apply, 236 }; 237 238 static int pwm_mediatek_probe(struct platform_device *pdev) 239 { 240 struct pwm_chip *chip; 241 struct pwm_mediatek_chip *pc; 242 const struct pwm_mediatek_of_data *soc; 243 unsigned int i; 244 int ret; 245 246 soc = of_device_get_match_data(&pdev->dev); 247 248 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, sizeof(*pc)); 249 if (IS_ERR(chip)) 250 return PTR_ERR(chip); 251 pc = to_pwm_mediatek_chip(chip); 252 253 pc->soc = soc; 254 255 pc->regs = devm_platform_ioremap_resource(pdev, 0); 256 if (IS_ERR(pc->regs)) 257 return PTR_ERR(pc->regs); 258 259 pc->clk_pwms = devm_kmalloc_array(&pdev->dev, soc->num_pwms, 260 sizeof(*pc->clk_pwms), GFP_KERNEL); 261 if (!pc->clk_pwms) 262 return -ENOMEM; 263 264 pc->clk_top = devm_clk_get(&pdev->dev, "top"); 265 if (IS_ERR(pc->clk_top)) 266 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top), 267 "Failed to get top clock\n"); 268 269 pc->clk_main = devm_clk_get(&pdev->dev, "main"); 270 if (IS_ERR(pc->clk_main)) 271 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), 272 "Failed to get main clock\n"); 273 274 for (i = 0; i < soc->num_pwms; i++) { 275 char name[8]; 276 277 snprintf(name, sizeof(name), "pwm%d", i + 1); 278 279 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); 280 if (IS_ERR(pc->clk_pwms[i])) 281 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]), 282 "Failed to get %s clock\n", name); 283 } 284 285 chip->ops = &pwm_mediatek_ops; 286 287 ret = devm_pwmchip_add(&pdev->dev, chip); 288 if (ret < 0) 289 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); 290 291 return 0; 292 } 293 294 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 295 .num_pwms = 8, 296 .pwm45_fixup = false, 297 .has_ck_26m_sel = false, 298 .reg_offset = mtk_pwm_reg_offset_v1, 299 }; 300 301 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 302 .num_pwms = 7, 303 .pwm45_fixup = false, 304 .has_ck_26m_sel = false, 305 .reg_offset = mtk_pwm_reg_offset_v1, 306 }; 307 308 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 309 .num_pwms = 6, 310 .pwm45_fixup = false, 311 .has_ck_26m_sel = true, 312 .reg_offset = mtk_pwm_reg_offset_v1, 313 }; 314 315 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 316 .num_pwms = 5, 317 .pwm45_fixup = true, 318 .has_ck_26m_sel = false, 319 .reg_offset = mtk_pwm_reg_offset_v1, 320 }; 321 322 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 323 .num_pwms = 4, 324 .pwm45_fixup = true, 325 .has_ck_26m_sel = false, 326 .reg_offset = mtk_pwm_reg_offset_v1, 327 }; 328 329 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 330 .num_pwms = 1, 331 .pwm45_fixup = false, 332 .has_ck_26m_sel = false, 333 .reg_offset = mtk_pwm_reg_offset_v1, 334 }; 335 336 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 337 .num_pwms = 3, 338 .pwm45_fixup = false, 339 .has_ck_26m_sel = true, 340 .reg_offset = mtk_pwm_reg_offset_v2, 341 }; 342 343 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 344 .num_pwms = 2, 345 .pwm45_fixup = false, 346 .has_ck_26m_sel = true, 347 .reg_offset = mtk_pwm_reg_offset_v1, 348 }; 349 350 static const struct pwm_mediatek_of_data mt7988_pwm_data = { 351 .num_pwms = 8, 352 .pwm45_fixup = false, 353 .has_ck_26m_sel = false, 354 .reg_offset = mtk_pwm_reg_offset_v2, 355 }; 356 357 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 358 .num_pwms = 4, 359 .pwm45_fixup = false, 360 .has_ck_26m_sel = true, 361 .reg_offset = mtk_pwm_reg_offset_v1, 362 }; 363 364 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 365 .num_pwms = 3, 366 .pwm45_fixup = false, 367 .has_ck_26m_sel = true, 368 .reg_offset = mtk_pwm_reg_offset_v1, 369 }; 370 371 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 372 .num_pwms = 5, 373 .pwm45_fixup = false, 374 .has_ck_26m_sel = true, 375 .reg_offset = mtk_pwm_reg_offset_v1, 376 }; 377 378 static const struct of_device_id pwm_mediatek_of_match[] = { 379 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 380 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data }, 381 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 382 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 383 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 384 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 385 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, 386 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 387 { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, 388 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 389 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, 390 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, 391 { }, 392 }; 393 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); 394 395 static struct platform_driver pwm_mediatek_driver = { 396 .driver = { 397 .name = "pwm-mediatek", 398 .of_match_table = pwm_mediatek_of_match, 399 }, 400 .probe = pwm_mediatek_probe, 401 }; 402 module_platform_driver(pwm_mediatek_driver); 403 404 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 405 MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver"); 406 MODULE_LICENSE("GPL v2"); 407