1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pulse Width Modulator driver 4 * 5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 7 * 8 */ 9 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/clk.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pwm.h> 20 #include <linux/slab.h> 21 #include <linux/types.h> 22 23 /* PWM registers and bits definitions */ 24 #define PWMCON 0x00 25 #define PWMHDUR 0x04 26 #define PWMLDUR 0x08 27 #define PWMGDUR 0x0c 28 #define PWMWAVENUM 0x28 29 #define PWMDWIDTH 0x2c 30 #define PWM45DWIDTH_FIXUP 0x30 31 #define PWMTHRES 0x30 32 #define PWM45THRES_FIXUP 0x34 33 34 #define PWM_CLK_DIV_MAX 7 35 36 struct pwm_mediatek_of_data { 37 unsigned int num_pwms; 38 bool pwm45_fixup; 39 }; 40 41 /** 42 * struct pwm_mediatek_chip - struct representing PWM chip 43 * @chip: linux PWM chip representation 44 * @regs: base address of PWM chip 45 * @clk_top: the top clock generator 46 * @clk_main: the clock used by PWM core 47 * @clk_pwms: the clock used by each PWM channel 48 * @clk_freq: the fix clock frequency of legacy MIPS SoC 49 */ 50 struct pwm_mediatek_chip { 51 struct pwm_chip chip; 52 void __iomem *regs; 53 struct clk *clk_top; 54 struct clk *clk_main; 55 struct clk **clk_pwms; 56 const struct pwm_mediatek_of_data *soc; 57 }; 58 59 static const unsigned int pwm_mediatek_reg_offset[] = { 60 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 61 }; 62 63 static inline struct pwm_mediatek_chip * 64 to_pwm_mediatek_chip(struct pwm_chip *chip) 65 { 66 return container_of(chip, struct pwm_mediatek_chip, chip); 67 } 68 69 static int pwm_mediatek_clk_enable(struct pwm_chip *chip, 70 struct pwm_device *pwm) 71 { 72 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 73 int ret; 74 75 ret = clk_prepare_enable(pc->clk_top); 76 if (ret < 0) 77 return ret; 78 79 ret = clk_prepare_enable(pc->clk_main); 80 if (ret < 0) 81 goto disable_clk_top; 82 83 ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); 84 if (ret < 0) 85 goto disable_clk_main; 86 87 return 0; 88 89 disable_clk_main: 90 clk_disable_unprepare(pc->clk_main); 91 disable_clk_top: 92 clk_disable_unprepare(pc->clk_top); 93 94 return ret; 95 } 96 97 static void pwm_mediatek_clk_disable(struct pwm_chip *chip, 98 struct pwm_device *pwm) 99 { 100 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 101 102 clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); 103 clk_disable_unprepare(pc->clk_main); 104 clk_disable_unprepare(pc->clk_top); 105 } 106 107 static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, 108 unsigned int num, unsigned int offset) 109 { 110 return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset); 111 } 112 113 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, 114 unsigned int num, unsigned int offset, 115 u32 value) 116 { 117 writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); 118 } 119 120 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 121 int duty_ns, int period_ns) 122 { 123 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 124 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, 125 reg_thres = PWMTHRES; 126 u64 resolution; 127 int ret; 128 129 ret = pwm_mediatek_clk_enable(chip, pwm); 130 131 if (ret < 0) 132 return ret; 133 134 /* Using resolution in picosecond gets accuracy higher */ 135 resolution = (u64)NSEC_PER_SEC * 1000; 136 do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); 137 138 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 139 while (cnt_period > 8191) { 140 resolution *= 2; 141 clkdiv++; 142 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 143 resolution); 144 } 145 146 if (clkdiv > PWM_CLK_DIV_MAX) { 147 pwm_mediatek_clk_disable(chip, pwm); 148 dev_err(chip->dev, "period %d not supported\n", period_ns); 149 return -EINVAL; 150 } 151 152 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 153 /* 154 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 155 * from the other PWMs on MT7623. 156 */ 157 reg_width = PWM45DWIDTH_FIXUP; 158 reg_thres = PWM45THRES_FIXUP; 159 } 160 161 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 162 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 163 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 164 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 165 166 pwm_mediatek_clk_disable(chip, pwm); 167 168 return 0; 169 } 170 171 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) 172 { 173 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 174 u32 value; 175 int ret; 176 177 ret = pwm_mediatek_clk_enable(chip, pwm); 178 if (ret < 0) 179 return ret; 180 181 value = readl(pc->regs); 182 value |= BIT(pwm->hwpwm); 183 writel(value, pc->regs); 184 185 return 0; 186 } 187 188 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) 189 { 190 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 191 u32 value; 192 193 value = readl(pc->regs); 194 value &= ~BIT(pwm->hwpwm); 195 writel(value, pc->regs); 196 197 pwm_mediatek_clk_disable(chip, pwm); 198 } 199 200 static const struct pwm_ops pwm_mediatek_ops = { 201 .config = pwm_mediatek_config, 202 .enable = pwm_mediatek_enable, 203 .disable = pwm_mediatek_disable, 204 .owner = THIS_MODULE, 205 }; 206 207 static int pwm_mediatek_probe(struct platform_device *pdev) 208 { 209 struct pwm_mediatek_chip *pc; 210 struct resource *res; 211 unsigned int i; 212 int ret; 213 214 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 215 if (!pc) 216 return -ENOMEM; 217 218 pc->soc = of_device_get_match_data(&pdev->dev); 219 220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 221 pc->regs = devm_ioremap_resource(&pdev->dev, res); 222 if (IS_ERR(pc->regs)) 223 return PTR_ERR(pc->regs); 224 225 pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms, 226 sizeof(*pc->clk_pwms), GFP_KERNEL); 227 if (!pc->clk_pwms) 228 return -ENOMEM; 229 230 pc->clk_top = devm_clk_get(&pdev->dev, "top"); 231 if (IS_ERR(pc->clk_top)) { 232 dev_err(&pdev->dev, "clock: top fail: %ld\n", 233 PTR_ERR(pc->clk_top)); 234 return PTR_ERR(pc->clk_top); 235 } 236 237 pc->clk_main = devm_clk_get(&pdev->dev, "main"); 238 if (IS_ERR(pc->clk_main)) { 239 dev_err(&pdev->dev, "clock: main fail: %ld\n", 240 PTR_ERR(pc->clk_main)); 241 return PTR_ERR(pc->clk_main); 242 } 243 244 for (i = 0; i < pc->soc->num_pwms; i++) { 245 char name[8]; 246 247 snprintf(name, sizeof(name), "pwm%d", i + 1); 248 249 pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); 250 if (IS_ERR(pc->clk_pwms[i])) { 251 dev_err(&pdev->dev, "clock: %s fail: %ld\n", 252 name, PTR_ERR(pc->clk_pwms[i])); 253 return PTR_ERR(pc->clk_pwms[i]); 254 } 255 } 256 257 platform_set_drvdata(pdev, pc); 258 259 pc->chip.dev = &pdev->dev; 260 pc->chip.ops = &pwm_mediatek_ops; 261 pc->chip.base = -1; 262 pc->chip.npwm = pc->soc->num_pwms; 263 264 ret = pwmchip_add(&pc->chip); 265 if (ret < 0) { 266 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 267 return ret; 268 } 269 270 return 0; 271 } 272 273 static int pwm_mediatek_remove(struct platform_device *pdev) 274 { 275 struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev); 276 277 return pwmchip_remove(&pc->chip); 278 } 279 280 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 281 .num_pwms = 8, 282 .pwm45_fixup = false, 283 }; 284 285 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 286 .num_pwms = 6, 287 .pwm45_fixup = false, 288 }; 289 290 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 291 .num_pwms = 5, 292 .pwm45_fixup = true, 293 }; 294 295 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 296 .num_pwms = 4, 297 .pwm45_fixup = true, 298 }; 299 300 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 301 .num_pwms = 1, 302 .pwm45_fixup = false, 303 }; 304 305 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 306 .num_pwms = 5, 307 .pwm45_fixup = false, 308 }; 309 310 static const struct of_device_id pwm_mediatek_of_match[] = { 311 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 312 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 313 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 314 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 315 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 316 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, 317 { }, 318 }; 319 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); 320 321 static struct platform_driver pwm_mediatek_driver = { 322 .driver = { 323 .name = "pwm-mediatek", 324 .of_match_table = pwm_mediatek_of_match, 325 }, 326 .probe = pwm_mediatek_probe, 327 .remove = pwm_mediatek_remove, 328 }; 329 module_platform_driver(pwm_mediatek_driver); 330 331 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 332 MODULE_LICENSE("GPL v2"); 333