1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek Pulse Width Modulator driver 4 * 5 * Copyright (C) 2015 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2017 Zhi Mao <zhi.mao@mediatek.com> 7 * 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/ioport.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pwm.h> 20 #include <linux/slab.h> 21 #include <linux/types.h> 22 23 /* PWM registers and bits definitions */ 24 #define PWMCON 0x00 25 #define PWMCON_CLKDIV GENMASK(2, 0) 26 #define PWMHDUR 0x04 27 #define PWMLDUR 0x08 28 #define PWMGDUR 0x0c 29 #define PWMWAVENUM 0x28 30 #define PWMDWIDTH 0x2c 31 #define PWMDWIDTH_PERIOD GENMASK(12, 0) 32 #define PWM45DWIDTH_FIXUP 0x30 33 #define PWMTHRES 0x30 34 #define PWMTHRES_DUTY GENMASK(12, 0) 35 #define PWM45THRES_FIXUP 0x34 36 #define PWM_CK_26M_SEL_V3 0x74 37 #define PWM_CK_26M_SEL 0x210 38 39 struct pwm_mediatek_of_data { 40 unsigned int num_pwms; 41 bool pwm45_fixup; 42 u16 pwm_ck_26m_sel_reg; 43 unsigned int chanreg_base; 44 unsigned int chanreg_width; 45 }; 46 47 /** 48 * struct pwm_mediatek_chip - struct representing PWM chip 49 * @regs: base address of PWM chip 50 * @clk_top: the top clock generator 51 * @clk_main: the clock used by PWM core 52 * @soc: pointer to chip's platform data 53 * @clk_pwms: the clock and clkrate used by each PWM channel 54 */ 55 struct pwm_mediatek_chip { 56 void __iomem *regs; 57 struct clk *clk_top; 58 struct clk *clk_main; 59 const struct pwm_mediatek_of_data *soc; 60 struct { 61 struct clk *clk; 62 unsigned long rate; 63 } clk_pwms[]; 64 }; 65 66 static inline struct pwm_mediatek_chip * 67 to_pwm_mediatek_chip(struct pwm_chip *chip) 68 { 69 return pwmchip_get_drvdata(chip); 70 } 71 72 static int pwm_mediatek_clk_enable(struct pwm_mediatek_chip *pc, 73 unsigned int hwpwm) 74 { 75 int ret; 76 77 ret = clk_prepare_enable(pc->clk_top); 78 if (ret < 0) 79 return ret; 80 81 ret = clk_prepare_enable(pc->clk_main); 82 if (ret < 0) 83 goto disable_clk_top; 84 85 ret = clk_prepare_enable(pc->clk_pwms[hwpwm].clk); 86 if (ret < 0) 87 goto disable_clk_main; 88 89 if (!pc->clk_pwms[hwpwm].rate) { 90 pc->clk_pwms[hwpwm].rate = clk_get_rate(pc->clk_pwms[hwpwm].clk); 91 92 /* 93 * With the clk running with not more than 1 GHz the 94 * calculations in .apply() won't overflow. 95 */ 96 if (!pc->clk_pwms[hwpwm].rate || 97 pc->clk_pwms[hwpwm].rate > 1000000000) { 98 ret = -EINVAL; 99 goto disable_clk_hwpwm; 100 } 101 } 102 103 return 0; 104 105 disable_clk_hwpwm: 106 clk_disable_unprepare(pc->clk_pwms[hwpwm].clk); 107 disable_clk_main: 108 clk_disable_unprepare(pc->clk_main); 109 disable_clk_top: 110 clk_disable_unprepare(pc->clk_top); 111 112 return ret; 113 } 114 115 static void pwm_mediatek_clk_disable(struct pwm_mediatek_chip *pc, 116 unsigned int hwpwm) 117 { 118 clk_disable_unprepare(pc->clk_pwms[hwpwm].clk); 119 clk_disable_unprepare(pc->clk_main); 120 clk_disable_unprepare(pc->clk_top); 121 } 122 123 static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, 124 unsigned int num, unsigned int offset, 125 u32 value) 126 { 127 writel(value, chip->regs + chip->soc->chanreg_base + 128 num * chip->soc->chanreg_width + offset); 129 } 130 131 static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, 132 unsigned int num, unsigned int offset) 133 { 134 return readl(chip->regs + chip->soc->chanreg_base + 135 num * chip->soc->chanreg_width + offset); 136 } 137 138 static void pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) 139 { 140 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 141 u32 value; 142 143 value = readl(pc->regs); 144 value |= BIT(pwm->hwpwm); 145 writel(value, pc->regs); 146 } 147 148 static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) 149 { 150 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 151 u32 value; 152 153 value = readl(pc->regs); 154 value &= ~BIT(pwm->hwpwm); 155 writel(value, pc->regs); 156 } 157 158 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 159 u64 duty_ns, u64 period_ns) 160 { 161 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 162 u32 clkdiv, enable; 163 u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES; 164 u64 cnt_period, cnt_duty; 165 unsigned long clk_rate; 166 int ret; 167 168 ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm); 169 if (ret < 0) 170 return ret; 171 172 clk_rate = pc->clk_pwms[pwm->hwpwm].rate; 173 174 /* Make sure we use the bus clock and not the 26MHz clock */ 175 if (pc->soc->pwm_ck_26m_sel_reg) 176 writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg); 177 178 cnt_period = mul_u64_u64_div_u64(period_ns, clk_rate, NSEC_PER_SEC); 179 if (cnt_period == 0) { 180 ret = -ERANGE; 181 goto out; 182 } 183 184 if (cnt_period > FIELD_MAX(PWMDWIDTH_PERIOD) + 1) { 185 if (cnt_period >= ((FIELD_MAX(PWMDWIDTH_PERIOD) + 1) << FIELD_MAX(PWMCON_CLKDIV))) { 186 clkdiv = FIELD_MAX(PWMCON_CLKDIV); 187 cnt_period = FIELD_MAX(PWMDWIDTH_PERIOD) + 1; 188 } else { 189 clkdiv = ilog2(cnt_period) - ilog2(FIELD_MAX(PWMDWIDTH_PERIOD)); 190 cnt_period >>= clkdiv; 191 } 192 } else { 193 clkdiv = 0; 194 } 195 196 cnt_duty = mul_u64_u64_div_u64(duty_ns, clk_rate, NSEC_PER_SEC) >> clkdiv; 197 if (cnt_duty > cnt_period) 198 cnt_duty = cnt_period; 199 200 if (cnt_duty) { 201 cnt_duty -= 1; 202 enable = BIT(pwm->hwpwm); 203 } else { 204 enable = 0; 205 } 206 207 cnt_period -= 1; 208 209 dev_dbg(&chip->dev, "pwm#%u: %lld/%lld @%lu -> CON: %x, PERIOD: %llx, DUTY: %llx\n", 210 pwm->hwpwm, duty_ns, period_ns, clk_rate, clkdiv, cnt_period, cnt_duty); 211 212 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 213 /* 214 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 215 * from the other PWMs on MT7623. 216 */ 217 reg_width = PWM45DWIDTH_FIXUP; 218 reg_thres = PWM45THRES_FIXUP; 219 } 220 221 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 222 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 223 224 if (enable) { 225 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 226 pwm_mediatek_enable(chip, pwm); 227 } else { 228 pwm_mediatek_disable(chip, pwm); 229 } 230 231 out: 232 pwm_mediatek_clk_disable(pc, pwm->hwpwm); 233 234 return ret; 235 } 236 237 static int pwm_mediatek_apply(struct pwm_chip *chip, struct pwm_device *pwm, 238 const struct pwm_state *state) 239 { 240 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 241 int err; 242 243 if (state->polarity != PWM_POLARITY_NORMAL) 244 return -EINVAL; 245 246 if (!state->enabled) { 247 if (pwm->state.enabled) { 248 pwm_mediatek_disable(chip, pwm); 249 pwm_mediatek_clk_disable(pc, pwm->hwpwm); 250 } 251 252 return 0; 253 } 254 255 err = pwm_mediatek_config(chip, pwm, state->duty_cycle, state->period); 256 if (err) 257 return err; 258 259 if (!pwm->state.enabled) 260 err = pwm_mediatek_clk_enable(pc, pwm->hwpwm); 261 262 return err; 263 } 264 265 static int pwm_mediatek_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 266 struct pwm_state *state) 267 { 268 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 269 int ret; 270 u32 enable; 271 u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES; 272 273 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 274 /* 275 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 276 * from the other PWMs on MT7623. 277 */ 278 reg_width = PWM45DWIDTH_FIXUP; 279 reg_thres = PWM45THRES_FIXUP; 280 } 281 282 ret = pwm_mediatek_clk_enable(pc, pwm->hwpwm); 283 if (ret < 0) 284 return ret; 285 286 enable = readl(pc->regs); 287 if (enable & BIT(pwm->hwpwm)) { 288 u32 clkdiv, cnt_period, cnt_duty; 289 unsigned long clk_rate; 290 291 clk_rate = pc->clk_pwms[pwm->hwpwm].rate; 292 293 state->enabled = true; 294 state->polarity = PWM_POLARITY_NORMAL; 295 296 clkdiv = FIELD_GET(PWMCON_CLKDIV, 297 pwm_mediatek_readl(pc, pwm->hwpwm, PWMCON)); 298 cnt_period = FIELD_GET(PWMDWIDTH_PERIOD, 299 pwm_mediatek_readl(pc, pwm->hwpwm, reg_width)); 300 cnt_duty = FIELD_GET(PWMTHRES_DUTY, 301 pwm_mediatek_readl(pc, pwm->hwpwm, reg_thres)); 302 303 /* 304 * cnt_period is a 13 bit value, NSEC_PER_SEC is 30 bits wide 305 * and clkdiv is less than 8, so the multiplication doesn't 306 * overflow an u64. 307 */ 308 state->period = 309 DIV_ROUND_UP_ULL((u64)cnt_period * NSEC_PER_SEC << clkdiv, clk_rate); 310 state->duty_cycle = 311 DIV_ROUND_UP_ULL((u64)cnt_duty * NSEC_PER_SEC << clkdiv, clk_rate); 312 } else { 313 state->enabled = false; 314 } 315 316 pwm_mediatek_clk_disable(pc, pwm->hwpwm); 317 318 return ret; 319 } 320 321 static const struct pwm_ops pwm_mediatek_ops = { 322 .apply = pwm_mediatek_apply, 323 .get_state = pwm_mediatek_get_state, 324 }; 325 326 static int pwm_mediatek_init_used_clks(struct pwm_mediatek_chip *pc) 327 { 328 const struct pwm_mediatek_of_data *soc = pc->soc; 329 unsigned int hwpwm; 330 u32 enabled, handled = 0; 331 int ret; 332 333 ret = clk_prepare_enable(pc->clk_top); 334 if (ret) 335 return ret; 336 337 ret = clk_prepare_enable(pc->clk_main); 338 if (ret) 339 goto err_enable_main; 340 341 enabled = readl(pc->regs) & GENMASK(soc->num_pwms - 1, 0); 342 343 while (enabled & ~handled) { 344 hwpwm = ilog2(enabled & ~handled); 345 346 ret = pwm_mediatek_clk_enable(pc, hwpwm); 347 if (ret) { 348 while (handled) { 349 hwpwm = ilog2(handled); 350 351 pwm_mediatek_clk_disable(pc, hwpwm); 352 handled &= ~BIT(hwpwm); 353 } 354 355 break; 356 } 357 358 handled |= BIT(hwpwm); 359 } 360 361 clk_disable_unprepare(pc->clk_main); 362 err_enable_main: 363 364 clk_disable_unprepare(pc->clk_top); 365 366 return ret; 367 } 368 369 static int pwm_mediatek_probe(struct platform_device *pdev) 370 { 371 struct pwm_chip *chip; 372 struct pwm_mediatek_chip *pc; 373 const struct pwm_mediatek_of_data *soc; 374 unsigned int i; 375 int ret; 376 377 soc = of_device_get_match_data(&pdev->dev); 378 379 chip = devm_pwmchip_alloc(&pdev->dev, soc->num_pwms, 380 sizeof(*pc) + soc->num_pwms * sizeof(*pc->clk_pwms)); 381 if (IS_ERR(chip)) 382 return PTR_ERR(chip); 383 pc = to_pwm_mediatek_chip(chip); 384 385 pc->soc = soc; 386 387 pc->regs = devm_platform_ioremap_resource(pdev, 0); 388 if (IS_ERR(pc->regs)) 389 return PTR_ERR(pc->regs); 390 391 pc->clk_top = devm_clk_get(&pdev->dev, "top"); 392 if (IS_ERR(pc->clk_top)) 393 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top), 394 "Failed to get top clock\n"); 395 396 pc->clk_main = devm_clk_get(&pdev->dev, "main"); 397 if (IS_ERR(pc->clk_main)) 398 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main), 399 "Failed to get main clock\n"); 400 401 for (i = 0; i < soc->num_pwms; i++) { 402 char name[8]; 403 404 snprintf(name, sizeof(name), "pwm%d", i + 1); 405 406 pc->clk_pwms[i].clk = devm_clk_get(&pdev->dev, name); 407 if (IS_ERR(pc->clk_pwms[i].clk)) 408 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i].clk), 409 "Failed to get %s clock\n", name); 410 411 ret = devm_clk_rate_exclusive_get(&pdev->dev, pc->clk_pwms[i].clk); 412 if (ret) 413 return dev_err_probe(&pdev->dev, ret, 414 "Failed to lock clock rate for %s\n", name); 415 } 416 417 ret = pwm_mediatek_init_used_clks(pc); 418 if (ret) 419 return dev_err_probe(&pdev->dev, ret, "Failed to initialize used clocks\n"); 420 421 chip->ops = &pwm_mediatek_ops; 422 423 ret = devm_pwmchip_add(&pdev->dev, chip); 424 if (ret < 0) 425 return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n"); 426 427 return 0; 428 } 429 430 static const struct pwm_mediatek_of_data mt2712_pwm_data = { 431 .num_pwms = 8, 432 .pwm45_fixup = false, 433 .chanreg_base = 0x10, 434 .chanreg_width = 0x40, 435 }; 436 437 static const struct pwm_mediatek_of_data mt6795_pwm_data = { 438 .num_pwms = 7, 439 .pwm45_fixup = false, 440 .chanreg_base = 0x10, 441 .chanreg_width = 0x40, 442 }; 443 444 static const struct pwm_mediatek_of_data mt7622_pwm_data = { 445 .num_pwms = 6, 446 .pwm45_fixup = false, 447 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 448 .chanreg_base = 0x10, 449 .chanreg_width = 0x40, 450 }; 451 452 static const struct pwm_mediatek_of_data mt7623_pwm_data = { 453 .num_pwms = 5, 454 .pwm45_fixup = true, 455 .chanreg_base = 0x10, 456 .chanreg_width = 0x40, 457 }; 458 459 static const struct pwm_mediatek_of_data mt7628_pwm_data = { 460 .num_pwms = 4, 461 .pwm45_fixup = true, 462 .chanreg_base = 0x10, 463 .chanreg_width = 0x40, 464 }; 465 466 static const struct pwm_mediatek_of_data mt7629_pwm_data = { 467 .num_pwms = 1, 468 .pwm45_fixup = false, 469 .chanreg_base = 0x10, 470 .chanreg_width = 0x40, 471 }; 472 473 static const struct pwm_mediatek_of_data mt7981_pwm_data = { 474 .num_pwms = 3, 475 .pwm45_fixup = false, 476 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 477 .chanreg_base = 0x80, 478 .chanreg_width = 0x40, 479 }; 480 481 static const struct pwm_mediatek_of_data mt7986_pwm_data = { 482 .num_pwms = 2, 483 .pwm45_fixup = false, 484 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 485 .chanreg_base = 0x10, 486 .chanreg_width = 0x40, 487 }; 488 489 static const struct pwm_mediatek_of_data mt7988_pwm_data = { 490 .num_pwms = 8, 491 .pwm45_fixup = false, 492 .chanreg_base = 0x80, 493 .chanreg_width = 0x40, 494 }; 495 496 static const struct pwm_mediatek_of_data mt8183_pwm_data = { 497 .num_pwms = 4, 498 .pwm45_fixup = false, 499 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 500 .chanreg_base = 0x10, 501 .chanreg_width = 0x40, 502 }; 503 504 static const struct pwm_mediatek_of_data mt8365_pwm_data = { 505 .num_pwms = 3, 506 .pwm45_fixup = false, 507 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 508 .chanreg_base = 0x10, 509 .chanreg_width = 0x40, 510 }; 511 512 static const struct pwm_mediatek_of_data mt8516_pwm_data = { 513 .num_pwms = 5, 514 .pwm45_fixup = false, 515 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL, 516 .chanreg_base = 0x10, 517 .chanreg_width = 0x40, 518 }; 519 520 static const struct pwm_mediatek_of_data mt6991_pwm_data = { 521 .num_pwms = 4, 522 .pwm45_fixup = false, 523 .pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3, 524 .chanreg_base = 0x100, 525 .chanreg_width = 0x100, 526 }; 527 528 static const struct of_device_id pwm_mediatek_of_match[] = { 529 { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, 530 { .compatible = "mediatek,mt6795-pwm", .data = &mt6795_pwm_data }, 531 { .compatible = "mediatek,mt6991-pwm", .data = &mt6991_pwm_data }, 532 { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, 533 { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, 534 { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, 535 { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, 536 { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data }, 537 { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, 538 { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data }, 539 { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, 540 { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, 541 { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, 542 { }, 543 }; 544 MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); 545 546 static struct platform_driver pwm_mediatek_driver = { 547 .driver = { 548 .name = "pwm-mediatek", 549 .of_match_table = pwm_mediatek_of_match, 550 }, 551 .probe = pwm_mediatek_probe, 552 }; 553 module_platform_driver(pwm_mediatek_driver); 554 555 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 556 MODULE_DESCRIPTION("MediaTek general purpose Pulse Width Modulator driver"); 557 MODULE_LICENSE("GPL v2"); 558