1 /* 2 * Intel Low Power Subsystem PWM controller driver 3 * 4 * Copyright (C) 2014, Intel Corporation 5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 6 * Author: Chew Kean Ho <kean.ho.chew@intel.com> 7 * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> 8 * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> 9 * Author: Alan Cox <alan@linux.intel.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/time.h> 22 23 #include "pwm-lpss.h" 24 25 #define PWM 0x00000000 26 #define PWM_ENABLE BIT(31) 27 #define PWM_SW_UPDATE BIT(30) 28 #define PWM_BASE_UNIT_SHIFT 8 29 #define PWM_ON_TIME_DIV_MASK 0x000000ff 30 31 /* Size of each PWM register space if multiple */ 32 #define PWM_SIZE 0x400 33 34 struct pwm_lpss_chip { 35 struct pwm_chip chip; 36 void __iomem *regs; 37 const struct pwm_lpss_boardinfo *info; 38 }; 39 40 /* BayTrail */ 41 const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { 42 .clk_rate = 25000000, 43 .npwm = 1, 44 .base_unit_bits = 16, 45 }; 46 EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); 47 48 /* Braswell */ 49 const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { 50 .clk_rate = 19200000, 51 .npwm = 1, 52 .base_unit_bits = 16, 53 }; 54 EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); 55 56 /* Broxton */ 57 const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { 58 .clk_rate = 19200000, 59 .npwm = 4, 60 .base_unit_bits = 22, 61 }; 62 EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info); 63 64 static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) 65 { 66 return container_of(chip, struct pwm_lpss_chip, chip); 67 } 68 69 static inline u32 pwm_lpss_read(const struct pwm_device *pwm) 70 { 71 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); 72 73 return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); 74 } 75 76 static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) 77 { 78 struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); 79 80 writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); 81 } 82 83 static void pwm_lpss_update(struct pwm_device *pwm) 84 { 85 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE); 86 /* Give it some time to propagate */ 87 usleep_range(10, 50); 88 } 89 90 static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, 91 int duty_ns, int period_ns) 92 { 93 struct pwm_lpss_chip *lpwm = to_lpwm(chip); 94 unsigned long long on_time_div; 95 unsigned long c = lpwm->info->clk_rate, base_unit_range; 96 unsigned long long base_unit, freq = NSEC_PER_SEC; 97 u32 ctrl; 98 99 do_div(freq, period_ns); 100 101 /* 102 * The equation is: 103 * base_unit = round(base_unit_range * freq / c) 104 */ 105 base_unit_range = BIT(lpwm->info->base_unit_bits); 106 freq *= base_unit_range; 107 108 base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); 109 110 if (duty_ns <= 0) 111 duty_ns = 1; 112 on_time_div = 255ULL * duty_ns; 113 do_div(on_time_div, period_ns); 114 on_time_div = 255ULL - on_time_div; 115 116 pm_runtime_get_sync(chip->dev); 117 118 ctrl = pwm_lpss_read(pwm); 119 ctrl &= ~PWM_ON_TIME_DIV_MASK; 120 ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); 121 base_unit &= (base_unit_range - 1); 122 ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; 123 ctrl |= on_time_div; 124 pwm_lpss_write(pwm, ctrl); 125 126 /* 127 * If the PWM is already enabled we need to notify the hardware 128 * about the change by setting PWM_SW_UPDATE. 129 */ 130 if (pwm_is_enabled(pwm)) 131 pwm_lpss_update(pwm); 132 133 pm_runtime_put(chip->dev); 134 135 return 0; 136 } 137 138 static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) 139 { 140 pm_runtime_get_sync(chip->dev); 141 142 /* 143 * Hardware must first see PWM_SW_UPDATE before the PWM can be 144 * enabled. 145 */ 146 pwm_lpss_update(pwm); 147 pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); 148 return 0; 149 } 150 151 static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) 152 { 153 pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); 154 pm_runtime_put(chip->dev); 155 } 156 157 static const struct pwm_ops pwm_lpss_ops = { 158 .config = pwm_lpss_config, 159 .enable = pwm_lpss_enable, 160 .disable = pwm_lpss_disable, 161 .owner = THIS_MODULE, 162 }; 163 164 struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, 165 const struct pwm_lpss_boardinfo *info) 166 { 167 struct pwm_lpss_chip *lpwm; 168 unsigned long c; 169 int ret; 170 171 lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); 172 if (!lpwm) 173 return ERR_PTR(-ENOMEM); 174 175 lpwm->regs = devm_ioremap_resource(dev, r); 176 if (IS_ERR(lpwm->regs)) 177 return ERR_CAST(lpwm->regs); 178 179 lpwm->info = info; 180 181 c = lpwm->info->clk_rate; 182 if (!c) 183 return ERR_PTR(-EINVAL); 184 185 lpwm->chip.dev = dev; 186 lpwm->chip.ops = &pwm_lpss_ops; 187 lpwm->chip.base = -1; 188 lpwm->chip.npwm = info->npwm; 189 190 ret = pwmchip_add(&lpwm->chip); 191 if (ret) { 192 dev_err(dev, "failed to add PWM chip: %d\n", ret); 193 return ERR_PTR(ret); 194 } 195 196 return lpwm; 197 } 198 EXPORT_SYMBOL_GPL(pwm_lpss_probe); 199 200 int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) 201 { 202 return pwmchip_remove(&lpwm->chip); 203 } 204 EXPORT_SYMBOL_GPL(pwm_lpss_remove); 205 206 MODULE_DESCRIPTION("PWM driver for Intel LPSS"); 207 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 208 MODULE_LICENSE("GPL v2"); 209