1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * simple driver for PWM (Pulse Width Modulator) controller 4 * 5 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> 6 * 7 * Limitations: 8 * - When disabled the output is driven to 0 independent of the configured 9 * polarity. 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/bitops.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pwm.h> 23 #include <linux/slab.h> 24 25 #define MX3_PWMCR 0x00 /* PWM Control Register */ 26 #define MX3_PWMSR 0x04 /* PWM Status Register */ 27 #define MX3_PWMSAR 0x0C /* PWM Sample Register */ 28 #define MX3_PWMPR 0x10 /* PWM Period Register */ 29 30 #define MX3_PWMCR_FWM GENMASK(27, 26) 31 #define MX3_PWMCR_STOPEN BIT(25) 32 #define MX3_PWMCR_DOZEN BIT(24) 33 #define MX3_PWMCR_WAITEN BIT(23) 34 #define MX3_PWMCR_DBGEN BIT(22) 35 #define MX3_PWMCR_BCTR BIT(21) 36 #define MX3_PWMCR_HCTR BIT(20) 37 38 #define MX3_PWMCR_POUTC GENMASK(19, 18) 39 #define MX3_PWMCR_POUTC_NORMAL 0 40 #define MX3_PWMCR_POUTC_INVERTED 1 41 #define MX3_PWMCR_POUTC_OFF 2 42 43 #define MX3_PWMCR_CLKSRC GENMASK(17, 16) 44 #define MX3_PWMCR_CLKSRC_OFF 0 45 #define MX3_PWMCR_CLKSRC_IPG 1 46 #define MX3_PWMCR_CLKSRC_IPG_HIGH 2 47 #define MX3_PWMCR_CLKSRC_IPG_32K 3 48 49 #define MX3_PWMCR_PRESCALER GENMASK(15, 4) 50 51 #define MX3_PWMCR_SWR BIT(3) 52 53 #define MX3_PWMCR_REPEAT GENMASK(2, 1) 54 #define MX3_PWMCR_REPEAT_1X 0 55 #define MX3_PWMCR_REPEAT_2X 1 56 #define MX3_PWMCR_REPEAT_4X 2 57 #define MX3_PWMCR_REPEAT_8X 3 58 59 #define MX3_PWMCR_EN BIT(0) 60 61 #define MX3_PWMSR_FWE BIT(6) 62 #define MX3_PWMSR_CMP BIT(5) 63 #define MX3_PWMSR_ROV BIT(4) 64 #define MX3_PWMSR_FE BIT(3) 65 66 #define MX3_PWMSR_FIFOAV GENMASK(2, 0) 67 #define MX3_PWMSR_FIFOAV_EMPTY 0 68 #define MX3_PWMSR_FIFOAV_1WORD 1 69 #define MX3_PWMSR_FIFOAV_2WORDS 2 70 #define MX3_PWMSR_FIFOAV_3WORDS 3 71 #define MX3_PWMSR_FIFOAV_4WORDS 4 72 73 #define MX3_PWMCR_PRESCALER_SET(x) FIELD_PREP(MX3_PWMCR_PRESCALER, (x) - 1) 74 #define MX3_PWMCR_PRESCALER_GET(x) (FIELD_GET(MX3_PWMCR_PRESCALER, \ 75 (x)) + 1) 76 77 #define MX3_PWM_SWR_LOOP 5 78 79 /* PWMPR register value of 0xffff has the same effect as 0xfffe */ 80 #define MX3_PWMPR_MAX 0xfffe 81 82 struct pwm_imx27_chip { 83 struct clk *clk_ipg; 84 struct clk *clk_per; 85 void __iomem *mmio_base; 86 87 /* 88 * The driver cannot read the current duty cycle from the hardware if 89 * the hardware is disabled. Cache the last programmed duty cycle 90 * value to return in that case. 91 */ 92 unsigned int duty_cycle; 93 }; 94 95 static inline struct pwm_imx27_chip *to_pwm_imx27_chip(struct pwm_chip *chip) 96 { 97 return pwmchip_get_drvdata(chip); 98 } 99 100 static int pwm_imx27_clk_prepare_enable(struct pwm_imx27_chip *imx) 101 { 102 int ret; 103 104 ret = clk_prepare_enable(imx->clk_ipg); 105 if (ret) 106 return ret; 107 108 ret = clk_prepare_enable(imx->clk_per); 109 if (ret) { 110 clk_disable_unprepare(imx->clk_ipg); 111 return ret; 112 } 113 114 return 0; 115 } 116 117 static void pwm_imx27_clk_disable_unprepare(struct pwm_imx27_chip *imx) 118 { 119 clk_disable_unprepare(imx->clk_per); 120 clk_disable_unprepare(imx->clk_ipg); 121 } 122 123 static int pwm_imx27_get_state(struct pwm_chip *chip, 124 struct pwm_device *pwm, struct pwm_state *state) 125 { 126 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 127 u32 period, prescaler, pwm_clk, val; 128 u64 tmp; 129 int ret; 130 131 ret = pwm_imx27_clk_prepare_enable(imx); 132 if (ret < 0) 133 return ret; 134 135 val = readl(imx->mmio_base + MX3_PWMCR); 136 137 if (val & MX3_PWMCR_EN) 138 state->enabled = true; 139 else 140 state->enabled = false; 141 142 switch (FIELD_GET(MX3_PWMCR_POUTC, val)) { 143 case MX3_PWMCR_POUTC_NORMAL: 144 state->polarity = PWM_POLARITY_NORMAL; 145 break; 146 case MX3_PWMCR_POUTC_INVERTED: 147 state->polarity = PWM_POLARITY_INVERSED; 148 break; 149 default: 150 dev_warn(pwmchip_parent(chip), "can't set polarity, output disconnected"); 151 } 152 153 prescaler = MX3_PWMCR_PRESCALER_GET(val); 154 pwm_clk = clk_get_rate(imx->clk_per); 155 val = readl(imx->mmio_base + MX3_PWMPR); 156 period = val >= MX3_PWMPR_MAX ? MX3_PWMPR_MAX : val; 157 158 /* PWMOUT (Hz) = PWMCLK / (PWMPR + 2) */ 159 tmp = NSEC_PER_SEC * (u64)(period + 2) * prescaler; 160 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); 161 162 /* 163 * PWMSAR can be read only if PWM is enabled. If the PWM is disabled, 164 * use the cached value. 165 */ 166 if (state->enabled) 167 val = readl(imx->mmio_base + MX3_PWMSAR); 168 else 169 val = imx->duty_cycle; 170 171 tmp = NSEC_PER_SEC * (u64)(val) * prescaler; 172 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); 173 174 pwm_imx27_clk_disable_unprepare(imx); 175 176 return 0; 177 } 178 179 static void pwm_imx27_sw_reset(struct pwm_chip *chip) 180 { 181 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 182 struct device *dev = pwmchip_parent(chip); 183 int wait_count = 0; 184 u32 cr; 185 186 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); 187 do { 188 usleep_range(200, 1000); 189 cr = readl(imx->mmio_base + MX3_PWMCR); 190 } while ((cr & MX3_PWMCR_SWR) && 191 (wait_count++ < MX3_PWM_SWR_LOOP)); 192 193 if (cr & MX3_PWMCR_SWR) 194 dev_warn(dev, "software reset timeout\n"); 195 } 196 197 static void pwm_imx27_wait_fifo_slot(struct pwm_chip *chip, 198 struct pwm_device *pwm) 199 { 200 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 201 struct device *dev = pwmchip_parent(chip); 202 unsigned int period_ms; 203 int fifoav; 204 u32 sr; 205 206 sr = readl(imx->mmio_base + MX3_PWMSR); 207 fifoav = FIELD_GET(MX3_PWMSR_FIFOAV, sr); 208 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) { 209 period_ms = DIV_ROUND_UP_ULL(pwm->state.period, 210 NSEC_PER_MSEC); 211 msleep(period_ms); 212 213 sr = readl(imx->mmio_base + MX3_PWMSR); 214 if (fifoav == FIELD_GET(MX3_PWMSR_FIFOAV, sr)) 215 dev_warn(dev, "there is no free FIFO slot\n"); 216 } 217 } 218 219 static int pwm_imx27_apply(struct pwm_chip *chip, struct pwm_device *pwm, 220 const struct pwm_state *state) 221 { 222 unsigned long period_cycles, duty_cycles, prescale; 223 struct pwm_imx27_chip *imx = to_pwm_imx27_chip(chip); 224 unsigned long long c; 225 unsigned long long clkrate; 226 int ret; 227 u32 cr; 228 229 clkrate = clk_get_rate(imx->clk_per); 230 c = clkrate * state->period; 231 232 do_div(c, NSEC_PER_SEC); 233 period_cycles = c; 234 235 prescale = period_cycles / 0x10000 + 1; 236 237 period_cycles /= prescale; 238 c = clkrate * state->duty_cycle; 239 do_div(c, NSEC_PER_SEC); 240 duty_cycles = c; 241 duty_cycles /= prescale; 242 243 /* 244 * according to imx pwm RM, the real period value should be PERIOD 245 * value in PWMPR plus 2. 246 */ 247 if (period_cycles > 2) 248 period_cycles -= 2; 249 else 250 period_cycles = 0; 251 252 /* 253 * Wait for a free FIFO slot if the PWM is already enabled, and flush 254 * the FIFO if the PWM was disabled and is about to be enabled. 255 */ 256 if (pwm->state.enabled) { 257 pwm_imx27_wait_fifo_slot(chip, pwm); 258 } else { 259 ret = pwm_imx27_clk_prepare_enable(imx); 260 if (ret) 261 return ret; 262 263 pwm_imx27_sw_reset(chip); 264 } 265 266 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR); 267 writel(period_cycles, imx->mmio_base + MX3_PWMPR); 268 269 /* 270 * Store the duty cycle for future reference in cases where the 271 * MX3_PWMSAR register can't be read (i.e. when the PWM is disabled). 272 */ 273 imx->duty_cycle = duty_cycles; 274 275 cr = MX3_PWMCR_PRESCALER_SET(prescale) | 276 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEN | MX3_PWMCR_WAITEN | 277 FIELD_PREP(MX3_PWMCR_CLKSRC, MX3_PWMCR_CLKSRC_IPG_HIGH) | 278 MX3_PWMCR_DBGEN; 279 280 if (state->polarity == PWM_POLARITY_INVERSED) 281 cr |= FIELD_PREP(MX3_PWMCR_POUTC, 282 MX3_PWMCR_POUTC_INVERTED); 283 284 if (state->enabled) 285 cr |= MX3_PWMCR_EN; 286 287 writel(cr, imx->mmio_base + MX3_PWMCR); 288 289 if (!state->enabled) 290 pwm_imx27_clk_disable_unprepare(imx); 291 292 return 0; 293 } 294 295 static const struct pwm_ops pwm_imx27_ops = { 296 .apply = pwm_imx27_apply, 297 .get_state = pwm_imx27_get_state, 298 }; 299 300 static const struct of_device_id pwm_imx27_dt_ids[] = { 301 { .compatible = "fsl,imx27-pwm", }, 302 { /* sentinel */ } 303 }; 304 MODULE_DEVICE_TABLE(of, pwm_imx27_dt_ids); 305 306 static int pwm_imx27_probe(struct platform_device *pdev) 307 { 308 struct pwm_chip *chip; 309 struct pwm_imx27_chip *imx; 310 int ret; 311 u32 pwmcr; 312 313 chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*imx)); 314 if (IS_ERR(chip)) 315 return PTR_ERR(chip); 316 imx = to_pwm_imx27_chip(chip); 317 318 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 319 if (IS_ERR(imx->clk_ipg)) 320 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_ipg), 321 "getting ipg clock failed\n"); 322 323 imx->clk_per = devm_clk_get(&pdev->dev, "per"); 324 if (IS_ERR(imx->clk_per)) 325 return dev_err_probe(&pdev->dev, PTR_ERR(imx->clk_per), 326 "failed to get peripheral clock\n"); 327 328 chip->ops = &pwm_imx27_ops; 329 330 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); 331 if (IS_ERR(imx->mmio_base)) 332 return PTR_ERR(imx->mmio_base); 333 334 ret = pwm_imx27_clk_prepare_enable(imx); 335 if (ret) 336 return ret; 337 338 /* keep clks on if pwm is running */ 339 pwmcr = readl(imx->mmio_base + MX3_PWMCR); 340 if (!(pwmcr & MX3_PWMCR_EN)) 341 pwm_imx27_clk_disable_unprepare(imx); 342 343 return devm_pwmchip_add(&pdev->dev, chip); 344 } 345 346 static struct platform_driver imx_pwm_driver = { 347 .driver = { 348 .name = "pwm-imx27", 349 .of_match_table = pwm_imx27_dt_ids, 350 }, 351 .probe = pwm_imx27_probe, 352 }; 353 module_platform_driver(imx_pwm_driver); 354 355 MODULE_DESCRIPTION("i.MX27 and later i.MX SoCs Pulse Width Modulator driver"); 356 MODULE_LICENSE("GPL v2"); 357 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 358