1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale FlexTimer Module (FTM) PWM Driver 4 * 5 * Copyright 2012-2013 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm.h> 16 #include <linux/pwm.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/fsl/ftm.h> 20 21 #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) 22 23 enum fsl_pwm_clk { 24 FSL_PWM_CLK_SYS, 25 FSL_PWM_CLK_FIX, 26 FSL_PWM_CLK_EXT, 27 FSL_PWM_CLK_CNTEN, 28 FSL_PWM_CLK_MAX 29 }; 30 31 struct fsl_ftm_soc { 32 bool has_enable_bits; 33 }; 34 35 struct fsl_pwm_periodcfg { 36 enum fsl_pwm_clk clk_select; 37 unsigned int clk_ps; 38 unsigned int mod_period; 39 }; 40 41 struct fsl_pwm_chip { 42 struct regmap *regmap; 43 44 /* This value is valid iff a pwm is running */ 45 struct fsl_pwm_periodcfg period; 46 47 struct clk *ipg_clk; 48 struct clk *clk[FSL_PWM_CLK_MAX]; 49 50 const struct fsl_ftm_soc *soc; 51 }; 52 53 static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) 54 { 55 return pwmchip_get_drvdata(chip); 56 } 57 58 static void ftm_clear_write_protection(struct fsl_pwm_chip *fpc) 59 { 60 u32 val; 61 62 regmap_read(fpc->regmap, FTM_FMS, &val); 63 if (val & FTM_FMS_WPEN) 64 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); 65 } 66 67 static void ftm_set_write_protection(struct fsl_pwm_chip *fpc) 68 { 69 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); 70 } 71 72 static bool fsl_pwm_periodcfg_are_equal(const struct fsl_pwm_periodcfg *a, 73 const struct fsl_pwm_periodcfg *b) 74 { 75 if (a->clk_select != b->clk_select) 76 return false; 77 if (a->clk_ps != b->clk_ps) 78 return false; 79 if (a->mod_period != b->mod_period) 80 return false; 81 return true; 82 } 83 84 static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 85 { 86 int ret; 87 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 88 89 ret = clk_prepare_enable(fpc->ipg_clk); 90 if (!ret && fpc->soc->has_enable_bits) 91 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); 92 93 return ret; 94 } 95 96 static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 97 { 98 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 99 100 if (fpc->soc->has_enable_bits) 101 regmap_clear_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); 102 103 clk_disable_unprepare(fpc->ipg_clk); 104 } 105 106 static unsigned int fsl_pwm_ticks_to_ns(struct fsl_pwm_chip *fpc, 107 unsigned int ticks) 108 { 109 unsigned long rate; 110 unsigned long long exval; 111 112 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); 113 if (rate >> fpc->period.clk_ps == 0) 114 return 0; 115 116 exval = ticks; 117 exval *= 1000000000UL; 118 do_div(exval, rate >> fpc->period.clk_ps); 119 return exval; 120 } 121 122 static bool fsl_pwm_calculate_period_clk(struct fsl_pwm_chip *fpc, 123 unsigned int period_ns, 124 enum fsl_pwm_clk index, 125 struct fsl_pwm_periodcfg *periodcfg 126 ) 127 { 128 unsigned long long c; 129 unsigned int ps; 130 131 c = clk_get_rate(fpc->clk[index]); 132 c = c * period_ns; 133 do_div(c, 1000000000UL); 134 135 if (c == 0) 136 return false; 137 138 for (ps = 0; ps < 8 ; ++ps, c >>= 1) { 139 if (c <= 0x10000) { 140 periodcfg->clk_select = index; 141 periodcfg->clk_ps = ps; 142 periodcfg->mod_period = c - 1; 143 return true; 144 } 145 } 146 return false; 147 } 148 149 static bool fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, 150 unsigned int period_ns, 151 struct fsl_pwm_periodcfg *periodcfg) 152 { 153 enum fsl_pwm_clk m0, m1; 154 unsigned long fix_rate, ext_rate; 155 bool ret; 156 157 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, FSL_PWM_CLK_SYS, 158 periodcfg); 159 if (ret) 160 return true; 161 162 fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); 163 ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); 164 165 if (fix_rate > ext_rate) { 166 m0 = FSL_PWM_CLK_FIX; 167 m1 = FSL_PWM_CLK_EXT; 168 } else { 169 m0 = FSL_PWM_CLK_EXT; 170 m1 = FSL_PWM_CLK_FIX; 171 } 172 173 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg); 174 if (ret) 175 return true; 176 177 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); 178 } 179 180 static unsigned int fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, 181 unsigned int duty_ns) 182 { 183 unsigned long long duty; 184 185 unsigned int period = fpc->period.mod_period + 1; 186 unsigned int period_ns = fsl_pwm_ticks_to_ns(fpc, period); 187 188 if (!period_ns) 189 return 0; 190 191 duty = (unsigned long long)duty_ns * period; 192 do_div(duty, period_ns); 193 194 return (unsigned int)duty; 195 } 196 197 static bool fsl_pwm_is_any_pwm_enabled(struct fsl_pwm_chip *fpc, 198 struct pwm_device *pwm) 199 { 200 u32 val; 201 202 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 203 if (~val & 0xFF) 204 return true; 205 else 206 return false; 207 } 208 209 static bool fsl_pwm_is_other_pwm_enabled(struct fsl_pwm_chip *fpc, 210 struct pwm_device *pwm) 211 { 212 u32 val; 213 214 regmap_read(fpc->regmap, FTM_OUTMASK, &val); 215 if (~(val | BIT(pwm->hwpwm)) & 0xFF) 216 return true; 217 else 218 return false; 219 } 220 221 static int fsl_pwm_apply_config(struct pwm_chip *chip, 222 struct pwm_device *pwm, 223 const struct pwm_state *newstate) 224 { 225 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 226 unsigned int duty; 227 u32 reg_polarity; 228 229 struct fsl_pwm_periodcfg periodcfg; 230 bool do_write_period = false; 231 232 if (!fsl_pwm_calculate_period(fpc, newstate->period, &periodcfg)) { 233 dev_err(pwmchip_parent(chip), "failed to calculate new period\n"); 234 return -EINVAL; 235 } 236 237 if (!fsl_pwm_is_any_pwm_enabled(fpc, pwm)) 238 do_write_period = true; 239 /* 240 * The Freescale FTM controller supports only a single period for 241 * all PWM channels, therefore verify if the newly computed period 242 * is different than the current period being used. In such case 243 * we allow to change the period only if no other pwm is running. 244 */ 245 else if (!fsl_pwm_periodcfg_are_equal(&fpc->period, &periodcfg)) { 246 if (fsl_pwm_is_other_pwm_enabled(fpc, pwm)) { 247 dev_err(pwmchip_parent(chip), 248 "Cannot change period for PWM %u, disable other PWMs first\n", 249 pwm->hwpwm); 250 return -EBUSY; 251 } 252 if (fpc->period.clk_select != periodcfg.clk_select) { 253 int ret; 254 enum fsl_pwm_clk oldclk = fpc->period.clk_select; 255 enum fsl_pwm_clk newclk = periodcfg.clk_select; 256 257 ret = clk_prepare_enable(fpc->clk[newclk]); 258 if (ret) 259 return ret; 260 clk_disable_unprepare(fpc->clk[oldclk]); 261 } 262 do_write_period = true; 263 } 264 265 ftm_clear_write_protection(fpc); 266 267 if (do_write_period) { 268 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_CLK_MASK, 269 FTM_SC_CLK(periodcfg.clk_select)); 270 regmap_update_bits(fpc->regmap, FTM_SC, FTM_SC_PS_MASK, 271 periodcfg.clk_ps); 272 regmap_write(fpc->regmap, FTM_MOD, periodcfg.mod_period); 273 274 fpc->period = periodcfg; 275 } 276 277 duty = fsl_pwm_calculate_duty(fpc, newstate->duty_cycle); 278 279 regmap_write(fpc->regmap, FTM_CSC(pwm->hwpwm), 280 FTM_CSC_MSB | FTM_CSC_ELSB); 281 regmap_write(fpc->regmap, FTM_CV(pwm->hwpwm), duty); 282 283 reg_polarity = 0; 284 if (newstate->polarity == PWM_POLARITY_INVERSED) 285 reg_polarity = BIT(pwm->hwpwm); 286 287 regmap_update_bits(fpc->regmap, FTM_POL, BIT(pwm->hwpwm), reg_polarity); 288 289 ftm_set_write_protection(fpc); 290 291 return 0; 292 } 293 294 static int fsl_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 295 const struct pwm_state *newstate) 296 { 297 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 298 struct pwm_state *oldstate = &pwm->state; 299 int ret; 300 301 /* 302 * oldstate to newstate : action 303 * 304 * disabled to disabled : ignore 305 * enabled to disabled : disable 306 * enabled to enabled : update settings 307 * disabled to enabled : update settings + enable 308 */ 309 310 if (!newstate->enabled) { 311 if (oldstate->enabled) { 312 regmap_set_bits(fpc->regmap, FTM_OUTMASK, 313 BIT(pwm->hwpwm)); 314 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 315 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); 316 } 317 318 return 0; 319 } 320 321 ret = fsl_pwm_apply_config(chip, pwm, newstate); 322 if (ret) 323 return ret; 324 325 /* check if need to enable */ 326 if (!oldstate->enabled) { 327 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); 328 if (ret) 329 return ret; 330 331 ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 332 if (ret) { 333 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); 334 return ret; 335 } 336 337 regmap_clear_bits(fpc->regmap, FTM_OUTMASK, BIT(pwm->hwpwm)); 338 } 339 340 return ret; 341 } 342 343 static const struct pwm_ops fsl_pwm_ops = { 344 .request = fsl_pwm_request, 345 .free = fsl_pwm_free, 346 .apply = fsl_pwm_apply, 347 }; 348 349 static int fsl_pwm_init(struct fsl_pwm_chip *fpc) 350 { 351 int ret; 352 353 ret = clk_prepare_enable(fpc->ipg_clk); 354 if (ret) 355 return ret; 356 357 regmap_write(fpc->regmap, FTM_CNTIN, 0x00); 358 regmap_write(fpc->regmap, FTM_OUTINIT, 0x00); 359 regmap_write(fpc->regmap, FTM_OUTMASK, 0xFF); 360 361 clk_disable_unprepare(fpc->ipg_clk); 362 363 return 0; 364 } 365 366 static bool fsl_pwm_volatile_reg(struct device *dev, unsigned int reg) 367 { 368 switch (reg) { 369 case FTM_FMS: 370 case FTM_MODE: 371 case FTM_CNT: 372 return true; 373 } 374 return false; 375 } 376 377 static const struct regmap_config fsl_pwm_regmap_config = { 378 .reg_bits = 32, 379 .reg_stride = 4, 380 .val_bits = 32, 381 382 .max_register = FTM_PWMLOAD, 383 .volatile_reg = fsl_pwm_volatile_reg, 384 .cache_type = REGCACHE_FLAT, 385 }; 386 387 static int fsl_pwm_probe(struct platform_device *pdev) 388 { 389 struct pwm_chip *chip; 390 struct fsl_pwm_chip *fpc; 391 void __iomem *base; 392 int ret; 393 394 chip = devm_pwmchip_alloc(&pdev->dev, 8, sizeof(*fpc)); 395 if (IS_ERR(chip)) 396 return PTR_ERR(chip); 397 fpc = to_fsl_chip(chip); 398 399 fpc->soc = of_device_get_match_data(&pdev->dev); 400 401 base = devm_platform_ioremap_resource(pdev, 0); 402 if (IS_ERR(base)) 403 return PTR_ERR(base); 404 405 fpc->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "ftm_sys", base, 406 &fsl_pwm_regmap_config); 407 if (IS_ERR(fpc->regmap)) { 408 dev_err(&pdev->dev, "regmap init failed\n"); 409 return PTR_ERR(fpc->regmap); 410 } 411 412 fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); 413 if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { 414 dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); 415 return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); 416 } 417 418 fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(&pdev->dev, "ftm_fix"); 419 if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) 420 return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); 421 422 fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(&pdev->dev, "ftm_ext"); 423 if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) 424 return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); 425 426 fpc->clk[FSL_PWM_CLK_CNTEN] = 427 devm_clk_get(&pdev->dev, "ftm_cnt_clk_en"); 428 if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) 429 return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); 430 431 /* 432 * ipg_clk is the interface clock for the IP. If not provided, use the 433 * ftm_sys clock as the default. 434 */ 435 fpc->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 436 if (IS_ERR(fpc->ipg_clk)) 437 fpc->ipg_clk = fpc->clk[FSL_PWM_CLK_SYS]; 438 439 chip->ops = &fsl_pwm_ops; 440 441 ret = devm_pwmchip_add(&pdev->dev, chip); 442 if (ret < 0) { 443 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); 444 return ret; 445 } 446 447 platform_set_drvdata(pdev, chip); 448 449 return fsl_pwm_init(fpc); 450 } 451 452 #ifdef CONFIG_PM_SLEEP 453 static int fsl_pwm_suspend(struct device *dev) 454 { 455 struct pwm_chip *chip = dev_get_drvdata(dev); 456 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 457 int i; 458 459 regcache_cache_only(fpc->regmap, true); 460 regcache_mark_dirty(fpc->regmap); 461 462 for (i = 0; i < chip->npwm; i++) { 463 struct pwm_device *pwm = &chip->pwms[i]; 464 465 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 466 continue; 467 468 clk_disable_unprepare(fpc->ipg_clk); 469 470 if (!pwm_is_enabled(pwm)) 471 continue; 472 473 clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); 474 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); 475 } 476 477 return 0; 478 } 479 480 static int fsl_pwm_resume(struct device *dev) 481 { 482 struct pwm_chip *chip = dev_get_drvdata(dev); 483 struct fsl_pwm_chip *fpc = to_fsl_chip(chip); 484 int i; 485 486 for (i = 0; i < chip->npwm; i++) { 487 struct pwm_device *pwm = &chip->pwms[i]; 488 489 if (!test_bit(PWMF_REQUESTED, &pwm->flags)) 490 continue; 491 492 clk_prepare_enable(fpc->ipg_clk); 493 494 if (!pwm_is_enabled(pwm)) 495 continue; 496 497 clk_prepare_enable(fpc->clk[fpc->period.clk_select]); 498 clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); 499 } 500 501 /* restore all registers from cache */ 502 regcache_cache_only(fpc->regmap, false); 503 regcache_sync(fpc->regmap); 504 505 return 0; 506 } 507 #endif 508 509 static const struct dev_pm_ops fsl_pwm_pm_ops = { 510 SET_SYSTEM_SLEEP_PM_OPS(fsl_pwm_suspend, fsl_pwm_resume) 511 }; 512 513 static const struct fsl_ftm_soc vf610_ftm_pwm = { 514 .has_enable_bits = false, 515 }; 516 517 static const struct fsl_ftm_soc imx8qm_ftm_pwm = { 518 .has_enable_bits = true, 519 }; 520 521 static const struct of_device_id fsl_pwm_dt_ids[] = { 522 { .compatible = "fsl,vf610-ftm-pwm", .data = &vf610_ftm_pwm }, 523 { .compatible = "fsl,imx8qm-ftm-pwm", .data = &imx8qm_ftm_pwm }, 524 { /* sentinel */ } 525 }; 526 MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); 527 528 static struct platform_driver fsl_pwm_driver = { 529 .driver = { 530 .name = "fsl-ftm-pwm", 531 .of_match_table = fsl_pwm_dt_ids, 532 .pm = &fsl_pwm_pm_ops, 533 }, 534 .probe = fsl_pwm_probe, 535 }; 536 module_platform_driver(fsl_pwm_driver); 537 538 MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); 539 MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); 540 MODULE_ALIAS("platform:fsl-ftm-pwm"); 541 MODULE_LICENSE("GPL"); 542