1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2016 Broadcom 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/err.h> 7 #include <linux/io.h> 8 #include <linux/math64.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/pwm.h> 13 14 #define IPROC_PWM_CTRL_OFFSET 0x00 15 #define IPROC_PWM_CTRL_TYPE_SHIFT(ch) (15 + (ch)) 16 #define IPROC_PWM_CTRL_POLARITY_SHIFT(ch) (8 + (ch)) 17 #define IPROC_PWM_CTRL_EN_SHIFT(ch) (ch) 18 19 #define IPROC_PWM_PERIOD_OFFSET(ch) (0x04 + ((ch) << 3)) 20 #define IPROC_PWM_PERIOD_MIN 0x02 21 #define IPROC_PWM_PERIOD_MAX 0xffff 22 23 #define IPROC_PWM_DUTY_CYCLE_OFFSET(ch) (0x08 + ((ch) << 3)) 24 #define IPROC_PWM_DUTY_CYCLE_MIN 0x00 25 #define IPROC_PWM_DUTY_CYCLE_MAX 0xffff 26 27 #define IPROC_PWM_PRESCALE_OFFSET 0x24 28 #define IPROC_PWM_PRESCALE_BITS 0x06 29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \ 30 IPROC_PWM_PRESCALE_BITS) 31 #define IPROC_PWM_PRESCALE_MASK(ch) (IPROC_PWM_PRESCALE_MAX << \ 32 IPROC_PWM_PRESCALE_SHIFT(ch)) 33 #define IPROC_PWM_PRESCALE_MIN 0x00 34 #define IPROC_PWM_PRESCALE_MAX 0x3f 35 36 struct iproc_pwmc { 37 void __iomem *base; 38 struct clk *clk; 39 }; 40 41 static inline struct iproc_pwmc *to_iproc_pwmc(struct pwm_chip *chip) 42 { 43 return pwmchip_get_drvdata(chip); 44 } 45 46 static void iproc_pwmc_enable(struct iproc_pwmc *ip, unsigned int channel) 47 { 48 u32 value; 49 50 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); 51 value |= 1 << IPROC_PWM_CTRL_EN_SHIFT(channel); 52 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); 53 54 /* must be a 400 ns delay between clearing and setting enable bit */ 55 ndelay(400); 56 } 57 58 static void iproc_pwmc_disable(struct iproc_pwmc *ip, unsigned int channel) 59 { 60 u32 value; 61 62 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); 63 value &= ~(1 << IPROC_PWM_CTRL_EN_SHIFT(channel)); 64 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); 65 66 /* must be a 400 ns delay between clearing and setting enable bit */ 67 ndelay(400); 68 } 69 70 static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 71 struct pwm_state *state) 72 { 73 struct iproc_pwmc *ip = to_iproc_pwmc(chip); 74 u64 tmp, multi, rate; 75 u32 value, prescale; 76 77 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); 78 79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) 80 state->enabled = true; 81 else 82 state->enabled = false; 83 84 if (value & BIT(IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm))) 85 state->polarity = PWM_POLARITY_NORMAL; 86 else 87 state->polarity = PWM_POLARITY_INVERSED; 88 89 rate = clk_get_rate(ip->clk); 90 if (rate == 0) { 91 state->period = 0; 92 state->duty_cycle = 0; 93 return 0; 94 } 95 96 value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); 97 prescale = value >> IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); 98 prescale &= IPROC_PWM_PRESCALE_MAX; 99 100 multi = NSEC_PER_SEC * (prescale + 1); 101 102 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); 103 tmp = (value & IPROC_PWM_PERIOD_MAX) * multi; 104 state->period = div64_u64(tmp, rate); 105 106 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); 107 tmp = (value & IPROC_PWM_PERIOD_MAX) * multi; 108 state->duty_cycle = div64_u64(tmp, rate); 109 110 return 0; 111 } 112 113 static int iproc_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm, 114 const struct pwm_state *state) 115 { 116 unsigned long prescale = IPROC_PWM_PRESCALE_MIN; 117 struct iproc_pwmc *ip = to_iproc_pwmc(chip); 118 u32 value, period, duty; 119 u64 rate; 120 121 rate = clk_get_rate(ip->clk); 122 123 /* 124 * Find period count, duty count and prescale to suit duty_cycle and 125 * period. This is done according to formulas described below: 126 * 127 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE 128 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE 129 * 130 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) 131 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) 132 */ 133 while (1) { 134 u64 value, div; 135 136 div = NSEC_PER_SEC * (prescale + 1); 137 value = rate * state->period; 138 period = div64_u64(value, div); 139 value = rate * state->duty_cycle; 140 duty = div64_u64(value, div); 141 142 if (period < IPROC_PWM_PERIOD_MIN) 143 return -EINVAL; 144 145 if (period <= IPROC_PWM_PERIOD_MAX && 146 duty <= IPROC_PWM_DUTY_CYCLE_MAX) 147 break; 148 149 /* Otherwise, increase prescale and recalculate counts */ 150 if (++prescale > IPROC_PWM_PRESCALE_MAX) 151 return -EINVAL; 152 } 153 154 iproc_pwmc_disable(ip, pwm->hwpwm); 155 156 /* Set prescale */ 157 value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); 158 value &= ~IPROC_PWM_PRESCALE_MASK(pwm->hwpwm); 159 value |= prescale << IPROC_PWM_PRESCALE_SHIFT(pwm->hwpwm); 160 writel(value, ip->base + IPROC_PWM_PRESCALE_OFFSET); 161 162 /* set period and duty cycle */ 163 writel(period, ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); 164 writel(duty, ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); 165 166 /* set polarity */ 167 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); 168 169 if (state->polarity == PWM_POLARITY_NORMAL) 170 value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm); 171 else 172 value &= ~(1 << IPROC_PWM_CTRL_POLARITY_SHIFT(pwm->hwpwm)); 173 174 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); 175 176 if (state->enabled) 177 iproc_pwmc_enable(ip, pwm->hwpwm); 178 179 return 0; 180 } 181 182 static const struct pwm_ops iproc_pwm_ops = { 183 .apply = iproc_pwmc_apply, 184 .get_state = iproc_pwmc_get_state, 185 }; 186 187 static int iproc_pwmc_probe(struct platform_device *pdev) 188 { 189 struct pwm_chip *chip; 190 struct iproc_pwmc *ip; 191 unsigned int i; 192 u32 value; 193 int ret; 194 195 chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*ip)); 196 if (IS_ERR(chip)) 197 return PTR_ERR(chip); 198 ip = to_iproc_pwmc(chip); 199 200 platform_set_drvdata(pdev, ip); 201 202 chip->ops = &iproc_pwm_ops; 203 204 ip->base = devm_platform_ioremap_resource(pdev, 0); 205 if (IS_ERR(ip->base)) 206 return PTR_ERR(ip->base); 207 208 ip->clk = devm_clk_get_enabled(&pdev->dev, NULL); 209 if (IS_ERR(ip->clk)) 210 return dev_err_probe(&pdev->dev, PTR_ERR(ip->clk), 211 "failed to get clock\n"); 212 213 /* Set full drive and normal polarity for all channels */ 214 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); 215 216 for (i = 0; i < chip->npwm; i++) { 217 value &= ~(1 << IPROC_PWM_CTRL_TYPE_SHIFT(i)); 218 value |= 1 << IPROC_PWM_CTRL_POLARITY_SHIFT(i); 219 } 220 221 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); 222 223 ret = devm_pwmchip_add(&pdev->dev, chip); 224 if (ret < 0) 225 return dev_err_probe(&pdev->dev, ret, 226 "failed to add PWM chip\n"); 227 228 return 0; 229 } 230 231 static const struct of_device_id bcm_iproc_pwmc_dt[] = { 232 { .compatible = "brcm,iproc-pwm" }, 233 { }, 234 }; 235 MODULE_DEVICE_TABLE(of, bcm_iproc_pwmc_dt); 236 237 static struct platform_driver iproc_pwmc_driver = { 238 .driver = { 239 .name = "bcm-iproc-pwm", 240 .of_match_table = bcm_iproc_pwmc_dt, 241 }, 242 .probe = iproc_pwmc_probe, 243 }; 244 module_platform_driver(iproc_pwmc_driver); 245 246 MODULE_AUTHOR("Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>"); 247 MODULE_DESCRIPTION("Broadcom iProc PWM driver"); 248 MODULE_LICENSE("GPL v2"); 249