1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PTP 1588 clock using the EG20T PCH 4 * 5 * Copyright (C) 2010 OMICRON electronics GmbH 6 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD. 7 * 8 * This code was derived from the IXP46X driver. 9 */ 10 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/ptp_clock_kernel.h> 21 #include <linux/ptp_pch.h> 22 #include <linux/slab.h> 23 24 #define STATION_ADDR_LEN 20 25 #define PCI_DEVICE_ID_PCH_1588 0x8819 26 #define IO_MEM_BAR 1 27 28 #define DEFAULT_ADDEND 0xA0000000 29 #define TICKS_NS_SHIFT 5 30 #define N_EXT_TS 2 31 32 enum pch_status { 33 PCH_SUCCESS, 34 PCH_INVALIDPARAM, 35 PCH_NOTIMESTAMP, 36 PCH_INTERRUPTMODEINUSE, 37 PCH_FAILED, 38 PCH_UNSUPPORTED, 39 }; 40 41 /* 42 * struct pch_ts_regs - IEEE 1588 registers 43 */ 44 struct pch_ts_regs { 45 u32 control; 46 u32 event; 47 u32 addend; 48 u32 accum; 49 u32 test; 50 u32 ts_compare; 51 u32 rsystime_lo; 52 u32 rsystime_hi; 53 u32 systime_lo; 54 u32 systime_hi; 55 u32 trgt_lo; 56 u32 trgt_hi; 57 u32 asms_lo; 58 u32 asms_hi; 59 u32 amms_lo; 60 u32 amms_hi; 61 u32 ch_control; 62 u32 ch_event; 63 u32 tx_snap_lo; 64 u32 tx_snap_hi; 65 u32 rx_snap_lo; 66 u32 rx_snap_hi; 67 u32 src_uuid_lo; 68 u32 src_uuid_hi; 69 u32 can_status; 70 u32 can_snap_lo; 71 u32 can_snap_hi; 72 u32 ts_sel; 73 u32 ts_st[6]; 74 u32 reserve1[14]; 75 u32 stl_max_set_en; 76 u32 stl_max_set; 77 u32 reserve2[13]; 78 u32 srst; 79 }; 80 81 #define PCH_TSC_RESET (1 << 0) 82 #define PCH_TSC_TTM_MASK (1 << 1) 83 #define PCH_TSC_ASMS_MASK (1 << 2) 84 #define PCH_TSC_AMMS_MASK (1 << 3) 85 #define PCH_TSC_PPSM_MASK (1 << 4) 86 #define PCH_TSE_TTIPEND (1 << 1) 87 #define PCH_TSE_SNS (1 << 2) 88 #define PCH_TSE_SNM (1 << 3) 89 #define PCH_TSE_PPS (1 << 4) 90 #define PCH_CC_MM (1 << 0) 91 #define PCH_CC_TA (1 << 1) 92 93 #define PCH_CC_MODE_SHIFT 16 94 #define PCH_CC_MODE_MASK 0x001F0000 95 #define PCH_CC_VERSION (1 << 31) 96 #define PCH_CE_TXS (1 << 0) 97 #define PCH_CE_RXS (1 << 1) 98 #define PCH_CE_OVR (1 << 0) 99 #define PCH_CE_VAL (1 << 1) 100 #define PCH_ECS_ETH (1 << 0) 101 102 #define PCH_ECS_CAN (1 << 1) 103 #define PCH_STATION_BYTES 6 104 105 #define PCH_IEEE1588_ETH (1 << 0) 106 #define PCH_IEEE1588_CAN (1 << 1) 107 108 /* 109 * struct pch_dev - Driver private data 110 */ 111 struct pch_dev { 112 struct pch_ts_regs __iomem *regs; 113 struct ptp_clock *ptp_clock; 114 struct ptp_clock_info caps; 115 int exts0_enabled; 116 int exts1_enabled; 117 118 u32 mem_base; 119 u32 mem_size; 120 u32 irq; 121 struct pci_dev *pdev; 122 spinlock_t register_lock; 123 }; 124 125 /* 126 * struct pch_params - 1588 module parameter 127 */ 128 struct pch_params { 129 u8 station[STATION_ADDR_LEN]; 130 }; 131 132 /* structure to hold the module parameters */ 133 static struct pch_params pch_param = { 134 "00:00:00:00:00:00" 135 }; 136 137 /* 138 * Register access functions 139 */ 140 static inline void pch_eth_enable_set(struct pch_dev *chip) 141 { 142 u32 val; 143 /* SET the eth_enable bit */ 144 val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH); 145 iowrite32(val, (&chip->regs->ts_sel)); 146 } 147 148 static u64 pch_systime_read(struct pch_ts_regs __iomem *regs) 149 { 150 u64 ns; 151 u32 lo, hi; 152 153 lo = ioread32(®s->systime_lo); 154 hi = ioread32(®s->systime_hi); 155 156 ns = ((u64) hi) << 32; 157 ns |= lo; 158 ns <<= TICKS_NS_SHIFT; 159 160 return ns; 161 } 162 163 static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns) 164 { 165 u32 hi, lo; 166 167 ns >>= TICKS_NS_SHIFT; 168 hi = ns >> 32; 169 lo = ns & 0xffffffff; 170 171 iowrite32(lo, ®s->systime_lo); 172 iowrite32(hi, ®s->systime_hi); 173 } 174 175 static inline void pch_block_reset(struct pch_dev *chip) 176 { 177 u32 val; 178 /* Reset Hardware Assist block */ 179 val = ioread32(&chip->regs->control) | PCH_TSC_RESET; 180 iowrite32(val, (&chip->regs->control)); 181 val = val & ~PCH_TSC_RESET; 182 iowrite32(val, (&chip->regs->control)); 183 } 184 185 void pch_ch_control_write(struct pci_dev *pdev, u32 val) 186 { 187 struct pch_dev *chip = pci_get_drvdata(pdev); 188 189 iowrite32(val, (&chip->regs->ch_control)); 190 } 191 EXPORT_SYMBOL(pch_ch_control_write); 192 193 u32 pch_ch_event_read(struct pci_dev *pdev) 194 { 195 struct pch_dev *chip = pci_get_drvdata(pdev); 196 u32 val; 197 198 val = ioread32(&chip->regs->ch_event); 199 200 return val; 201 } 202 EXPORT_SYMBOL(pch_ch_event_read); 203 204 void pch_ch_event_write(struct pci_dev *pdev, u32 val) 205 { 206 struct pch_dev *chip = pci_get_drvdata(pdev); 207 208 iowrite32(val, (&chip->regs->ch_event)); 209 } 210 EXPORT_SYMBOL(pch_ch_event_write); 211 212 u32 pch_src_uuid_lo_read(struct pci_dev *pdev) 213 { 214 struct pch_dev *chip = pci_get_drvdata(pdev); 215 u32 val; 216 217 val = ioread32(&chip->regs->src_uuid_lo); 218 219 return val; 220 } 221 EXPORT_SYMBOL(pch_src_uuid_lo_read); 222 223 u32 pch_src_uuid_hi_read(struct pci_dev *pdev) 224 { 225 struct pch_dev *chip = pci_get_drvdata(pdev); 226 u32 val; 227 228 val = ioread32(&chip->regs->src_uuid_hi); 229 230 return val; 231 } 232 EXPORT_SYMBOL(pch_src_uuid_hi_read); 233 234 u64 pch_rx_snap_read(struct pci_dev *pdev) 235 { 236 struct pch_dev *chip = pci_get_drvdata(pdev); 237 u64 ns; 238 u32 lo, hi; 239 240 lo = ioread32(&chip->regs->rx_snap_lo); 241 hi = ioread32(&chip->regs->rx_snap_hi); 242 243 ns = ((u64) hi) << 32; 244 ns |= lo; 245 ns <<= TICKS_NS_SHIFT; 246 247 return ns; 248 } 249 EXPORT_SYMBOL(pch_rx_snap_read); 250 251 u64 pch_tx_snap_read(struct pci_dev *pdev) 252 { 253 struct pch_dev *chip = pci_get_drvdata(pdev); 254 u64 ns; 255 u32 lo, hi; 256 257 lo = ioread32(&chip->regs->tx_snap_lo); 258 hi = ioread32(&chip->regs->tx_snap_hi); 259 260 ns = ((u64) hi) << 32; 261 ns |= lo; 262 ns <<= TICKS_NS_SHIFT; 263 264 return ns; 265 } 266 EXPORT_SYMBOL(pch_tx_snap_read); 267 268 /* This function enables all 64 bits in system time registers [high & low]. 269 This is a work-around for non continuous value in the SystemTime Register*/ 270 static void pch_set_system_time_count(struct pch_dev *chip) 271 { 272 iowrite32(0x01, &chip->regs->stl_max_set_en); 273 iowrite32(0xFFFFFFFF, &chip->regs->stl_max_set); 274 iowrite32(0x00, &chip->regs->stl_max_set_en); 275 } 276 277 static void pch_reset(struct pch_dev *chip) 278 { 279 /* Reset Hardware Assist */ 280 pch_block_reset(chip); 281 282 /* enable all 32 bits in system time registers */ 283 pch_set_system_time_count(chip); 284 } 285 286 /** 287 * pch_set_station_address() - This API sets the station address used by 288 * IEEE 1588 hardware when looking at PTP 289 * traffic on the ethernet interface 290 * @addr: dress which contain the column separated address to be used. 291 * @pdev: PCI device. 292 */ 293 int pch_set_station_address(u8 *addr, struct pci_dev *pdev) 294 { 295 s32 i; 296 struct pch_dev *chip = pci_get_drvdata(pdev); 297 298 /* Verify the parameter */ 299 if ((chip->regs == NULL) || addr == (u8 *)NULL) { 300 dev_err(&pdev->dev, 301 "invalid params returning PCH_INVALIDPARAM\n"); 302 return PCH_INVALIDPARAM; 303 } 304 /* For all station address bytes */ 305 for (i = 0; i < PCH_STATION_BYTES; i++) { 306 u32 val; 307 s32 tmp; 308 309 tmp = hex_to_bin(addr[i * 3]); 310 if (tmp < 0) { 311 dev_err(&pdev->dev, 312 "invalid params returning PCH_INVALIDPARAM\n"); 313 return PCH_INVALIDPARAM; 314 } 315 val = tmp * 16; 316 tmp = hex_to_bin(addr[(i * 3) + 1]); 317 if (tmp < 0) { 318 dev_err(&pdev->dev, 319 "invalid params returning PCH_INVALIDPARAM\n"); 320 return PCH_INVALIDPARAM; 321 } 322 val += tmp; 323 /* Expects ':' separated addresses */ 324 if ((i < 5) && (addr[(i * 3) + 2] != ':')) { 325 dev_err(&pdev->dev, 326 "invalid params returning PCH_INVALIDPARAM\n"); 327 return PCH_INVALIDPARAM; 328 } 329 330 /* Ideally we should set the address only after validating 331 entire string */ 332 dev_dbg(&pdev->dev, "invoking pch_station_set\n"); 333 iowrite32(val, &chip->regs->ts_st[i]); 334 } 335 return 0; 336 } 337 EXPORT_SYMBOL(pch_set_station_address); 338 339 /* 340 * Interrupt service routine 341 */ 342 static irqreturn_t isr(int irq, void *priv) 343 { 344 struct pch_dev *pch_dev = priv; 345 struct pch_ts_regs __iomem *regs = pch_dev->regs; 346 struct ptp_clock_event event; 347 u32 ack = 0, lo, hi, val; 348 349 val = ioread32(®s->event); 350 351 if (val & PCH_TSE_SNS) { 352 ack |= PCH_TSE_SNS; 353 if (pch_dev->exts0_enabled) { 354 hi = ioread32(®s->asms_hi); 355 lo = ioread32(®s->asms_lo); 356 event.type = PTP_CLOCK_EXTTS; 357 event.index = 0; 358 event.timestamp = ((u64) hi) << 32; 359 event.timestamp |= lo; 360 event.timestamp <<= TICKS_NS_SHIFT; 361 ptp_clock_event(pch_dev->ptp_clock, &event); 362 } 363 } 364 365 if (val & PCH_TSE_SNM) { 366 ack |= PCH_TSE_SNM; 367 if (pch_dev->exts1_enabled) { 368 hi = ioread32(®s->amms_hi); 369 lo = ioread32(®s->amms_lo); 370 event.type = PTP_CLOCK_EXTTS; 371 event.index = 1; 372 event.timestamp = ((u64) hi) << 32; 373 event.timestamp |= lo; 374 event.timestamp <<= TICKS_NS_SHIFT; 375 ptp_clock_event(pch_dev->ptp_clock, &event); 376 } 377 } 378 379 if (val & PCH_TSE_TTIPEND) 380 ack |= PCH_TSE_TTIPEND; /* this bit seems to be always set */ 381 382 if (ack) { 383 iowrite32(ack, ®s->event); 384 return IRQ_HANDLED; 385 } else 386 return IRQ_NONE; 387 } 388 389 /* 390 * PTP clock operations 391 */ 392 393 static int ptp_pch_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 394 { 395 u64 adj; 396 u32 diff, addend; 397 int neg_adj = 0; 398 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 399 struct pch_ts_regs __iomem *regs = pch_dev->regs; 400 401 if (ppb < 0) { 402 neg_adj = 1; 403 ppb = -ppb; 404 } 405 addend = DEFAULT_ADDEND; 406 adj = addend; 407 adj *= ppb; 408 diff = div_u64(adj, 1000000000ULL); 409 410 addend = neg_adj ? addend - diff : addend + diff; 411 412 iowrite32(addend, ®s->addend); 413 414 return 0; 415 } 416 417 static int ptp_pch_adjtime(struct ptp_clock_info *ptp, s64 delta) 418 { 419 s64 now; 420 unsigned long flags; 421 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 422 struct pch_ts_regs __iomem *regs = pch_dev->regs; 423 424 spin_lock_irqsave(&pch_dev->register_lock, flags); 425 now = pch_systime_read(regs); 426 now += delta; 427 pch_systime_write(regs, now); 428 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 429 430 return 0; 431 } 432 433 static int ptp_pch_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 434 { 435 u64 ns; 436 unsigned long flags; 437 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 438 struct pch_ts_regs __iomem *regs = pch_dev->regs; 439 440 spin_lock_irqsave(&pch_dev->register_lock, flags); 441 ns = pch_systime_read(regs); 442 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 443 444 *ts = ns_to_timespec64(ns); 445 return 0; 446 } 447 448 static int ptp_pch_settime(struct ptp_clock_info *ptp, 449 const struct timespec64 *ts) 450 { 451 u64 ns; 452 unsigned long flags; 453 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 454 struct pch_ts_regs __iomem *regs = pch_dev->regs; 455 456 ns = timespec64_to_ns(ts); 457 458 spin_lock_irqsave(&pch_dev->register_lock, flags); 459 pch_systime_write(regs, ns); 460 spin_unlock_irqrestore(&pch_dev->register_lock, flags); 461 462 return 0; 463 } 464 465 static int ptp_pch_enable(struct ptp_clock_info *ptp, 466 struct ptp_clock_request *rq, int on) 467 { 468 struct pch_dev *pch_dev = container_of(ptp, struct pch_dev, caps); 469 470 switch (rq->type) { 471 case PTP_CLK_REQ_EXTTS: 472 switch (rq->extts.index) { 473 case 0: 474 pch_dev->exts0_enabled = on ? 1 : 0; 475 break; 476 case 1: 477 pch_dev->exts1_enabled = on ? 1 : 0; 478 break; 479 default: 480 return -EINVAL; 481 } 482 return 0; 483 default: 484 break; 485 } 486 487 return -EOPNOTSUPP; 488 } 489 490 static const struct ptp_clock_info ptp_pch_caps = { 491 .owner = THIS_MODULE, 492 .name = "PCH timer", 493 .max_adj = 50000000, 494 .n_ext_ts = N_EXT_TS, 495 .n_pins = 0, 496 .pps = 0, 497 .adjfreq = ptp_pch_adjfreq, 498 .adjtime = ptp_pch_adjtime, 499 .gettime64 = ptp_pch_gettime, 500 .settime64 = ptp_pch_settime, 501 .enable = ptp_pch_enable, 502 }; 503 504 #define pch_suspend NULL 505 #define pch_resume NULL 506 507 static void pch_remove(struct pci_dev *pdev) 508 { 509 struct pch_dev *chip = pci_get_drvdata(pdev); 510 511 ptp_clock_unregister(chip->ptp_clock); 512 /* free the interrupt */ 513 if (pdev->irq != 0) 514 free_irq(pdev->irq, chip); 515 516 /* unmap the virtual IO memory space */ 517 if (chip->regs != NULL) { 518 iounmap(chip->regs); 519 chip->regs = NULL; 520 } 521 /* release the reserved IO memory space */ 522 if (chip->mem_base != 0) { 523 release_mem_region(chip->mem_base, chip->mem_size); 524 chip->mem_base = 0; 525 } 526 pci_disable_device(pdev); 527 kfree(chip); 528 dev_info(&pdev->dev, "complete\n"); 529 } 530 531 static s32 532 pch_probe(struct pci_dev *pdev, const struct pci_device_id *id) 533 { 534 s32 ret; 535 unsigned long flags; 536 struct pch_dev *chip; 537 538 chip = kzalloc(sizeof(struct pch_dev), GFP_KERNEL); 539 if (chip == NULL) 540 return -ENOMEM; 541 542 /* enable the 1588 pci device */ 543 ret = pci_enable_device(pdev); 544 if (ret != 0) { 545 dev_err(&pdev->dev, "could not enable the pci device\n"); 546 goto err_pci_en; 547 } 548 549 chip->mem_base = pci_resource_start(pdev, IO_MEM_BAR); 550 if (!chip->mem_base) { 551 dev_err(&pdev->dev, "could not locate IO memory address\n"); 552 ret = -ENODEV; 553 goto err_pci_start; 554 } 555 556 /* retrieve the available length of the IO memory space */ 557 chip->mem_size = pci_resource_len(pdev, IO_MEM_BAR); 558 559 /* allocate the memory for the device registers */ 560 if (!request_mem_region(chip->mem_base, chip->mem_size, "1588_regs")) { 561 dev_err(&pdev->dev, 562 "could not allocate register memory space\n"); 563 ret = -EBUSY; 564 goto err_req_mem_region; 565 } 566 567 /* get the virtual address to the 1588 registers */ 568 chip->regs = ioremap(chip->mem_base, chip->mem_size); 569 570 if (!chip->regs) { 571 dev_err(&pdev->dev, "Could not get virtual address\n"); 572 ret = -ENOMEM; 573 goto err_ioremap; 574 } 575 576 chip->caps = ptp_pch_caps; 577 chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev); 578 if (IS_ERR(chip->ptp_clock)) { 579 ret = PTR_ERR(chip->ptp_clock); 580 goto err_ptp_clock_reg; 581 } 582 583 spin_lock_init(&chip->register_lock); 584 585 ret = request_irq(pdev->irq, &isr, IRQF_SHARED, KBUILD_MODNAME, chip); 586 if (ret != 0) { 587 dev_err(&pdev->dev, "failed to get irq %d\n", pdev->irq); 588 goto err_req_irq; 589 } 590 591 /* indicate success */ 592 chip->irq = pdev->irq; 593 chip->pdev = pdev; 594 pci_set_drvdata(pdev, chip); 595 596 spin_lock_irqsave(&chip->register_lock, flags); 597 /* reset the ieee1588 h/w */ 598 pch_reset(chip); 599 600 iowrite32(DEFAULT_ADDEND, &chip->regs->addend); 601 iowrite32(1, &chip->regs->trgt_lo); 602 iowrite32(0, &chip->regs->trgt_hi); 603 iowrite32(PCH_TSE_TTIPEND, &chip->regs->event); 604 605 pch_eth_enable_set(chip); 606 607 if (strcmp(pch_param.station, "00:00:00:00:00:00") != 0) { 608 if (pch_set_station_address(pch_param.station, pdev) != 0) { 609 dev_err(&pdev->dev, 610 "Invalid station address parameter\n" 611 "Module loaded but station address not set correctly\n" 612 ); 613 } 614 } 615 spin_unlock_irqrestore(&chip->register_lock, flags); 616 return 0; 617 618 err_req_irq: 619 ptp_clock_unregister(chip->ptp_clock); 620 err_ptp_clock_reg: 621 iounmap(chip->regs); 622 chip->regs = NULL; 623 624 err_ioremap: 625 release_mem_region(chip->mem_base, chip->mem_size); 626 627 err_req_mem_region: 628 chip->mem_base = 0; 629 630 err_pci_start: 631 pci_disable_device(pdev); 632 633 err_pci_en: 634 kfree(chip); 635 dev_err(&pdev->dev, "probe failed(ret=0x%x)\n", ret); 636 637 return ret; 638 } 639 640 static const struct pci_device_id pch_ieee1588_pcidev_id[] = { 641 { 642 .vendor = PCI_VENDOR_ID_INTEL, 643 .device = PCI_DEVICE_ID_PCH_1588 644 }, 645 {0} 646 }; 647 MODULE_DEVICE_TABLE(pci, pch_ieee1588_pcidev_id); 648 649 static SIMPLE_DEV_PM_OPS(pch_pm_ops, pch_suspend, pch_resume); 650 651 static struct pci_driver pch_driver = { 652 .name = KBUILD_MODNAME, 653 .id_table = pch_ieee1588_pcidev_id, 654 .probe = pch_probe, 655 .remove = pch_remove, 656 .driver.pm = &pch_pm_ops, 657 }; 658 659 static void __exit ptp_pch_exit(void) 660 { 661 pci_unregister_driver(&pch_driver); 662 } 663 664 static s32 __init ptp_pch_init(void) 665 { 666 s32 ret; 667 668 /* register the driver with the pci core */ 669 ret = pci_register_driver(&pch_driver); 670 671 return ret; 672 } 673 674 module_init(ptp_pch_init); 675 module_exit(ptp_pch_exit); 676 677 module_param_string(station, 678 pch_param.station, sizeof(pch_param.station), 0444); 679 MODULE_PARM_DESC(station, 680 "IEEE 1588 station address to use - colon separated hex values"); 681 682 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); 683 MODULE_DESCRIPTION("PTP clock using the EG20T timer"); 684 MODULE_LICENSE("GPL"); 685