1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2020 Facebook */ 3 4 #include <linux/err.h> 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/debugfs.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/serial_8250.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/platform_device.h> 14 #include <linux/ptp_clock_kernel.h> 15 #include <linux/spi/spi.h> 16 #include <linux/spi/xilinx_spi.h> 17 #include <net/devlink.h> 18 #include <linux/i2c.h> 19 #include <linux/mtd/mtd.h> 20 21 #ifndef PCI_VENDOR_ID_FACEBOOK 22 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b 23 #endif 24 25 #ifndef PCI_DEVICE_ID_FACEBOOK_TIMECARD 26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400 27 #endif 28 29 static struct class timecard_class = { 30 .owner = THIS_MODULE, 31 .name = "timecard", 32 }; 33 34 struct ocp_reg { 35 u32 ctrl; 36 u32 status; 37 u32 select; 38 u32 version; 39 u32 time_ns; 40 u32 time_sec; 41 u32 __pad0[2]; 42 u32 adjust_ns; 43 u32 adjust_sec; 44 u32 __pad1[2]; 45 u32 offset_ns; 46 u32 offset_window_ns; 47 u32 __pad2[2]; 48 u32 drift_ns; 49 u32 drift_window_ns; 50 u32 __pad3[6]; 51 u32 servo_offset_p; 52 u32 servo_offset_i; 53 u32 servo_drift_p; 54 u32 servo_drift_i; 55 }; 56 57 #define OCP_CTRL_ENABLE BIT(0) 58 #define OCP_CTRL_ADJUST_TIME BIT(1) 59 #define OCP_CTRL_ADJUST_OFFSET BIT(2) 60 #define OCP_CTRL_ADJUST_DRIFT BIT(3) 61 #define OCP_CTRL_ADJUST_SERVO BIT(8) 62 #define OCP_CTRL_READ_TIME_REQ BIT(30) 63 #define OCP_CTRL_READ_TIME_DONE BIT(31) 64 65 #define OCP_STATUS_IN_SYNC BIT(0) 66 #define OCP_STATUS_IN_HOLDOVER BIT(1) 67 68 #define OCP_SELECT_CLK_NONE 0 69 #define OCP_SELECT_CLK_REG 0xfe 70 71 struct tod_reg { 72 u32 ctrl; 73 u32 status; 74 u32 uart_polarity; 75 u32 version; 76 u32 adj_sec; 77 u32 __pad0[3]; 78 u32 uart_baud; 79 u32 __pad1[3]; 80 u32 utc_status; 81 u32 leap; 82 }; 83 84 #define TOD_CTRL_PROTOCOL BIT(28) 85 #define TOD_CTRL_DISABLE_FMT_A BIT(17) 86 #define TOD_CTRL_DISABLE_FMT_B BIT(16) 87 #define TOD_CTRL_ENABLE BIT(0) 88 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1) 89 #define TOD_CTRL_GNSS_SHIFT 24 90 91 #define TOD_STATUS_UTC_MASK 0xff 92 #define TOD_STATUS_UTC_VALID BIT(8) 93 #define TOD_STATUS_LEAP_VALID BIT(16) 94 95 struct ts_reg { 96 u32 enable; 97 u32 error; 98 u32 polarity; 99 u32 version; 100 u32 __pad0[4]; 101 u32 cable_delay; 102 u32 __pad1[3]; 103 u32 intr; 104 u32 intr_mask; 105 u32 event_count; 106 u32 __pad2[1]; 107 u32 ts_count; 108 u32 time_ns; 109 u32 time_sec; 110 u32 data_width; 111 u32 data; 112 }; 113 114 struct pps_reg { 115 u32 ctrl; 116 u32 status; 117 u32 __pad0[6]; 118 u32 cable_delay; 119 }; 120 121 #define PPS_STATUS_FILTER_ERR BIT(0) 122 #define PPS_STATUS_SUPERV_ERR BIT(1) 123 124 struct img_reg { 125 u32 version; 126 }; 127 128 struct gpio_reg { 129 u32 gpio1; 130 u32 __pad0; 131 u32 gpio2; 132 u32 __pad1; 133 }; 134 135 struct irig_master_reg { 136 u32 ctrl; 137 u32 status; 138 u32 __pad0; 139 u32 version; 140 u32 adj_sec; 141 u32 mode_ctrl; 142 }; 143 144 #define IRIG_M_CTRL_ENABLE BIT(0) 145 146 struct irig_slave_reg { 147 u32 ctrl; 148 u32 status; 149 u32 __pad0; 150 u32 version; 151 u32 adj_sec; 152 u32 mode_ctrl; 153 }; 154 155 #define IRIG_S_CTRL_ENABLE BIT(0) 156 157 struct dcf_master_reg { 158 u32 ctrl; 159 u32 status; 160 u32 __pad0; 161 u32 version; 162 u32 adj_sec; 163 }; 164 165 #define DCF_M_CTRL_ENABLE BIT(0) 166 167 struct dcf_slave_reg { 168 u32 ctrl; 169 u32 status; 170 u32 __pad0; 171 u32 version; 172 u32 adj_sec; 173 }; 174 175 #define DCF_S_CTRL_ENABLE BIT(0) 176 177 struct ptp_ocp_flash_info { 178 const char *name; 179 int pci_offset; 180 int data_size; 181 void *data; 182 }; 183 184 struct ptp_ocp_i2c_info { 185 const char *name; 186 unsigned long fixed_rate; 187 size_t data_size; 188 void *data; 189 }; 190 191 struct ptp_ocp_ext_info { 192 int index; 193 irqreturn_t (*irq_fcn)(int irq, void *priv); 194 int (*enable)(void *priv, u32 req, bool enable); 195 }; 196 197 struct ptp_ocp_ext_src { 198 void __iomem *mem; 199 struct ptp_ocp *bp; 200 struct ptp_ocp_ext_info *info; 201 int irq_vec; 202 }; 203 204 struct ptp_ocp { 205 struct pci_dev *pdev; 206 struct device dev; 207 spinlock_t lock; 208 struct ocp_reg __iomem *reg; 209 struct tod_reg __iomem *tod; 210 struct pps_reg __iomem *pps_to_ext; 211 struct pps_reg __iomem *pps_to_clk; 212 struct gpio_reg __iomem *pps_select; 213 struct gpio_reg __iomem *sma; 214 struct irig_master_reg __iomem *irig_out; 215 struct irig_slave_reg __iomem *irig_in; 216 struct dcf_master_reg __iomem *dcf_out; 217 struct dcf_slave_reg __iomem *dcf_in; 218 struct tod_reg __iomem *nmea_out; 219 struct ptp_ocp_ext_src *pps; 220 struct ptp_ocp_ext_src *ts0; 221 struct ptp_ocp_ext_src *ts1; 222 struct ptp_ocp_ext_src *ts2; 223 struct img_reg __iomem *image; 224 struct ptp_clock *ptp; 225 struct ptp_clock_info ptp_info; 226 struct platform_device *i2c_ctrl; 227 struct platform_device *spi_flash; 228 struct clk_hw *i2c_clk; 229 struct timer_list watchdog; 230 struct dentry *debug_root; 231 time64_t gnss_lost; 232 int id; 233 int n_irqs; 234 int gnss_port; 235 int gnss2_port; 236 int mac_port; /* miniature atomic clock */ 237 int nmea_port; 238 u8 serial[6]; 239 bool has_serial; 240 u32 pps_req_map; 241 int flash_start; 242 u32 utc_tai_offset; 243 u32 ts_window_adjust; 244 }; 245 246 #define OCP_REQ_TIMESTAMP BIT(0) 247 #define OCP_REQ_PPS BIT(1) 248 249 struct ocp_resource { 250 unsigned long offset; 251 int size; 252 int irq_vec; 253 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); 254 void *extra; 255 unsigned long bp_offset; 256 const char * const name; 257 }; 258 259 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); 260 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); 261 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); 262 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); 263 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); 264 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 265 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); 266 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable); 267 268 #define bp_assign_entry(bp, res, val) ({ \ 269 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ 270 *(typeof(val) *)addr = val; \ 271 }) 272 273 #define OCP_RES_LOCATION(member) \ 274 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member) 275 276 #define OCP_MEM_RESOURCE(member) \ 277 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem 278 279 #define OCP_SERIAL_RESOURCE(member) \ 280 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial 281 282 #define OCP_I2C_RESOURCE(member) \ 283 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c 284 285 #define OCP_SPI_RESOURCE(member) \ 286 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi 287 288 #define OCP_EXT_RESOURCE(member) \ 289 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext 290 291 /* This is the MSI vector mapping used. 292 * 0: TS3 (and PPS) 293 * 1: TS0 294 * 2: TS1 295 * 3: GNSS 296 * 4: GNSS2 297 * 5: MAC 298 * 6: TS2 299 * 7: I2C controller 300 * 8: HWICAP (notused) 301 * 9: SPI Flash 302 * 10: NMEA 303 */ 304 305 static struct ocp_resource ocp_fb_resource[] = { 306 { 307 OCP_MEM_RESOURCE(reg), 308 .offset = 0x01000000, .size = 0x10000, 309 }, 310 { 311 OCP_EXT_RESOURCE(ts0), 312 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 313 .extra = &(struct ptp_ocp_ext_info) { 314 .index = 0, 315 .irq_fcn = ptp_ocp_ts_irq, 316 .enable = ptp_ocp_ts_enable, 317 }, 318 }, 319 { 320 OCP_EXT_RESOURCE(ts1), 321 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 322 .extra = &(struct ptp_ocp_ext_info) { 323 .index = 1, 324 .irq_fcn = ptp_ocp_ts_irq, 325 .enable = ptp_ocp_ts_enable, 326 }, 327 }, 328 { 329 OCP_EXT_RESOURCE(ts2), 330 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, 331 .extra = &(struct ptp_ocp_ext_info) { 332 .index = 2, 333 .irq_fcn = ptp_ocp_ts_irq, 334 .enable = ptp_ocp_ts_enable, 335 }, 336 }, 337 { 338 OCP_EXT_RESOURCE(pps), 339 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, 340 .extra = &(struct ptp_ocp_ext_info) { 341 .index = 3, 342 .irq_fcn = ptp_ocp_ts_irq, 343 .enable = ptp_ocp_ts_enable, 344 }, 345 }, 346 { 347 OCP_MEM_RESOURCE(pps_to_ext), 348 .offset = 0x01030000, .size = 0x10000, 349 }, 350 { 351 OCP_MEM_RESOURCE(pps_to_clk), 352 .offset = 0x01040000, .size = 0x10000, 353 }, 354 { 355 OCP_MEM_RESOURCE(tod), 356 .offset = 0x01050000, .size = 0x10000, 357 }, 358 { 359 OCP_MEM_RESOURCE(irig_in), 360 .offset = 0x01070000, .size = 0x10000, 361 }, 362 { 363 OCP_MEM_RESOURCE(irig_out), 364 .offset = 0x01080000, .size = 0x10000, 365 }, 366 { 367 OCP_MEM_RESOURCE(dcf_in), 368 .offset = 0x01090000, .size = 0x10000, 369 }, 370 { 371 OCP_MEM_RESOURCE(dcf_out), 372 .offset = 0x010A0000, .size = 0x10000, 373 }, 374 { 375 OCP_MEM_RESOURCE(nmea_out), 376 .offset = 0x010B0000, .size = 0x10000, 377 }, 378 { 379 OCP_MEM_RESOURCE(image), 380 .offset = 0x00020000, .size = 0x1000, 381 }, 382 { 383 OCP_MEM_RESOURCE(pps_select), 384 .offset = 0x00130000, .size = 0x1000, 385 }, 386 { 387 OCP_MEM_RESOURCE(sma), 388 .offset = 0x00140000, .size = 0x1000, 389 }, 390 { 391 OCP_I2C_RESOURCE(i2c_ctrl), 392 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, 393 .extra = &(struct ptp_ocp_i2c_info) { 394 .name = "xiic-i2c", 395 .fixed_rate = 50000000, 396 }, 397 }, 398 { 399 OCP_SERIAL_RESOURCE(gnss_port), 400 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 401 }, 402 { 403 OCP_SERIAL_RESOURCE(gnss2_port), 404 .offset = 0x00170000 + 0x1000, .irq_vec = 4, 405 }, 406 { 407 OCP_SERIAL_RESOURCE(mac_port), 408 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 409 }, 410 { 411 OCP_SERIAL_RESOURCE(nmea_port), 412 .offset = 0x00190000 + 0x1000, .irq_vec = 10, 413 }, 414 { 415 OCP_SPI_RESOURCE(spi_flash), 416 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 417 .extra = &(struct ptp_ocp_flash_info) { 418 .name = "xilinx_spi", .pci_offset = 0, 419 .data_size = sizeof(struct xspi_platform_data), 420 .data = &(struct xspi_platform_data) { 421 .num_chipselect = 1, 422 .bits_per_word = 8, 423 .num_devices = 1, 424 .devices = &(struct spi_board_info) { 425 .modalias = "spi-nor", 426 }, 427 }, 428 }, 429 }, 430 { 431 .setup = ptp_ocp_fb_board_init, 432 }, 433 { } 434 }; 435 436 static const struct pci_device_id ptp_ocp_pcidev_id[] = { 437 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) }, 438 { 0 } 439 }; 440 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); 441 442 static DEFINE_MUTEX(ptp_ocp_lock); 443 static DEFINE_IDR(ptp_ocp_idr); 444 445 struct ocp_selector { 446 const char *name; 447 int value; 448 }; 449 450 static struct ocp_selector ptp_ocp_clock[] = { 451 { .name = "NONE", .value = 0 }, 452 { .name = "TOD", .value = 1 }, 453 { .name = "IRIG", .value = 2 }, 454 { .name = "PPS", .value = 3 }, 455 { .name = "PTP", .value = 4 }, 456 { .name = "RTC", .value = 5 }, 457 { .name = "DCF", .value = 6 }, 458 { .name = "REGS", .value = 0xfe }, 459 { .name = "EXT", .value = 0xff }, 460 { } 461 }; 462 463 static struct ocp_selector ptp_ocp_sma_in[] = { 464 { .name = "10Mhz", .value = 0x00 }, 465 { .name = "PPS1", .value = 0x01 }, 466 { .name = "PPS2", .value = 0x02 }, 467 { .name = "TS1", .value = 0x04 }, 468 { .name = "TS2", .value = 0x08 }, 469 { .name = "IRIG", .value = 0x10 }, 470 { .name = "DCF", .value = 0x20 }, 471 { } 472 }; 473 474 static struct ocp_selector ptp_ocp_sma_out[] = { 475 { .name = "10Mhz", .value = 0x00 }, 476 { .name = "PHC", .value = 0x01 }, 477 { .name = "MAC", .value = 0x02 }, 478 { .name = "GNSS", .value = 0x04 }, 479 { .name = "GNSS2", .value = 0x08 }, 480 { .name = "IRIG", .value = 0x10 }, 481 { .name = "DCF", .value = 0x20 }, 482 { } 483 }; 484 485 static const char * 486 ptp_ocp_select_name_from_val(struct ocp_selector *tbl, int val) 487 { 488 int i; 489 490 for (i = 0; tbl[i].name; i++) 491 if (tbl[i].value == val) 492 return tbl[i].name; 493 return NULL; 494 } 495 496 static int 497 ptp_ocp_select_val_from_name(struct ocp_selector *tbl, const char *name) 498 { 499 const char *select; 500 int i; 501 502 for (i = 0; tbl[i].name; i++) { 503 select = tbl[i].name; 504 if (!strncasecmp(name, select, strlen(select))) 505 return tbl[i].value; 506 } 507 return -EINVAL; 508 } 509 510 static ssize_t 511 ptp_ocp_select_table_show(struct ocp_selector *tbl, char *buf) 512 { 513 ssize_t count; 514 int i; 515 516 count = 0; 517 for (i = 0; tbl[i].name; i++) 518 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name); 519 if (count) 520 count--; 521 count += sysfs_emit_at(buf, count, "\n"); 522 return count; 523 } 524 525 static int 526 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, 527 struct ptp_system_timestamp *sts) 528 { 529 u32 ctrl, time_sec, time_ns; 530 int i; 531 532 ptp_read_system_prets(sts); 533 534 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 535 iowrite32(ctrl, &bp->reg->ctrl); 536 537 for (i = 0; i < 100; i++) { 538 ctrl = ioread32(&bp->reg->ctrl); 539 if (ctrl & OCP_CTRL_READ_TIME_DONE) 540 break; 541 } 542 ptp_read_system_postts(sts); 543 544 if (sts && bp->ts_window_adjust) { 545 s64 ns = timespec64_to_ns(&sts->post_ts); 546 547 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust); 548 } 549 550 time_ns = ioread32(&bp->reg->time_ns); 551 time_sec = ioread32(&bp->reg->time_sec); 552 553 ts->tv_sec = time_sec; 554 ts->tv_nsec = time_ns; 555 556 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; 557 } 558 559 static int 560 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, 561 struct ptp_system_timestamp *sts) 562 { 563 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 564 unsigned long flags; 565 int err; 566 567 spin_lock_irqsave(&bp->lock, flags); 568 err = __ptp_ocp_gettime_locked(bp, ts, sts); 569 spin_unlock_irqrestore(&bp->lock, flags); 570 571 return err; 572 } 573 574 static void 575 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) 576 { 577 u32 ctrl, time_sec, time_ns; 578 u32 select; 579 580 time_ns = ts->tv_nsec; 581 time_sec = ts->tv_sec; 582 583 select = ioread32(&bp->reg->select); 584 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 585 586 iowrite32(time_ns, &bp->reg->adjust_ns); 587 iowrite32(time_sec, &bp->reg->adjust_sec); 588 589 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE; 590 iowrite32(ctrl, &bp->reg->ctrl); 591 592 /* restore clock selection */ 593 iowrite32(select >> 16, &bp->reg->select); 594 } 595 596 static int 597 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) 598 { 599 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 600 unsigned long flags; 601 602 spin_lock_irqsave(&bp->lock, flags); 603 __ptp_ocp_settime_locked(bp, ts); 604 spin_unlock_irqrestore(&bp->lock, flags); 605 606 return 0; 607 } 608 609 static void 610 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u64 adj_val) 611 { 612 u32 select, ctrl; 613 614 select = ioread32(&bp->reg->select); 615 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 616 617 iowrite32(adj_val, &bp->reg->offset_ns); 618 iowrite32(adj_val & 0x7f, &bp->reg->offset_window_ns); 619 620 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE; 621 iowrite32(ctrl, &bp->reg->ctrl); 622 623 /* restore clock selection */ 624 iowrite32(select >> 16, &bp->reg->select); 625 } 626 627 static int 628 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) 629 { 630 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 631 unsigned long flags; 632 u32 adj_ns, sign; 633 634 sign = delta_ns < 0 ? BIT(31) : 0; 635 adj_ns = sign ? -delta_ns : delta_ns; 636 637 spin_lock_irqsave(&bp->lock, flags); 638 __ptp_ocp_adjtime_locked(bp, sign | adj_ns); 639 spin_unlock_irqrestore(&bp->lock, flags); 640 641 return 0; 642 } 643 644 static int 645 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 646 { 647 if (scaled_ppm == 0) 648 return 0; 649 650 return -EOPNOTSUPP; 651 } 652 653 static int 654 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) 655 { 656 return -EOPNOTSUPP; 657 } 658 659 static int 660 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, 661 int on) 662 { 663 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 664 struct ptp_ocp_ext_src *ext = NULL; 665 u32 req; 666 int err; 667 668 switch (rq->type) { 669 case PTP_CLK_REQ_EXTTS: 670 req = OCP_REQ_TIMESTAMP; 671 switch (rq->extts.index) { 672 case 0: 673 ext = bp->ts0; 674 break; 675 case 1: 676 ext = bp->ts1; 677 break; 678 case 2: 679 ext = bp->ts2; 680 break; 681 case 3: 682 ext = bp->pps; 683 break; 684 } 685 break; 686 case PTP_CLK_REQ_PPS: 687 req = OCP_REQ_PPS; 688 ext = bp->pps; 689 break; 690 case PTP_CLK_REQ_PEROUT: 691 if (on && 692 (rq->perout.period.sec != 1 || rq->perout.period.nsec != 0)) 693 return -EINVAL; 694 /* This is a request for 1PPS on an output SMA. 695 * Allow, but assume manual configuration. 696 */ 697 return 0; 698 default: 699 return -EOPNOTSUPP; 700 } 701 702 err = -ENXIO; 703 if (ext) 704 err = ext->info->enable(ext, req, on); 705 706 return err; 707 } 708 709 static const struct ptp_clock_info ptp_ocp_clock_info = { 710 .owner = THIS_MODULE, 711 .name = KBUILD_MODNAME, 712 .max_adj = 100000000, 713 .gettimex64 = ptp_ocp_gettimex, 714 .settime64 = ptp_ocp_settime, 715 .adjtime = ptp_ocp_adjtime, 716 .adjfine = ptp_ocp_null_adjfine, 717 .adjphase = ptp_ocp_null_adjphase, 718 .enable = ptp_ocp_enable, 719 .pps = true, 720 .n_ext_ts = 4, 721 .n_per_out = 1, 722 }; 723 724 static void 725 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) 726 { 727 u32 ctrl, select; 728 729 select = ioread32(&bp->reg->select); 730 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 731 732 iowrite32(0, &bp->reg->drift_ns); 733 734 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE; 735 iowrite32(ctrl, &bp->reg->ctrl); 736 737 /* restore clock selection */ 738 iowrite32(select >> 16, &bp->reg->select); 739 } 740 741 static void 742 ptp_ocp_watchdog(struct timer_list *t) 743 { 744 struct ptp_ocp *bp = from_timer(bp, t, watchdog); 745 unsigned long flags; 746 u32 status; 747 748 status = ioread32(&bp->pps_to_clk->status); 749 750 if (status & PPS_STATUS_SUPERV_ERR) { 751 iowrite32(status, &bp->pps_to_clk->status); 752 if (!bp->gnss_lost) { 753 spin_lock_irqsave(&bp->lock, flags); 754 __ptp_ocp_clear_drift_locked(bp); 755 spin_unlock_irqrestore(&bp->lock, flags); 756 bp->gnss_lost = ktime_get_real_seconds(); 757 } 758 759 } else if (bp->gnss_lost) { 760 bp->gnss_lost = 0; 761 } 762 763 mod_timer(&bp->watchdog, jiffies + HZ); 764 } 765 766 static void 767 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp) 768 { 769 ktime_t start, end; 770 ktime_t delay; 771 u32 ctrl; 772 773 ctrl = ioread32(&bp->reg->ctrl); 774 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE; 775 776 iowrite32(ctrl, &bp->reg->ctrl); 777 778 start = ktime_get_ns(); 779 780 ctrl = ioread32(&bp->reg->ctrl); 781 782 end = ktime_get_ns(); 783 784 delay = end - start; 785 bp->ts_window_adjust = (delay >> 5) * 3; 786 } 787 788 static int 789 ptp_ocp_init_clock(struct ptp_ocp *bp) 790 { 791 struct timespec64 ts; 792 bool sync; 793 u32 ctrl; 794 795 ctrl = OCP_CTRL_ENABLE; 796 iowrite32(ctrl, &bp->reg->ctrl); 797 798 /* NO DRIFT Correction */ 799 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ 800 iowrite32(0x2000, &bp->reg->servo_offset_p); 801 iowrite32(0x1000, &bp->reg->servo_offset_i); 802 iowrite32(0, &bp->reg->servo_drift_p); 803 iowrite32(0, &bp->reg->servo_drift_i); 804 805 /* latch servo values */ 806 ctrl |= OCP_CTRL_ADJUST_SERVO; 807 iowrite32(ctrl, &bp->reg->ctrl); 808 809 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { 810 dev_err(&bp->pdev->dev, "clock not enabled\n"); 811 return -ENODEV; 812 } 813 814 ptp_ocp_estimate_pci_timing(bp); 815 816 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 817 if (!sync) { 818 ktime_get_clocktai_ts64(&ts); 819 ptp_ocp_settime(&bp->ptp_info, &ts); 820 } 821 822 /* If there is a clock supervisor, then enable the watchdog */ 823 if (bp->pps_to_clk) { 824 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); 825 mod_timer(&bp->watchdog, jiffies + HZ); 826 } 827 828 return 0; 829 } 830 831 static void 832 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val) 833 { 834 unsigned long flags; 835 836 spin_lock_irqsave(&bp->lock, flags); 837 838 bp->utc_tai_offset = val; 839 840 if (bp->irig_out) 841 iowrite32(val, &bp->irig_out->adj_sec); 842 if (bp->dcf_out) 843 iowrite32(val, &bp->dcf_out->adj_sec); 844 if (bp->nmea_out) 845 iowrite32(val, &bp->nmea_out->adj_sec); 846 847 spin_unlock_irqrestore(&bp->lock, flags); 848 } 849 850 static void 851 ptp_ocp_tod_init(struct ptp_ocp *bp) 852 { 853 u32 ctrl, reg; 854 855 ctrl = ioread32(&bp->tod->ctrl); 856 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; 857 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); 858 iowrite32(ctrl, &bp->tod->ctrl); 859 860 reg = ioread32(&bp->tod->utc_status); 861 if (reg & TOD_STATUS_UTC_VALID) 862 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK); 863 } 864 865 static void 866 ptp_ocp_tod_info(struct ptp_ocp *bp) 867 { 868 static const char * const proto_name[] = { 869 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", 870 "UBX", "UBX_UTC", "UBX_LS", "UBX_none" 871 }; 872 static const char * const gnss_name[] = { 873 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", 874 }; 875 u32 version, ctrl, reg; 876 int idx; 877 878 version = ioread32(&bp->tod->version); 879 dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n", 880 version >> 24, (version >> 16) & 0xff, version & 0xffff); 881 882 ctrl = ioread32(&bp->tod->ctrl); 883 idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0; 884 idx += (ctrl >> 16) & 3; 885 dev_info(&bp->pdev->dev, "control: %x\n", ctrl); 886 dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx], 887 ctrl & TOD_CTRL_ENABLE ? "enabled" : ""); 888 889 idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; 890 if (idx < ARRAY_SIZE(gnss_name)) 891 dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]); 892 893 reg = ioread32(&bp->tod->status); 894 dev_info(&bp->pdev->dev, "status: %x\n", reg); 895 896 reg = ioread32(&bp->tod->adj_sec); 897 dev_info(&bp->pdev->dev, "correction: %d\n", reg); 898 899 reg = ioread32(&bp->tod->utc_status); 900 dev_info(&bp->pdev->dev, "utc_status: %x\n", reg); 901 dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n", 902 reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0, 903 reg & TOD_STATUS_LEAP_VALID ? 1 : 0); 904 } 905 906 static int 907 ptp_ocp_firstchild(struct device *dev, void *data) 908 { 909 return 1; 910 } 911 912 static int 913 ptp_ocp_read_i2c(struct i2c_adapter *adap, u8 addr, u8 reg, u8 sz, u8 *data) 914 { 915 struct i2c_msg msgs[2] = { 916 { 917 .addr = addr, 918 .len = 1, 919 .buf = ®, 920 }, 921 { 922 .addr = addr, 923 .flags = I2C_M_RD, 924 .len = 2, 925 .buf = data, 926 }, 927 }; 928 int err; 929 u8 len; 930 931 /* xiic-i2c for some stupid reason only does 2 byte reads. */ 932 while (sz) { 933 len = min_t(u8, sz, 2); 934 msgs[1].len = len; 935 err = i2c_transfer(adap, msgs, 2); 936 if (err != msgs[1].len) 937 return err; 938 msgs[1].buf += len; 939 reg += len; 940 sz -= len; 941 } 942 return 0; 943 } 944 945 static void 946 ptp_ocp_get_serial_number(struct ptp_ocp *bp) 947 { 948 struct i2c_adapter *adap; 949 struct device *dev; 950 int err; 951 952 if (!bp->i2c_ctrl) 953 return; 954 955 dev = device_find_child(&bp->i2c_ctrl->dev, NULL, ptp_ocp_firstchild); 956 if (!dev) { 957 dev_err(&bp->pdev->dev, "Can't find I2C adapter\n"); 958 return; 959 } 960 961 adap = i2c_verify_adapter(dev); 962 if (!adap) { 963 dev_err(&bp->pdev->dev, "device '%s' isn't an I2C adapter\n", 964 dev_name(dev)); 965 goto out; 966 } 967 968 err = ptp_ocp_read_i2c(adap, 0x58, 0x9A, 6, bp->serial); 969 if (err) { 970 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", err); 971 goto out; 972 } 973 974 bp->has_serial = true; 975 976 out: 977 put_device(dev); 978 } 979 980 static struct device * 981 ptp_ocp_find_flash(struct ptp_ocp *bp) 982 { 983 struct device *dev, *last; 984 985 last = NULL; 986 dev = &bp->spi_flash->dev; 987 988 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) { 989 if (!strcmp("mtd", dev_bus_name(dev))) 990 break; 991 put_device(last); 992 last = dev; 993 } 994 put_device(last); 995 996 return dev; 997 } 998 999 static int 1000 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, 1001 const struct firmware *fw) 1002 { 1003 struct mtd_info *mtd = dev_get_drvdata(dev); 1004 struct ptp_ocp *bp = devlink_priv(devlink); 1005 size_t off, len, resid, wrote; 1006 struct erase_info erase; 1007 size_t base, blksz; 1008 int err = 0; 1009 1010 off = 0; 1011 base = bp->flash_start; 1012 blksz = 4096; 1013 resid = fw->size; 1014 1015 while (resid) { 1016 devlink_flash_update_status_notify(devlink, "Flashing", 1017 NULL, off, fw->size); 1018 1019 len = min_t(size_t, resid, blksz); 1020 erase.addr = base + off; 1021 erase.len = blksz; 1022 1023 err = mtd_erase(mtd, &erase); 1024 if (err) 1025 goto out; 1026 1027 err = mtd_write(mtd, base + off, len, &wrote, &fw->data[off]); 1028 if (err) 1029 goto out; 1030 1031 off += blksz; 1032 resid -= len; 1033 } 1034 out: 1035 return err; 1036 } 1037 1038 static int 1039 ptp_ocp_devlink_flash_update(struct devlink *devlink, 1040 struct devlink_flash_update_params *params, 1041 struct netlink_ext_ack *extack) 1042 { 1043 struct ptp_ocp *bp = devlink_priv(devlink); 1044 struct device *dev; 1045 const char *msg; 1046 int err; 1047 1048 dev = ptp_ocp_find_flash(bp); 1049 if (!dev) { 1050 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); 1051 return -ENODEV; 1052 } 1053 1054 devlink_flash_update_status_notify(devlink, "Preparing to flash", 1055 NULL, 0, 0); 1056 1057 err = ptp_ocp_devlink_flash(devlink, dev, params->fw); 1058 1059 msg = err ? "Flash error" : "Flash complete"; 1060 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); 1061 1062 put_device(dev); 1063 return err; 1064 } 1065 1066 static int 1067 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1068 struct netlink_ext_ack *extack) 1069 { 1070 struct ptp_ocp *bp = devlink_priv(devlink); 1071 char buf[32]; 1072 int err; 1073 1074 err = devlink_info_driver_name_put(req, KBUILD_MODNAME); 1075 if (err) 1076 return err; 1077 1078 if (bp->image) { 1079 u32 ver = ioread32(&bp->image->version); 1080 1081 if (ver & 0xffff) { 1082 sprintf(buf, "%d", ver); 1083 err = devlink_info_version_running_put(req, 1084 "fw", 1085 buf); 1086 } else { 1087 sprintf(buf, "%d", ver >> 16); 1088 err = devlink_info_version_running_put(req, 1089 "loader", 1090 buf); 1091 } 1092 if (err) 1093 return err; 1094 } 1095 1096 if (!bp->has_serial) 1097 ptp_ocp_get_serial_number(bp); 1098 1099 if (bp->has_serial) { 1100 sprintf(buf, "%pM", bp->serial); 1101 err = devlink_info_serial_number_put(req, buf); 1102 if (err) 1103 return err; 1104 } 1105 1106 return 0; 1107 } 1108 1109 static const struct devlink_ops ptp_ocp_devlink_ops = { 1110 .flash_update = ptp_ocp_devlink_flash_update, 1111 .info_get = ptp_ocp_devlink_info_get, 1112 }; 1113 1114 static void __iomem * 1115 __ptp_ocp_get_mem(struct ptp_ocp *bp, unsigned long start, int size) 1116 { 1117 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); 1118 1119 return devm_ioremap_resource(&bp->pdev->dev, &res); 1120 } 1121 1122 static void __iomem * 1123 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1124 { 1125 unsigned long start; 1126 1127 start = pci_resource_start(bp->pdev, 0) + r->offset; 1128 return __ptp_ocp_get_mem(bp, start, r->size); 1129 } 1130 1131 static void 1132 ptp_ocp_set_irq_resource(struct resource *res, int irq) 1133 { 1134 struct resource r = DEFINE_RES_IRQ(irq); 1135 *res = r; 1136 } 1137 1138 static void 1139 ptp_ocp_set_mem_resource(struct resource *res, unsigned long start, int size) 1140 { 1141 struct resource r = DEFINE_RES_MEM(start, size); 1142 *res = r; 1143 } 1144 1145 static int 1146 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) 1147 { 1148 struct ptp_ocp_flash_info *info; 1149 struct pci_dev *pdev = bp->pdev; 1150 struct platform_device *p; 1151 struct resource res[2]; 1152 unsigned long start; 1153 int id; 1154 1155 start = pci_resource_start(pdev, 0) + r->offset; 1156 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1157 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1158 1159 info = r->extra; 1160 id = pci_dev_id(pdev) << 1; 1161 id += info->pci_offset; 1162 1163 p = platform_device_register_resndata(&pdev->dev, info->name, id, 1164 res, 2, info->data, 1165 info->data_size); 1166 if (IS_ERR(p)) 1167 return PTR_ERR(p); 1168 1169 bp_assign_entry(bp, r, p); 1170 1171 return 0; 1172 } 1173 1174 static struct platform_device * 1175 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) 1176 { 1177 struct ptp_ocp_i2c_info *info; 1178 struct resource res[2]; 1179 unsigned long start; 1180 1181 info = r->extra; 1182 start = pci_resource_start(pdev, 0) + r->offset; 1183 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1184 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1185 1186 return platform_device_register_resndata(&pdev->dev, info->name, 1187 id, res, 2, 1188 info->data, info->data_size); 1189 } 1190 1191 static int 1192 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) 1193 { 1194 struct pci_dev *pdev = bp->pdev; 1195 struct ptp_ocp_i2c_info *info; 1196 struct platform_device *p; 1197 struct clk_hw *clk; 1198 char buf[32]; 1199 int id; 1200 1201 info = r->extra; 1202 id = pci_dev_id(bp->pdev); 1203 1204 sprintf(buf, "AXI.%d", id); 1205 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, 1206 info->fixed_rate); 1207 if (IS_ERR(clk)) 1208 return PTR_ERR(clk); 1209 bp->i2c_clk = clk; 1210 1211 sprintf(buf, "%s.%d", info->name, id); 1212 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); 1213 p = ptp_ocp_i2c_bus(bp->pdev, r, id); 1214 if (IS_ERR(p)) 1215 return PTR_ERR(p); 1216 1217 bp_assign_entry(bp, r, p); 1218 1219 return 0; 1220 } 1221 1222 static irqreturn_t 1223 ptp_ocp_ts_irq(int irq, void *priv) 1224 { 1225 struct ptp_ocp_ext_src *ext = priv; 1226 struct ts_reg __iomem *reg = ext->mem; 1227 struct ptp_clock_event ev; 1228 u32 sec, nsec; 1229 1230 if (ext == ext->bp->pps) { 1231 if (ext->bp->pps_req_map & OCP_REQ_PPS) { 1232 ev.type = PTP_CLOCK_PPS; 1233 ptp_clock_event(ext->bp->ptp, &ev); 1234 } 1235 1236 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) 1237 goto out; 1238 } 1239 1240 /* XXX should fix API - this converts s/ns -> ts -> s/ns */ 1241 sec = ioread32(®->time_sec); 1242 nsec = ioread32(®->time_ns); 1243 1244 ev.type = PTP_CLOCK_EXTTS; 1245 ev.index = ext->info->index; 1246 ev.timestamp = sec * NSEC_PER_SEC + nsec; 1247 1248 ptp_clock_event(ext->bp->ptp, &ev); 1249 1250 out: 1251 iowrite32(1, ®->intr); /* write 1 to ack */ 1252 1253 return IRQ_HANDLED; 1254 } 1255 1256 static int 1257 ptp_ocp_ts_enable(void *priv, u32 req, bool enable) 1258 { 1259 struct ptp_ocp_ext_src *ext = priv; 1260 struct ts_reg __iomem *reg = ext->mem; 1261 struct ptp_ocp *bp = ext->bp; 1262 1263 if (ext == bp->pps) { 1264 u32 old_map = bp->pps_req_map; 1265 1266 if (enable) 1267 bp->pps_req_map |= req; 1268 else 1269 bp->pps_req_map &= ~req; 1270 1271 /* if no state change, just return */ 1272 if ((!!old_map ^ !!bp->pps_req_map) == 0) 1273 return 0; 1274 } 1275 1276 if (enable) { 1277 iowrite32(1, ®->enable); 1278 iowrite32(1, ®->intr_mask); 1279 iowrite32(1, ®->intr); 1280 } else { 1281 iowrite32(0, ®->intr_mask); 1282 iowrite32(0, ®->enable); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void 1289 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) 1290 { 1291 ext->info->enable(ext, ~0, false); 1292 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); 1293 kfree(ext); 1294 } 1295 1296 static int 1297 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) 1298 { 1299 struct pci_dev *pdev = bp->pdev; 1300 struct ptp_ocp_ext_src *ext; 1301 int err; 1302 1303 ext = kzalloc(sizeof(*ext), GFP_KERNEL); 1304 if (!ext) 1305 return -ENOMEM; 1306 1307 ext->mem = ptp_ocp_get_mem(bp, r); 1308 if (IS_ERR(ext->mem)) { 1309 err = PTR_ERR(ext->mem); 1310 goto out; 1311 } 1312 1313 ext->bp = bp; 1314 ext->info = r->extra; 1315 ext->irq_vec = r->irq_vec; 1316 1317 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, 1318 ext, "ocp%d.%s", bp->id, r->name); 1319 if (err) { 1320 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); 1321 goto out; 1322 } 1323 1324 bp_assign_entry(bp, r, ext); 1325 1326 return 0; 1327 1328 out: 1329 kfree(ext); 1330 return err; 1331 } 1332 1333 static int 1334 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) 1335 { 1336 struct pci_dev *pdev = bp->pdev; 1337 struct uart_8250_port uart; 1338 1339 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets 1340 * the serial port device claim and release the pci resource. 1341 */ 1342 memset(&uart, 0, sizeof(uart)); 1343 uart.port.dev = &pdev->dev; 1344 uart.port.iotype = UPIO_MEM; 1345 uart.port.regshift = 2; 1346 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; 1347 uart.port.irq = pci_irq_vector(pdev, r->irq_vec); 1348 uart.port.uartclk = 50000000; 1349 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP; 1350 uart.port.type = PORT_16550A; 1351 1352 return serial8250_register_8250_port(&uart); 1353 } 1354 1355 static int 1356 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) 1357 { 1358 int port; 1359 1360 port = ptp_ocp_serial_line(bp, r); 1361 if (port < 0) 1362 return port; 1363 1364 bp_assign_entry(bp, r, port); 1365 1366 return 0; 1367 } 1368 1369 static int 1370 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1371 { 1372 void __iomem *mem; 1373 1374 mem = ptp_ocp_get_mem(bp, r); 1375 if (IS_ERR(mem)) 1376 return PTR_ERR(mem); 1377 1378 bp_assign_entry(bp, r, mem); 1379 1380 return 0; 1381 } 1382 1383 static void 1384 ptp_ocp_nmea_out_init(struct ptp_ocp *bp) 1385 { 1386 if (!bp->nmea_out) 1387 return; 1388 1389 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ 1390 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */ 1391 iowrite32(1, &bp->nmea_out->ctrl); /* enable */ 1392 } 1393 1394 /* FB specific board initializers; last "resource" registered. */ 1395 static int 1396 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 1397 { 1398 bp->flash_start = 1024 * 4096; 1399 1400 ptp_ocp_tod_init(bp); 1401 ptp_ocp_nmea_out_init(bp); 1402 1403 return ptp_ocp_init_clock(bp); 1404 } 1405 1406 static bool 1407 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r) 1408 { 1409 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs; 1410 1411 if (!allow) 1412 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n", 1413 r->irq_vec, r->name); 1414 return allow; 1415 } 1416 1417 static int 1418 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) 1419 { 1420 struct ocp_resource *r, *table; 1421 int err = 0; 1422 1423 table = (struct ocp_resource *)driver_data; 1424 for (r = table; r->setup; r++) { 1425 if (!ptp_ocp_allow_irq(bp, r)) 1426 continue; 1427 err = r->setup(bp, r); 1428 if (err) { 1429 dev_err(&bp->pdev->dev, 1430 "Could not register %s: err %d\n", 1431 r->name, err); 1432 break; 1433 } 1434 } 1435 return err; 1436 } 1437 1438 static void 1439 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable) 1440 { 1441 u32 ctrl; 1442 bool on; 1443 1444 ctrl = ioread32(reg); 1445 on = ctrl & bit; 1446 if (on ^ enable) { 1447 ctrl &= ~bit; 1448 ctrl |= enable ? bit : 0; 1449 iowrite32(ctrl, reg); 1450 } 1451 } 1452 1453 static void 1454 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable) 1455 { 1456 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl, 1457 IRIG_M_CTRL_ENABLE, enable); 1458 } 1459 1460 static void 1461 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable) 1462 { 1463 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl, 1464 IRIG_S_CTRL_ENABLE, enable); 1465 } 1466 1467 static void 1468 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable) 1469 { 1470 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl, 1471 DCF_M_CTRL_ENABLE, enable); 1472 } 1473 1474 static void 1475 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable) 1476 { 1477 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl, 1478 DCF_S_CTRL_ENABLE, enable); 1479 } 1480 1481 static void 1482 __handle_signal_outputs(struct ptp_ocp *bp, u32 val) 1483 { 1484 ptp_ocp_irig_out(bp, val & 0x00100010); 1485 ptp_ocp_dcf_out(bp, val & 0x00200020); 1486 } 1487 1488 static void 1489 __handle_signal_inputs(struct ptp_ocp *bp, u32 val) 1490 { 1491 ptp_ocp_irig_in(bp, val & 0x00100010); 1492 ptp_ocp_dcf_in(bp, val & 0x00200020); 1493 } 1494 1495 /* 1496 * ANT0 == gps (in) 1497 * ANT1 == sma1 (in) 1498 * ANT2 == sma2 (in) 1499 * ANT3 == sma3 (out) 1500 * ANT4 == sma4 (out) 1501 */ 1502 1503 enum ptp_ocp_sma_mode { 1504 SMA_MODE_IN, 1505 SMA_MODE_OUT, 1506 }; 1507 1508 static struct ptp_ocp_sma_connector { 1509 enum ptp_ocp_sma_mode mode; 1510 bool fixed_mode; 1511 u16 default_out_idx; 1512 } ptp_ocp_sma_map[4] = { 1513 { 1514 .mode = SMA_MODE_IN, 1515 .fixed_mode = true, 1516 }, 1517 { 1518 .mode = SMA_MODE_IN, 1519 .fixed_mode = true, 1520 }, 1521 { 1522 .mode = SMA_MODE_OUT, 1523 .fixed_mode = true, 1524 .default_out_idx = 0, /* 10Mhz */ 1525 }, 1526 { 1527 .mode = SMA_MODE_OUT, 1528 .fixed_mode = true, 1529 .default_out_idx = 1, /* PHC */ 1530 }, 1531 }; 1532 1533 static ssize_t 1534 ptp_ocp_show_output(u32 val, char *buf, int default_idx) 1535 { 1536 const char *name; 1537 ssize_t count; 1538 1539 count = sysfs_emit(buf, "OUT: "); 1540 name = ptp_ocp_select_name_from_val(ptp_ocp_sma_out, val); 1541 if (!name) 1542 name = ptp_ocp_sma_out[default_idx].name; 1543 count += sysfs_emit_at(buf, count, "%s\n", name); 1544 return count; 1545 } 1546 1547 static ssize_t 1548 ptp_ocp_show_inputs(u32 val, char *buf, const char *zero_in) 1549 { 1550 const char *name; 1551 ssize_t count; 1552 int i; 1553 1554 count = sysfs_emit(buf, "IN: "); 1555 for (i = 0; i < ARRAY_SIZE(ptp_ocp_sma_in); i++) { 1556 if (val & ptp_ocp_sma_in[i].value) { 1557 name = ptp_ocp_sma_in[i].name; 1558 count += sysfs_emit_at(buf, count, "%s ", name); 1559 } 1560 } 1561 if (!val && zero_in) 1562 count += sysfs_emit_at(buf, count, "%s ", zero_in); 1563 if (count) 1564 count--; 1565 count += sysfs_emit_at(buf, count, "\n"); 1566 return count; 1567 } 1568 1569 static int 1570 sma_parse_inputs(const char *buf, enum ptp_ocp_sma_mode *mode) 1571 { 1572 struct ocp_selector *tbl[] = { ptp_ocp_sma_in, ptp_ocp_sma_out }; 1573 int idx, count, dir; 1574 char **argv; 1575 int ret; 1576 1577 argv = argv_split(GFP_KERNEL, buf, &count); 1578 if (!argv) 1579 return -ENOMEM; 1580 1581 ret = -EINVAL; 1582 if (!count) 1583 goto out; 1584 1585 idx = 0; 1586 dir = *mode == SMA_MODE_IN ? 0 : 1; 1587 if (!strcasecmp("IN:", argv[idx])) { 1588 dir = 0; 1589 idx++; 1590 } 1591 if (!strcasecmp("OUT:", argv[0])) { 1592 dir = 1; 1593 idx++; 1594 } 1595 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; 1596 1597 ret = 0; 1598 for (; idx < count; idx++) 1599 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]); 1600 if (ret < 0) 1601 ret = -EINVAL; 1602 1603 out: 1604 argv_free(argv); 1605 return ret; 1606 } 1607 1608 static ssize_t 1609 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, u32 val, char *buf, 1610 const char *zero_in) 1611 { 1612 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1]; 1613 1614 if (sma->mode == SMA_MODE_IN) 1615 return ptp_ocp_show_inputs(val, buf, zero_in); 1616 1617 return ptp_ocp_show_output(val, buf, sma->default_out_idx); 1618 } 1619 1620 static ssize_t 1621 sma1_show(struct device *dev, struct device_attribute *attr, char *buf) 1622 { 1623 struct ptp_ocp *bp = dev_get_drvdata(dev); 1624 u32 val; 1625 1626 val = ioread32(&bp->sma->gpio1) & 0x3f; 1627 return ptp_ocp_sma_show(bp, 1, val, buf, ptp_ocp_sma_in[0].name); 1628 } 1629 1630 static ssize_t 1631 sma2_show(struct device *dev, struct device_attribute *attr, char *buf) 1632 { 1633 struct ptp_ocp *bp = dev_get_drvdata(dev); 1634 u32 val; 1635 1636 val = (ioread32(&bp->sma->gpio1) >> 16) & 0x3f; 1637 return ptp_ocp_sma_show(bp, 2, val, buf, NULL); 1638 } 1639 1640 static ssize_t 1641 sma3_show(struct device *dev, struct device_attribute *attr, char *buf) 1642 { 1643 struct ptp_ocp *bp = dev_get_drvdata(dev); 1644 u32 val; 1645 1646 val = ioread32(&bp->sma->gpio2) & 0x3f; 1647 return ptp_ocp_sma_show(bp, 3, val, buf, NULL); 1648 } 1649 1650 static ssize_t 1651 sma4_show(struct device *dev, struct device_attribute *attr, char *buf) 1652 { 1653 struct ptp_ocp *bp = dev_get_drvdata(dev); 1654 u32 val; 1655 1656 val = (ioread32(&bp->sma->gpio2) >> 16) & 0x3f; 1657 return ptp_ocp_sma_show(bp, 4, val, buf, NULL); 1658 } 1659 1660 static void 1661 ptp_ocp_sma_store_output(struct ptp_ocp *bp, u32 val, u32 shift) 1662 { 1663 unsigned long flags; 1664 u32 gpio, mask; 1665 1666 mask = 0xffff << (16 - shift); 1667 1668 spin_lock_irqsave(&bp->lock, flags); 1669 1670 gpio = ioread32(&bp->sma->gpio2); 1671 gpio = (gpio & mask) | (val << shift); 1672 1673 __handle_signal_outputs(bp, gpio); 1674 1675 iowrite32(gpio, &bp->sma->gpio2); 1676 1677 spin_unlock_irqrestore(&bp->lock, flags); 1678 } 1679 1680 static void 1681 ptp_ocp_sma_store_inputs(struct ptp_ocp *bp, u32 val, u32 shift) 1682 { 1683 unsigned long flags; 1684 u32 gpio, mask; 1685 1686 mask = 0xffff << (16 - shift); 1687 1688 spin_lock_irqsave(&bp->lock, flags); 1689 1690 gpio = ioread32(&bp->sma->gpio1); 1691 gpio = (gpio & mask) | (val << shift); 1692 1693 __handle_signal_inputs(bp, gpio); 1694 1695 iowrite32(gpio, &bp->sma->gpio1); 1696 1697 spin_unlock_irqrestore(&bp->lock, flags); 1698 } 1699 1700 static ssize_t 1701 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr, u32 shift) 1702 { 1703 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1]; 1704 enum ptp_ocp_sma_mode mode; 1705 int val; 1706 1707 mode = sma->mode; 1708 val = sma_parse_inputs(buf, &mode); 1709 if (val < 0) 1710 return val; 1711 1712 if (mode != sma->mode && sma->fixed_mode) 1713 return -EOPNOTSUPP; 1714 1715 if (mode != sma->mode) { 1716 pr_err("Mode changes not supported yet.\n"); 1717 return -EOPNOTSUPP; 1718 } 1719 1720 if (sma->mode == SMA_MODE_IN) 1721 ptp_ocp_sma_store_inputs(bp, val, shift); 1722 else 1723 ptp_ocp_sma_store_output(bp, val, shift); 1724 1725 return 0; 1726 } 1727 1728 static ssize_t 1729 sma1_store(struct device *dev, struct device_attribute *attr, 1730 const char *buf, size_t count) 1731 { 1732 struct ptp_ocp *bp = dev_get_drvdata(dev); 1733 int err; 1734 1735 err = ptp_ocp_sma_store(bp, buf, 1, 0); 1736 return err ? err : count; 1737 } 1738 1739 static ssize_t 1740 sma2_store(struct device *dev, struct device_attribute *attr, 1741 const char *buf, size_t count) 1742 { 1743 struct ptp_ocp *bp = dev_get_drvdata(dev); 1744 int err; 1745 1746 err = ptp_ocp_sma_store(bp, buf, 2, 16); 1747 return err ? err : count; 1748 } 1749 1750 static ssize_t 1751 sma3_store(struct device *dev, struct device_attribute *attr, 1752 const char *buf, size_t count) 1753 { 1754 struct ptp_ocp *bp = dev_get_drvdata(dev); 1755 int err; 1756 1757 err = ptp_ocp_sma_store(bp, buf, 3, 0); 1758 return err ? err : count; 1759 } 1760 1761 static ssize_t 1762 sma4_store(struct device *dev, struct device_attribute *attr, 1763 const char *buf, size_t count) 1764 { 1765 struct ptp_ocp *bp = dev_get_drvdata(dev); 1766 int err; 1767 1768 err = ptp_ocp_sma_store(bp, buf, 4, 16); 1769 return err ? err : count; 1770 } 1771 static DEVICE_ATTR_RW(sma1); 1772 static DEVICE_ATTR_RW(sma2); 1773 static DEVICE_ATTR_RW(sma3); 1774 static DEVICE_ATTR_RW(sma4); 1775 1776 static ssize_t 1777 available_sma_inputs_show(struct device *dev, 1778 struct device_attribute *attr, char *buf) 1779 { 1780 return ptp_ocp_select_table_show(ptp_ocp_sma_in, buf); 1781 } 1782 static DEVICE_ATTR_RO(available_sma_inputs); 1783 1784 static ssize_t 1785 available_sma_outputs_show(struct device *dev, 1786 struct device_attribute *attr, char *buf) 1787 { 1788 return ptp_ocp_select_table_show(ptp_ocp_sma_out, buf); 1789 } 1790 static DEVICE_ATTR_RO(available_sma_outputs); 1791 1792 static ssize_t 1793 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) 1794 { 1795 struct ptp_ocp *bp = dev_get_drvdata(dev); 1796 1797 if (!bp->has_serial) 1798 ptp_ocp_get_serial_number(bp); 1799 1800 return sysfs_emit(buf, "%pM\n", bp->serial); 1801 } 1802 static DEVICE_ATTR_RO(serialnum); 1803 1804 static ssize_t 1805 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) 1806 { 1807 struct ptp_ocp *bp = dev_get_drvdata(dev); 1808 ssize_t ret; 1809 1810 if (bp->gnss_lost) 1811 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); 1812 else 1813 ret = sysfs_emit(buf, "SYNC\n"); 1814 1815 return ret; 1816 } 1817 static DEVICE_ATTR_RO(gnss_sync); 1818 1819 static ssize_t 1820 utc_tai_offset_show(struct device *dev, 1821 struct device_attribute *attr, char *buf) 1822 { 1823 struct ptp_ocp *bp = dev_get_drvdata(dev); 1824 1825 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset); 1826 } 1827 1828 static ssize_t 1829 utc_tai_offset_store(struct device *dev, 1830 struct device_attribute *attr, 1831 const char *buf, size_t count) 1832 { 1833 struct ptp_ocp *bp = dev_get_drvdata(dev); 1834 int err; 1835 u32 val; 1836 1837 err = kstrtou32(buf, 0, &val); 1838 if (err) 1839 return err; 1840 1841 ptp_ocp_utc_distribute(bp, val); 1842 1843 return count; 1844 } 1845 static DEVICE_ATTR_RW(utc_tai_offset); 1846 1847 static ssize_t 1848 ts_window_adjust_show(struct device *dev, 1849 struct device_attribute *attr, char *buf) 1850 { 1851 struct ptp_ocp *bp = dev_get_drvdata(dev); 1852 1853 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust); 1854 } 1855 1856 static ssize_t 1857 ts_window_adjust_store(struct device *dev, 1858 struct device_attribute *attr, 1859 const char *buf, size_t count) 1860 { 1861 struct ptp_ocp *bp = dev_get_drvdata(dev); 1862 int err; 1863 u32 val; 1864 1865 err = kstrtou32(buf, 0, &val); 1866 if (err) 1867 return err; 1868 1869 bp->ts_window_adjust = val; 1870 1871 return count; 1872 } 1873 static DEVICE_ATTR_RW(ts_window_adjust); 1874 1875 static ssize_t 1876 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1877 { 1878 struct ptp_ocp *bp = dev_get_drvdata(dev); 1879 u32 val; 1880 1881 val = ioread32(&bp->irig_out->ctrl); 1882 val = (val >> 16) & 0x07; 1883 return sysfs_emit(buf, "%d\n", val); 1884 } 1885 1886 static ssize_t 1887 irig_b_mode_store(struct device *dev, 1888 struct device_attribute *attr, 1889 const char *buf, size_t count) 1890 { 1891 struct ptp_ocp *bp = dev_get_drvdata(dev); 1892 unsigned long flags; 1893 int err; 1894 u32 reg; 1895 u8 val; 1896 1897 err = kstrtou8(buf, 0, &val); 1898 if (err) 1899 return err; 1900 if (val > 7) 1901 return -EINVAL; 1902 1903 reg = ((val & 0x7) << 16); 1904 1905 spin_lock_irqsave(&bp->lock, flags); 1906 iowrite32(0, &bp->irig_out->ctrl); /* disable */ 1907 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */ 1908 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl); 1909 spin_unlock_irqrestore(&bp->lock, flags); 1910 1911 return count; 1912 } 1913 static DEVICE_ATTR_RW(irig_b_mode); 1914 1915 static ssize_t 1916 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) 1917 { 1918 struct ptp_ocp *bp = dev_get_drvdata(dev); 1919 const char *p; 1920 u32 select; 1921 1922 select = ioread32(&bp->reg->select); 1923 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16); 1924 1925 return sysfs_emit(buf, "%s\n", p); 1926 } 1927 1928 static ssize_t 1929 clock_source_store(struct device *dev, struct device_attribute *attr, 1930 const char *buf, size_t count) 1931 { 1932 struct ptp_ocp *bp = dev_get_drvdata(dev); 1933 unsigned long flags; 1934 int val; 1935 1936 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf); 1937 if (val < 0) 1938 return val; 1939 1940 spin_lock_irqsave(&bp->lock, flags); 1941 iowrite32(val, &bp->reg->select); 1942 spin_unlock_irqrestore(&bp->lock, flags); 1943 1944 return count; 1945 } 1946 static DEVICE_ATTR_RW(clock_source); 1947 1948 static ssize_t 1949 available_clock_sources_show(struct device *dev, 1950 struct device_attribute *attr, char *buf) 1951 { 1952 return ptp_ocp_select_table_show(ptp_ocp_clock, buf); 1953 } 1954 static DEVICE_ATTR_RO(available_clock_sources); 1955 1956 static struct attribute *timecard_attrs[] = { 1957 &dev_attr_serialnum.attr, 1958 &dev_attr_gnss_sync.attr, 1959 &dev_attr_clock_source.attr, 1960 &dev_attr_available_clock_sources.attr, 1961 &dev_attr_sma1.attr, 1962 &dev_attr_sma2.attr, 1963 &dev_attr_sma3.attr, 1964 &dev_attr_sma4.attr, 1965 &dev_attr_available_sma_inputs.attr, 1966 &dev_attr_available_sma_outputs.attr, 1967 &dev_attr_irig_b_mode.attr, 1968 &dev_attr_utc_tai_offset.attr, 1969 &dev_attr_ts_window_adjust.attr, 1970 NULL, 1971 }; 1972 ATTRIBUTE_GROUPS(timecard); 1973 1974 static const char * 1975 gpio_map(u32 gpio, u32 bit, const char *pri, const char *sec, const char *def) 1976 { 1977 const char *ans; 1978 1979 if (gpio & (1 << bit)) 1980 ans = pri; 1981 else if (gpio & (1 << (bit + 16))) 1982 ans = sec; 1983 else 1984 ans = def; 1985 return ans; 1986 } 1987 1988 static void 1989 gpio_multi_map(char *buf, u32 gpio, u32 bit, 1990 const char *pri, const char *sec, const char *def) 1991 { 1992 char *ans = buf; 1993 1994 strcpy(ans, def); 1995 if (gpio & (1 << bit)) 1996 ans += sprintf(ans, "%s ", pri); 1997 if (gpio & (1 << (bit + 16))) 1998 ans += sprintf(ans, "%s ", sec); 1999 } 2000 2001 static int 2002 ptp_ocp_summary_show(struct seq_file *s, void *data) 2003 { 2004 struct device *dev = s->private; 2005 struct ptp_system_timestamp sts; 2006 u32 sma_in, sma_out, ctrl, val; 2007 struct ts_reg __iomem *ts_reg; 2008 struct timespec64 ts; 2009 struct ptp_ocp *bp; 2010 const char *src; 2011 bool on, map; 2012 char *buf; 2013 2014 buf = (char *)__get_free_page(GFP_KERNEL); 2015 if (!buf) 2016 return -ENOMEM; 2017 2018 bp = dev_get_drvdata(dev); 2019 sma_in = ioread32(&bp->sma->gpio1); 2020 sma_out = ioread32(&bp->sma->gpio2); 2021 2022 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp)); 2023 2024 sma1_show(dev, NULL, buf); 2025 seq_printf(s, " sma1: %s", buf); 2026 2027 sma2_show(dev, NULL, buf); 2028 seq_printf(s, " sma2: %s", buf); 2029 2030 sma3_show(dev, NULL, buf); 2031 seq_printf(s, " sma3: %s", buf); 2032 2033 sma4_show(dev, NULL, buf); 2034 seq_printf(s, " sma4: %s", buf); 2035 2036 if (bp->ts0) { 2037 ts_reg = bp->ts0->mem; 2038 on = ioread32(&ts_reg->enable); 2039 src = "GNSS"; 2040 seq_printf(s, "%7s: %s, src: %s\n", "TS0", 2041 on ? " ON" : "OFF", src); 2042 } 2043 2044 if (bp->ts1) { 2045 ts_reg = bp->ts1->mem; 2046 on = ioread32(&ts_reg->enable); 2047 src = gpio_map(sma_in, 2, "sma1", "sma2", "----"); 2048 seq_printf(s, "%7s: %s, src: %s\n", "TS1", 2049 on ? " ON" : "OFF", src); 2050 } 2051 2052 if (bp->ts2) { 2053 ts_reg = bp->ts2->mem; 2054 on = ioread32(&ts_reg->enable); 2055 src = gpio_map(sma_in, 3, "sma1", "sma2", "----"); 2056 seq_printf(s, "%7s: %s, src: %s\n", "TS2", 2057 on ? " ON" : "OFF", src); 2058 } 2059 2060 if (bp->pps) { 2061 ts_reg = bp->pps->mem; 2062 src = "PHC"; 2063 on = ioread32(&ts_reg->enable); 2064 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP); 2065 seq_printf(s, "%7s: %s, src: %s\n", "TS3", 2066 on && map ? " ON" : "OFF", src); 2067 2068 map = !!(bp->pps_req_map & OCP_REQ_PPS); 2069 seq_printf(s, "%7s: %s, src: %s\n", "PPS", 2070 on && map ? " ON" : "OFF", src); 2071 } 2072 2073 if (bp->irig_out) { 2074 ctrl = ioread32(&bp->irig_out->ctrl); 2075 on = ctrl & IRIG_M_CTRL_ENABLE; 2076 val = ioread32(&bp->irig_out->status); 2077 gpio_multi_map(buf, sma_out, 4, "sma3", "sma4", "----"); 2078 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG", 2079 on ? " ON" : "OFF", val, (ctrl >> 16), buf); 2080 } 2081 2082 if (bp->irig_in) { 2083 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE; 2084 val = ioread32(&bp->irig_in->status); 2085 src = gpio_map(sma_in, 4, "sma1", "sma2", "----"); 2086 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in", 2087 on ? " ON" : "OFF", val, src); 2088 } 2089 2090 if (bp->dcf_out) { 2091 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE; 2092 val = ioread32(&bp->dcf_out->status); 2093 gpio_multi_map(buf, sma_out, 5, "sma3", "sma4", "----"); 2094 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", 2095 on ? " ON" : "OFF", val, buf); 2096 } 2097 2098 if (bp->dcf_in) { 2099 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE; 2100 val = ioread32(&bp->dcf_in->status); 2101 src = gpio_map(sma_in, 5, "sma1", "sma2", "----"); 2102 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", 2103 on ? " ON" : "OFF", val, src); 2104 } 2105 2106 if (bp->nmea_out) { 2107 on = ioread32(&bp->nmea_out->ctrl) & 1; 2108 val = ioread32(&bp->nmea_out->status); 2109 seq_printf(s, "%7s: %s, error: %d\n", "NMEA", 2110 on ? " ON" : "OFF", val); 2111 } 2112 2113 /* compute src for PPS1, used below. */ 2114 if (bp->pps_select) { 2115 val = ioread32(&bp->pps_select->gpio1); 2116 if (val & 0x01) 2117 src = gpio_map(sma_in, 0, "sma1", "sma2", "----"); 2118 else if (val & 0x02) 2119 src = "MAC"; 2120 else if (val & 0x04) 2121 src = "GNSS"; 2122 else 2123 src = "----"; 2124 } else { 2125 src = "?"; 2126 } 2127 2128 /* assumes automatic switchover/selection */ 2129 val = ioread32(&bp->reg->select); 2130 switch (val >> 16) { 2131 case 0: 2132 sprintf(buf, "----"); 2133 break; 2134 case 2: 2135 sprintf(buf, "IRIG"); 2136 break; 2137 case 3: 2138 sprintf(buf, "%s via PPS1", src); 2139 break; 2140 case 6: 2141 sprintf(buf, "DCF"); 2142 break; 2143 default: 2144 strcpy(buf, "unknown"); 2145 break; 2146 } 2147 val = ioread32(&bp->reg->status); 2148 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf, 2149 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced"); 2150 2151 /* reuses PPS1 src from earlier */ 2152 seq_printf(s, "MAC PPS1 src: %s\n", src); 2153 2154 src = gpio_map(sma_in, 1, "sma1", "sma2", "GNSS2"); 2155 seq_printf(s, "MAC PPS2 src: %s\n", src); 2156 2157 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) { 2158 struct timespec64 sys_ts; 2159 s64 pre_ns, post_ns, ns; 2160 2161 pre_ns = timespec64_to_ns(&sts.pre_ts); 2162 post_ns = timespec64_to_ns(&sts.post_ts); 2163 ns = (pre_ns + post_ns) / 2; 2164 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC; 2165 sys_ts = ns_to_timespec64(ns); 2166 2167 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC", 2168 ts.tv_sec, ts.tv_nsec, &ts); 2169 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS", 2170 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts, 2171 bp->utc_tai_offset); 2172 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "", 2173 timespec64_to_ns(&ts) - ns, 2174 post_ns - pre_ns); 2175 } 2176 2177 free_page((unsigned long)buf); 2178 return 0; 2179 } 2180 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary); 2181 2182 static struct dentry *ptp_ocp_debugfs_root; 2183 2184 static void 2185 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp) 2186 { 2187 struct dentry *d; 2188 2189 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root); 2190 bp->debug_root = d; 2191 debugfs_create_file("summary", 0444, bp->debug_root, 2192 &bp->dev, &ptp_ocp_summary_fops); 2193 } 2194 2195 static void 2196 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp) 2197 { 2198 debugfs_remove_recursive(bp->debug_root); 2199 } 2200 2201 static void 2202 ptp_ocp_debugfs_init(void) 2203 { 2204 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL); 2205 } 2206 2207 static void 2208 ptp_ocp_debugfs_fini(void) 2209 { 2210 debugfs_remove_recursive(ptp_ocp_debugfs_root); 2211 } 2212 2213 static void 2214 ptp_ocp_dev_release(struct device *dev) 2215 { 2216 struct ptp_ocp *bp = dev_get_drvdata(dev); 2217 2218 mutex_lock(&ptp_ocp_lock); 2219 idr_remove(&ptp_ocp_idr, bp->id); 2220 mutex_unlock(&ptp_ocp_lock); 2221 } 2222 2223 static int 2224 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) 2225 { 2226 int err; 2227 2228 mutex_lock(&ptp_ocp_lock); 2229 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); 2230 mutex_unlock(&ptp_ocp_lock); 2231 if (err < 0) { 2232 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); 2233 return err; 2234 } 2235 bp->id = err; 2236 2237 bp->ptp_info = ptp_ocp_clock_info; 2238 spin_lock_init(&bp->lock); 2239 bp->gnss_port = -1; 2240 bp->gnss2_port = -1; 2241 bp->mac_port = -1; 2242 bp->nmea_port = -1; 2243 bp->pdev = pdev; 2244 2245 device_initialize(&bp->dev); 2246 dev_set_name(&bp->dev, "ocp%d", bp->id); 2247 bp->dev.class = &timecard_class; 2248 bp->dev.parent = &pdev->dev; 2249 bp->dev.release = ptp_ocp_dev_release; 2250 dev_set_drvdata(&bp->dev, bp); 2251 2252 err = device_add(&bp->dev); 2253 if (err) { 2254 dev_err(&bp->dev, "device add failed: %d\n", err); 2255 goto out; 2256 } 2257 2258 pci_set_drvdata(pdev, bp); 2259 2260 return 0; 2261 2262 out: 2263 ptp_ocp_dev_release(&bp->dev); 2264 put_device(&bp->dev); 2265 return err; 2266 } 2267 2268 static void 2269 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) 2270 { 2271 struct device *dev = &bp->dev; 2272 2273 if (sysfs_create_link(&dev->kobj, &child->kobj, link)) 2274 dev_err(dev, "%s symlink failed\n", link); 2275 } 2276 2277 static void 2278 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) 2279 { 2280 struct device *dev, *child; 2281 2282 dev = &bp->pdev->dev; 2283 2284 child = device_find_child_by_name(dev, name); 2285 if (!child) { 2286 dev_err(dev, "Could not find device %s\n", name); 2287 return; 2288 } 2289 2290 ptp_ocp_symlink(bp, child, link); 2291 put_device(child); 2292 } 2293 2294 static int 2295 ptp_ocp_complete(struct ptp_ocp *bp) 2296 { 2297 struct pps_device *pps; 2298 char buf[32]; 2299 2300 if (bp->gnss_port != -1) { 2301 sprintf(buf, "ttyS%d", bp->gnss_port); 2302 ptp_ocp_link_child(bp, buf, "ttyGNSS"); 2303 } 2304 if (bp->gnss2_port != -1) { 2305 sprintf(buf, "ttyS%d", bp->gnss2_port); 2306 ptp_ocp_link_child(bp, buf, "ttyGNSS2"); 2307 } 2308 if (bp->mac_port != -1) { 2309 sprintf(buf, "ttyS%d", bp->mac_port); 2310 ptp_ocp_link_child(bp, buf, "ttyMAC"); 2311 } 2312 if (bp->nmea_port != -1) { 2313 sprintf(buf, "ttyS%d", bp->nmea_port); 2314 ptp_ocp_link_child(bp, buf, "ttyNMEA"); 2315 } 2316 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); 2317 ptp_ocp_link_child(bp, buf, "ptp"); 2318 2319 pps = pps_lookup_dev(bp->ptp); 2320 if (pps) 2321 ptp_ocp_symlink(bp, pps->dev, "pps"); 2322 2323 if (device_add_groups(&bp->dev, timecard_groups)) 2324 pr_err("device add groups failed\n"); 2325 2326 ptp_ocp_debugfs_add_device(bp); 2327 2328 return 0; 2329 } 2330 2331 static void 2332 ptp_ocp_phc_info(struct ptp_ocp *bp) 2333 { 2334 struct timespec64 ts; 2335 u32 version, select; 2336 bool sync; 2337 2338 version = ioread32(&bp->reg->version); 2339 select = ioread32(&bp->reg->select); 2340 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", 2341 version >> 24, (version >> 16) & 0xff, version & 0xffff, 2342 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16), 2343 ptp_clock_index(bp->ptp)); 2344 2345 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 2346 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) 2347 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n", 2348 ts.tv_sec, ts.tv_nsec, 2349 sync ? "in-sync" : "UNSYNCED"); 2350 } 2351 2352 static void 2353 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud) 2354 { 2355 if (port != -1) 2356 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud); 2357 } 2358 2359 static void 2360 ptp_ocp_info(struct ptp_ocp *bp) 2361 { 2362 static int nmea_baud[] = { 2363 1200, 2400, 4800, 9600, 19200, 38400, 2364 57600, 115200, 230400, 460800, 921600, 2365 1000000, 2000000 2366 }; 2367 struct device *dev = &bp->pdev->dev; 2368 u32 reg; 2369 2370 ptp_ocp_phc_info(bp); 2371 if (bp->tod) 2372 ptp_ocp_tod_info(bp); 2373 2374 if (bp->image) { 2375 u32 ver = ioread32(&bp->image->version); 2376 2377 dev_info(dev, "version %x\n", ver); 2378 if (ver & 0xffff) 2379 dev_info(dev, "regular image, version %d\n", 2380 ver & 0xffff); 2381 else 2382 dev_info(dev, "golden image, version %d\n", 2383 ver >> 16); 2384 } 2385 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200); 2386 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200); 2387 ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600); 2388 if (bp->nmea_out && bp->nmea_port != -1) { 2389 int baud = -1; 2390 2391 reg = ioread32(&bp->nmea_out->uart_baud); 2392 if (reg < ARRAY_SIZE(nmea_baud)) 2393 baud = nmea_baud[reg]; 2394 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud); 2395 } 2396 } 2397 2398 static void 2399 ptp_ocp_detach_sysfs(struct ptp_ocp *bp) 2400 { 2401 struct device *dev = &bp->dev; 2402 2403 sysfs_remove_link(&dev->kobj, "ttyGNSS"); 2404 sysfs_remove_link(&dev->kobj, "ttyMAC"); 2405 sysfs_remove_link(&dev->kobj, "ptp"); 2406 sysfs_remove_link(&dev->kobj, "pps"); 2407 device_remove_groups(dev, timecard_groups); 2408 } 2409 2410 static void 2411 ptp_ocp_detach(struct ptp_ocp *bp) 2412 { 2413 ptp_ocp_debugfs_remove_device(bp); 2414 ptp_ocp_detach_sysfs(bp); 2415 if (timer_pending(&bp->watchdog)) 2416 del_timer_sync(&bp->watchdog); 2417 if (bp->ts0) 2418 ptp_ocp_unregister_ext(bp->ts0); 2419 if (bp->ts1) 2420 ptp_ocp_unregister_ext(bp->ts1); 2421 if (bp->ts2) 2422 ptp_ocp_unregister_ext(bp->ts2); 2423 if (bp->pps) 2424 ptp_ocp_unregister_ext(bp->pps); 2425 if (bp->gnss_port != -1) 2426 serial8250_unregister_port(bp->gnss_port); 2427 if (bp->gnss2_port != -1) 2428 serial8250_unregister_port(bp->gnss2_port); 2429 if (bp->mac_port != -1) 2430 serial8250_unregister_port(bp->mac_port); 2431 if (bp->nmea_port != -1) 2432 serial8250_unregister_port(bp->nmea_port); 2433 if (bp->spi_flash) 2434 platform_device_unregister(bp->spi_flash); 2435 if (bp->i2c_ctrl) 2436 platform_device_unregister(bp->i2c_ctrl); 2437 if (bp->i2c_clk) 2438 clk_hw_unregister_fixed_rate(bp->i2c_clk); 2439 if (bp->n_irqs) 2440 pci_free_irq_vectors(bp->pdev); 2441 if (bp->ptp) 2442 ptp_clock_unregister(bp->ptp); 2443 device_unregister(&bp->dev); 2444 } 2445 2446 static int 2447 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2448 { 2449 struct devlink *devlink; 2450 struct ptp_ocp *bp; 2451 int err; 2452 2453 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); 2454 if (!devlink) { 2455 dev_err(&pdev->dev, "devlink_alloc failed\n"); 2456 return -ENOMEM; 2457 } 2458 2459 err = pci_enable_device(pdev); 2460 if (err) { 2461 dev_err(&pdev->dev, "pci_enable_device\n"); 2462 goto out_unregister; 2463 } 2464 2465 bp = devlink_priv(devlink); 2466 err = ptp_ocp_device_init(bp, pdev); 2467 if (err) 2468 goto out_disable; 2469 2470 /* compat mode. 2471 * Older FPGA firmware only returns 2 irq's. 2472 * allow this - if not all of the IRQ's are returned, skip the 2473 * extra devices and just register the clock. 2474 */ 2475 err = pci_alloc_irq_vectors(pdev, 1, 11, PCI_IRQ_MSI | PCI_IRQ_MSIX); 2476 if (err < 0) { 2477 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); 2478 goto out; 2479 } 2480 bp->n_irqs = err; 2481 pci_set_master(pdev); 2482 2483 err = ptp_ocp_register_resources(bp, id->driver_data); 2484 if (err) 2485 goto out; 2486 2487 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); 2488 if (IS_ERR(bp->ptp)) { 2489 err = PTR_ERR(bp->ptp); 2490 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); 2491 bp->ptp = NULL; 2492 goto out; 2493 } 2494 2495 err = ptp_ocp_complete(bp); 2496 if (err) 2497 goto out; 2498 2499 ptp_ocp_info(bp); 2500 devlink_register(devlink); 2501 return 0; 2502 2503 out: 2504 ptp_ocp_detach(bp); 2505 pci_set_drvdata(pdev, NULL); 2506 out_disable: 2507 pci_disable_device(pdev); 2508 out_unregister: 2509 devlink_free(devlink); 2510 return err; 2511 } 2512 2513 static void 2514 ptp_ocp_remove(struct pci_dev *pdev) 2515 { 2516 struct ptp_ocp *bp = pci_get_drvdata(pdev); 2517 struct devlink *devlink = priv_to_devlink(bp); 2518 2519 devlink_unregister(devlink); 2520 ptp_ocp_detach(bp); 2521 pci_set_drvdata(pdev, NULL); 2522 pci_disable_device(pdev); 2523 2524 devlink_free(devlink); 2525 } 2526 2527 static struct pci_driver ptp_ocp_driver = { 2528 .name = KBUILD_MODNAME, 2529 .id_table = ptp_ocp_pcidev_id, 2530 .probe = ptp_ocp_probe, 2531 .remove = ptp_ocp_remove, 2532 }; 2533 2534 static int 2535 ptp_ocp_i2c_notifier_call(struct notifier_block *nb, 2536 unsigned long action, void *data) 2537 { 2538 struct device *dev, *child = data; 2539 struct ptp_ocp *bp; 2540 bool add; 2541 2542 switch (action) { 2543 case BUS_NOTIFY_ADD_DEVICE: 2544 case BUS_NOTIFY_DEL_DEVICE: 2545 add = action == BUS_NOTIFY_ADD_DEVICE; 2546 break; 2547 default: 2548 return 0; 2549 } 2550 2551 if (!i2c_verify_adapter(child)) 2552 return 0; 2553 2554 dev = child; 2555 while ((dev = dev->parent)) 2556 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 2557 goto found; 2558 return 0; 2559 2560 found: 2561 bp = dev_get_drvdata(dev); 2562 if (add) 2563 ptp_ocp_symlink(bp, child, "i2c"); 2564 else 2565 sysfs_remove_link(&bp->dev.kobj, "i2c"); 2566 2567 return 0; 2568 } 2569 2570 static struct notifier_block ptp_ocp_i2c_notifier = { 2571 .notifier_call = ptp_ocp_i2c_notifier_call, 2572 }; 2573 2574 static int __init 2575 ptp_ocp_init(void) 2576 { 2577 const char *what; 2578 int err; 2579 2580 ptp_ocp_debugfs_init(); 2581 2582 what = "timecard class"; 2583 err = class_register(&timecard_class); 2584 if (err) 2585 goto out; 2586 2587 what = "i2c notifier"; 2588 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2589 if (err) 2590 goto out_notifier; 2591 2592 what = "ptp_ocp driver"; 2593 err = pci_register_driver(&ptp_ocp_driver); 2594 if (err) 2595 goto out_register; 2596 2597 return 0; 2598 2599 out_register: 2600 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2601 out_notifier: 2602 class_unregister(&timecard_class); 2603 out: 2604 ptp_ocp_debugfs_fini(); 2605 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); 2606 return err; 2607 } 2608 2609 static void __exit 2610 ptp_ocp_fini(void) 2611 { 2612 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2613 pci_unregister_driver(&ptp_ocp_driver); 2614 class_unregister(&timecard_class); 2615 ptp_ocp_debugfs_fini(); 2616 } 2617 2618 module_init(ptp_ocp_init); 2619 module_exit(ptp_ocp_fini); 2620 2621 MODULE_DESCRIPTION("OpenCompute TimeCard driver"); 2622 MODULE_LICENSE("GPL v2"); 2623