1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * NXP NETC V4 Timer driver 4 * Copyright 2025 NXP 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/fsl/netc_global.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/pci.h> 14 #include <linux/ptp_clock_kernel.h> 15 16 #define NETC_TMR_PCI_VENDOR_NXP 0x1131 17 18 #define NETC_TMR_CTRL 0x0080 19 #define TMR_CTRL_CK_SEL GENMASK(1, 0) 20 #define TMR_CTRL_TE BIT(2) 21 #define TMR_ETEP(i) BIT(8 + (i)) 22 #define TMR_COMP_MODE BIT(15) 23 #define TMR_CTRL_TCLK_PERIOD GENMASK(25, 16) 24 #define TMR_CTRL_FS BIT(28) 25 26 #define NETC_TMR_TEVENT 0x0084 27 #define TMR_TEVNET_PPEN(i) BIT(7 - (i)) 28 #define TMR_TEVENT_PPEN_ALL GENMASK(7, 5) 29 #define TMR_TEVENT_ALMEN(i) BIT(16 + (i)) 30 #define TMR_TEVENT_ETS_THREN(i) BIT(20 + (i)) 31 #define TMR_TEVENT_ETSEN(i) BIT(24 + (i)) 32 #define TMR_TEVENT_ETS_OVEN(i) BIT(28 + (i)) 33 #define TMR_TEVENT_ETS(i) (TMR_TEVENT_ETS_THREN(i) | \ 34 TMR_TEVENT_ETSEN(i) | \ 35 TMR_TEVENT_ETS_OVEN(i)) 36 37 #define NETC_TMR_TEMASK 0x0088 38 #define NETC_TMR_STAT 0x0094 39 #define TMR_STAT_ETS_VLD(i) BIT(24 + (i)) 40 41 #define NETC_TMR_CNT_L 0x0098 42 #define NETC_TMR_CNT_H 0x009c 43 #define NETC_TMR_ADD 0x00a0 44 #define NETC_TMR_PRSC 0x00a8 45 #define NETC_TMR_ECTRL 0x00ac 46 #define NETC_TMR_OFF_L 0x00b0 47 #define NETC_TMR_OFF_H 0x00b4 48 49 /* i = 0, 1, i indicates the index of TMR_ALARM */ 50 #define NETC_TMR_ALARM_L(i) (0x00b8 + (i) * 8) 51 #define NETC_TMR_ALARM_H(i) (0x00bc + (i) * 8) 52 53 /* i = 0, 1, 2. i indicates the index of TMR_FIPER. */ 54 #define NETC_TMR_FIPER(i) (0x00d0 + (i) * 4) 55 56 #define NETC_TMR_FIPER_CTRL 0x00dc 57 #define FIPER_CTRL_DIS(i) (BIT(7) << (i) * 8) 58 #define FIPER_CTRL_PG(i) (BIT(6) << (i) * 8) 59 #define FIPER_CTRL_FS_ALARM(i) (BIT(5) << (i) * 8) 60 #define FIPER_CTRL_PW(i) (GENMASK(4, 0) << (i) * 8) 61 #define FIPER_CTRL_SET_PW(i, v) (((v) & GENMASK(4, 0)) << 8 * (i)) 62 63 /* i = 0, 1, i indicates the index of TMR_ETTS */ 64 #define NETC_TMR_ETTS_L(i) (0x00e0 + (i) * 8) 65 #define NETC_TMR_ETTS_H(i) (0x00e4 + (i) * 8) 66 #define NETC_TMR_CUR_TIME_L 0x00f0 67 #define NETC_TMR_CUR_TIME_H 0x00f4 68 69 #define NETC_TMR_REGS_BAR 0 70 #define NETC_GLOBAL_OFFSET 0x10000 71 #define NETC_GLOBAL_IPBRR0 0xbf8 72 #define IPBRR0_IP_REV GENMASK(15, 0) 73 #define NETC_REV_4_1 0x0401 74 75 #define NETC_TMR_FIPER_NUM 3 76 #define NETC_TMR_INVALID_CHANNEL NETC_TMR_FIPER_NUM 77 #define NETC_TMR_DEFAULT_PRSC 2 78 #define NETC_TMR_DEFAULT_ALARM GENMASK_ULL(63, 0) 79 #define NETC_TMR_DEFAULT_FIPER GENMASK(31, 0) 80 #define NETC_TMR_FIPER_MAX_PW GENMASK(4, 0) 81 #define NETC_TMR_ALARM_NUM 2 82 #define NETC_TMR_DEFAULT_ETTF_THR 7 83 84 /* 1588 timer reference clock source select */ 85 #define NETC_TMR_CCM_TIMER1 0 /* enet_timer1_clk_root, from CCM */ 86 #define NETC_TMR_SYSTEM_CLK 1 /* enet_clk_root/2, from CCM */ 87 #define NETC_TMR_EXT_OSC 2 /* tmr_1588_clk, from IO pins */ 88 89 #define NETC_TMR_SYSCLK_333M 333333333U 90 91 enum netc_pp_type { 92 NETC_PP_PPS = 1, 93 NETC_PP_PEROUT, 94 }; 95 96 struct netc_pp { 97 enum netc_pp_type type; 98 bool enabled; 99 int alarm_id; 100 u32 period; /* pulse period, ns */ 101 u64 stime; /* start time, ns */ 102 }; 103 104 struct netc_timer { 105 void __iomem *base; 106 struct pci_dev *pdev; 107 spinlock_t lock; /* Prevent concurrent access to registers */ 108 109 struct ptp_clock *clock; 110 struct ptp_clock_info caps; 111 u32 clk_select; 112 u32 clk_freq; 113 u32 oclk_prsc; 114 /* High 32-bit is integer part, low 32-bit is fractional part */ 115 u64 period; 116 117 int irq; 118 char irq_name[24]; 119 int revision; 120 u32 tmr_emask; 121 u8 pps_channel; 122 u8 fs_alarm_num; 123 u8 fs_alarm_bitmap; 124 struct netc_pp pp[NETC_TMR_FIPER_NUM]; /* periodic pulse */ 125 }; 126 127 #define netc_timer_rd(p, o) netc_read((p)->base + (o)) 128 #define netc_timer_wr(p, o, v) netc_write((p)->base + (o), v) 129 #define ptp_to_netc_timer(ptp) container_of((ptp), struct netc_timer, caps) 130 131 static const char *const timer_clk_src[] = { 132 "ccm", 133 "ext" 134 }; 135 136 static void netc_timer_cnt_write(struct netc_timer *priv, u64 ns) 137 { 138 u32 tmr_cnt_h = upper_32_bits(ns); 139 u32 tmr_cnt_l = lower_32_bits(ns); 140 141 /* Writes to the TMR_CNT_L register copies the written value 142 * into the shadow TMR_CNT_L register. Writes to the TMR_CNT_H 143 * register copies the values written into the shadow TMR_CNT_H 144 * register. Contents of the shadow registers are copied into 145 * the TMR_CNT_L and TMR_CNT_H registers following a write into 146 * the TMR_CNT_H register. So the user must writes to TMR_CNT_L 147 * register first. Other H/L registers should have the same 148 * behavior. 149 */ 150 netc_timer_wr(priv, NETC_TMR_CNT_L, tmr_cnt_l); 151 netc_timer_wr(priv, NETC_TMR_CNT_H, tmr_cnt_h); 152 } 153 154 static u64 netc_timer_offset_read(struct netc_timer *priv) 155 { 156 u32 tmr_off_l, tmr_off_h; 157 u64 offset; 158 159 tmr_off_l = netc_timer_rd(priv, NETC_TMR_OFF_L); 160 tmr_off_h = netc_timer_rd(priv, NETC_TMR_OFF_H); 161 offset = (((u64)tmr_off_h) << 32) | tmr_off_l; 162 163 return offset; 164 } 165 166 static void netc_timer_offset_write(struct netc_timer *priv, u64 offset) 167 { 168 u32 tmr_off_h = upper_32_bits(offset); 169 u32 tmr_off_l = lower_32_bits(offset); 170 171 netc_timer_wr(priv, NETC_TMR_OFF_L, tmr_off_l); 172 netc_timer_wr(priv, NETC_TMR_OFF_H, tmr_off_h); 173 } 174 175 static u64 netc_timer_cur_time_read(struct netc_timer *priv) 176 { 177 u32 time_h, time_l; 178 u64 ns; 179 180 /* The user should read NETC_TMR_CUR_TIME_L first to 181 * get correct current time. 182 */ 183 time_l = netc_timer_rd(priv, NETC_TMR_CUR_TIME_L); 184 time_h = netc_timer_rd(priv, NETC_TMR_CUR_TIME_H); 185 ns = (u64)time_h << 32 | time_l; 186 187 return ns; 188 } 189 190 static void netc_timer_alarm_write(struct netc_timer *priv, 191 u64 alarm, int index) 192 { 193 u32 alarm_h = upper_32_bits(alarm); 194 u32 alarm_l = lower_32_bits(alarm); 195 196 netc_timer_wr(priv, NETC_TMR_ALARM_L(index), alarm_l); 197 netc_timer_wr(priv, NETC_TMR_ALARM_H(index), alarm_h); 198 } 199 200 static u32 netc_timer_get_integral_period(struct netc_timer *priv) 201 { 202 u32 tmr_ctrl, integral_period; 203 204 tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL); 205 integral_period = FIELD_GET(TMR_CTRL_TCLK_PERIOD, tmr_ctrl); 206 207 return integral_period; 208 } 209 210 static u32 netc_timer_calculate_fiper_pw(struct netc_timer *priv, 211 u32 fiper) 212 { 213 u64 divisor, pulse_width; 214 215 /* Set the FIPER pulse width to half FIPER interval by default. 216 * pulse_width = (fiper / 2) / TMR_GCLK_period, 217 * TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq, 218 * TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz, 219 * so pulse_width = fiper * clk_freq / (2 * NSEC_PER_SEC * oclk_prsc). 220 */ 221 divisor = mul_u32_u32(2 * NSEC_PER_SEC, priv->oclk_prsc); 222 pulse_width = div64_u64(mul_u32_u32(fiper, priv->clk_freq), divisor); 223 224 /* The FIPER_PW field only has 5 bits, need to update oclk_prsc */ 225 if (pulse_width > NETC_TMR_FIPER_MAX_PW) 226 pulse_width = NETC_TMR_FIPER_MAX_PW; 227 228 return pulse_width; 229 } 230 231 static void netc_timer_set_pps_alarm(struct netc_timer *priv, int channel, 232 u32 integral_period) 233 { 234 struct netc_pp *pp = &priv->pp[channel]; 235 u64 alarm; 236 237 /* Get the alarm value */ 238 alarm = netc_timer_cur_time_read(priv) + NSEC_PER_MSEC; 239 alarm = roundup_u64(alarm, NSEC_PER_SEC); 240 alarm = roundup_u64(alarm, integral_period); 241 242 netc_timer_alarm_write(priv, alarm, pp->alarm_id); 243 } 244 245 static void netc_timer_set_perout_alarm(struct netc_timer *priv, int channel, 246 u32 integral_period) 247 { 248 u64 cur_time = netc_timer_cur_time_read(priv); 249 struct netc_pp *pp = &priv->pp[channel]; 250 u64 alarm, delta, min_time; 251 u32 period = pp->period; 252 u64 stime = pp->stime; 253 254 min_time = cur_time + NSEC_PER_MSEC + period; 255 if (stime < min_time) { 256 delta = min_time - stime; 257 stime += roundup_u64(delta, period); 258 } 259 260 alarm = roundup_u64(stime - period, integral_period); 261 netc_timer_alarm_write(priv, alarm, pp->alarm_id); 262 } 263 264 static int netc_timer_get_alarm_id(struct netc_timer *priv) 265 { 266 int i; 267 268 for (i = 0; i < priv->fs_alarm_num; i++) { 269 if (!(priv->fs_alarm_bitmap & BIT(i))) { 270 priv->fs_alarm_bitmap |= BIT(i); 271 break; 272 } 273 } 274 275 return i; 276 } 277 278 static u64 netc_timer_get_gclk_period(struct netc_timer *priv) 279 { 280 /* TMR_GCLK_freq = (clk_freq / oclk_prsc) Hz. 281 * TMR_GCLK_period = NSEC_PER_SEC / TMR_GCLK_freq. 282 * TMR_GCLK_period = (NSEC_PER_SEC * oclk_prsc) / clk_freq 283 */ 284 285 return div_u64(mul_u32_u32(NSEC_PER_SEC, priv->oclk_prsc), 286 priv->clk_freq); 287 } 288 289 static void netc_timer_enable_periodic_pulse(struct netc_timer *priv, 290 u8 channel) 291 { 292 u32 fiper_pw, fiper, fiper_ctrl, integral_period; 293 struct netc_pp *pp = &priv->pp[channel]; 294 int alarm_id = pp->alarm_id; 295 296 integral_period = netc_timer_get_integral_period(priv); 297 /* Set to desired FIPER interval in ns - TCLK_PERIOD */ 298 fiper = pp->period - integral_period; 299 fiper_pw = netc_timer_calculate_fiper_pw(priv, fiper); 300 301 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL); 302 fiper_ctrl &= ~(FIPER_CTRL_DIS(channel) | FIPER_CTRL_PW(channel) | 303 FIPER_CTRL_FS_ALARM(channel)); 304 fiper_ctrl |= FIPER_CTRL_SET_PW(channel, fiper_pw); 305 fiper_ctrl |= alarm_id ? FIPER_CTRL_FS_ALARM(channel) : 0; 306 307 priv->tmr_emask |= TMR_TEVNET_PPEN(channel) | 308 TMR_TEVENT_ALMEN(alarm_id); 309 310 if (pp->type == NETC_PP_PPS) 311 netc_timer_set_pps_alarm(priv, channel, integral_period); 312 else 313 netc_timer_set_perout_alarm(priv, channel, integral_period); 314 315 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask); 316 netc_timer_wr(priv, NETC_TMR_FIPER(channel), fiper); 317 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl); 318 } 319 320 static void netc_timer_disable_periodic_pulse(struct netc_timer *priv, 321 u8 channel) 322 { 323 struct netc_pp *pp = &priv->pp[channel]; 324 int alarm_id = pp->alarm_id; 325 u32 fiper_ctrl; 326 327 if (!pp->enabled) 328 return; 329 330 priv->tmr_emask &= ~(TMR_TEVNET_PPEN(channel) | 331 TMR_TEVENT_ALMEN(alarm_id)); 332 333 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL); 334 fiper_ctrl |= FIPER_CTRL_DIS(channel); 335 336 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, alarm_id); 337 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask); 338 netc_timer_wr(priv, NETC_TMR_FIPER(channel), NETC_TMR_DEFAULT_FIPER); 339 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl); 340 } 341 342 static u8 netc_timer_select_pps_channel(struct netc_timer *priv) 343 { 344 int i; 345 346 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) { 347 if (!priv->pp[i].enabled) 348 return i; 349 } 350 351 return NETC_TMR_INVALID_CHANNEL; 352 } 353 354 /* Note that users should not use this API to output PPS signal on 355 * external pins, because PTP_CLK_REQ_PPS trigger internal PPS event 356 * for input into kernel PPS subsystem. See: 357 * https://lore.kernel.org/r/20201117213826.18235-1-a.fatoum@pengutronix.de 358 */ 359 static int netc_timer_enable_pps(struct netc_timer *priv, 360 struct ptp_clock_request *rq, int on) 361 { 362 struct device *dev = &priv->pdev->dev; 363 unsigned long flags; 364 struct netc_pp *pp; 365 int err = 0; 366 367 spin_lock_irqsave(&priv->lock, flags); 368 369 if (on) { 370 int alarm_id; 371 u8 channel; 372 373 if (priv->pps_channel < NETC_TMR_FIPER_NUM) { 374 channel = priv->pps_channel; 375 } else { 376 channel = netc_timer_select_pps_channel(priv); 377 if (channel == NETC_TMR_INVALID_CHANNEL) { 378 dev_err(dev, "No available FIPERs\n"); 379 err = -EBUSY; 380 goto unlock_spinlock; 381 } 382 } 383 384 pp = &priv->pp[channel]; 385 if (pp->enabled) 386 goto unlock_spinlock; 387 388 alarm_id = netc_timer_get_alarm_id(priv); 389 if (alarm_id == priv->fs_alarm_num) { 390 dev_err(dev, "No available ALARMs\n"); 391 err = -EBUSY; 392 goto unlock_spinlock; 393 } 394 395 pp->enabled = true; 396 pp->type = NETC_PP_PPS; 397 pp->alarm_id = alarm_id; 398 pp->period = NSEC_PER_SEC; 399 priv->pps_channel = channel; 400 401 netc_timer_enable_periodic_pulse(priv, channel); 402 } else { 403 /* pps_channel is invalid if PPS is not enabled, so no 404 * processing is needed. 405 */ 406 if (priv->pps_channel >= NETC_TMR_FIPER_NUM) 407 goto unlock_spinlock; 408 409 netc_timer_disable_periodic_pulse(priv, priv->pps_channel); 410 pp = &priv->pp[priv->pps_channel]; 411 priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id); 412 memset(pp, 0, sizeof(*pp)); 413 priv->pps_channel = NETC_TMR_INVALID_CHANNEL; 414 } 415 416 unlock_spinlock: 417 spin_unlock_irqrestore(&priv->lock, flags); 418 419 return err; 420 } 421 422 static int net_timer_enable_perout(struct netc_timer *priv, 423 struct ptp_clock_request *rq, int on) 424 { 425 struct device *dev = &priv->pdev->dev; 426 u32 channel = rq->perout.index; 427 unsigned long flags; 428 struct netc_pp *pp; 429 int err = 0; 430 431 spin_lock_irqsave(&priv->lock, flags); 432 433 pp = &priv->pp[channel]; 434 if (pp->type == NETC_PP_PPS) { 435 dev_err(dev, "FIPER%u is being used for PPS\n", channel); 436 err = -EBUSY; 437 goto unlock_spinlock; 438 } 439 440 if (on) { 441 u64 period_ns, gclk_period, max_period, min_period; 442 struct timespec64 period, stime; 443 u32 integral_period; 444 int alarm_id; 445 446 period.tv_sec = rq->perout.period.sec; 447 period.tv_nsec = rq->perout.period.nsec; 448 period_ns = timespec64_to_ns(&period); 449 450 integral_period = netc_timer_get_integral_period(priv); 451 max_period = (u64)NETC_TMR_DEFAULT_FIPER + integral_period; 452 gclk_period = netc_timer_get_gclk_period(priv); 453 min_period = gclk_period * 4 + integral_period; 454 if (period_ns > max_period || period_ns < min_period) { 455 dev_err(dev, "The period range is %llu ~ %llu\n", 456 min_period, max_period); 457 err = -EINVAL; 458 goto unlock_spinlock; 459 } 460 461 if (pp->enabled) { 462 alarm_id = pp->alarm_id; 463 } else { 464 alarm_id = netc_timer_get_alarm_id(priv); 465 if (alarm_id == priv->fs_alarm_num) { 466 dev_err(dev, "No available ALARMs\n"); 467 err = -EBUSY; 468 goto unlock_spinlock; 469 } 470 471 pp->type = NETC_PP_PEROUT; 472 pp->enabled = true; 473 pp->alarm_id = alarm_id; 474 } 475 476 stime.tv_sec = rq->perout.start.sec; 477 stime.tv_nsec = rq->perout.start.nsec; 478 pp->stime = timespec64_to_ns(&stime); 479 pp->period = period_ns; 480 481 netc_timer_enable_periodic_pulse(priv, channel); 482 } else { 483 netc_timer_disable_periodic_pulse(priv, channel); 484 priv->fs_alarm_bitmap &= ~BIT(pp->alarm_id); 485 memset(pp, 0, sizeof(*pp)); 486 } 487 488 unlock_spinlock: 489 spin_unlock_irqrestore(&priv->lock, flags); 490 491 return err; 492 } 493 494 static void netc_timer_handle_etts_event(struct netc_timer *priv, int index, 495 bool update_event) 496 { 497 struct ptp_clock_event event; 498 u32 etts_l = 0, etts_h = 0; 499 500 while (netc_timer_rd(priv, NETC_TMR_STAT) & TMR_STAT_ETS_VLD(index)) { 501 etts_l = netc_timer_rd(priv, NETC_TMR_ETTS_L(index)); 502 etts_h = netc_timer_rd(priv, NETC_TMR_ETTS_H(index)); 503 } 504 505 /* Invalid time stamp */ 506 if (!etts_l && !etts_h) 507 return; 508 509 if (update_event) { 510 event.type = PTP_CLOCK_EXTTS; 511 event.index = index; 512 event.timestamp = (u64)etts_h << 32; 513 event.timestamp |= etts_l; 514 ptp_clock_event(priv->clock, &event); 515 } 516 } 517 518 static int netc_timer_enable_extts(struct netc_timer *priv, 519 struct ptp_clock_request *rq, int on) 520 { 521 int index = rq->extts.index; 522 unsigned long flags; 523 u32 tmr_ctrl; 524 525 /* Reject requests to enable time stamping on both edges */ 526 if ((rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES) 527 return -EOPNOTSUPP; 528 529 spin_lock_irqsave(&priv->lock, flags); 530 531 netc_timer_handle_etts_event(priv, rq->extts.index, false); 532 if (on) { 533 tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL); 534 if (rq->extts.flags & PTP_FALLING_EDGE) 535 tmr_ctrl |= TMR_ETEP(index); 536 else 537 tmr_ctrl &= ~TMR_ETEP(index); 538 539 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl); 540 priv->tmr_emask |= TMR_TEVENT_ETS(index); 541 } else { 542 priv->tmr_emask &= ~TMR_TEVENT_ETS(index); 543 } 544 545 netc_timer_wr(priv, NETC_TMR_TEMASK, priv->tmr_emask); 546 547 spin_unlock_irqrestore(&priv->lock, flags); 548 549 return 0; 550 } 551 552 static void netc_timer_disable_fiper(struct netc_timer *priv) 553 { 554 u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL); 555 int i; 556 557 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) { 558 if (!priv->pp[i].enabled) 559 continue; 560 561 fiper_ctrl |= FIPER_CTRL_DIS(i); 562 netc_timer_wr(priv, NETC_TMR_FIPER(i), NETC_TMR_DEFAULT_FIPER); 563 } 564 565 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl); 566 } 567 568 static void netc_timer_enable_fiper(struct netc_timer *priv) 569 { 570 u32 integral_period = netc_timer_get_integral_period(priv); 571 u32 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL); 572 int i; 573 574 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) { 575 struct netc_pp *pp = &priv->pp[i]; 576 u32 fiper; 577 578 if (!pp->enabled) 579 continue; 580 581 fiper_ctrl &= ~FIPER_CTRL_DIS(i); 582 583 if (pp->type == NETC_PP_PPS) 584 netc_timer_set_pps_alarm(priv, i, integral_period); 585 else if (pp->type == NETC_PP_PEROUT) 586 netc_timer_set_perout_alarm(priv, i, integral_period); 587 588 fiper = pp->period - integral_period; 589 netc_timer_wr(priv, NETC_TMR_FIPER(i), fiper); 590 } 591 592 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl); 593 } 594 595 static int netc_timer_enable(struct ptp_clock_info *ptp, 596 struct ptp_clock_request *rq, int on) 597 { 598 struct netc_timer *priv = ptp_to_netc_timer(ptp); 599 600 switch (rq->type) { 601 case PTP_CLK_REQ_PPS: 602 return netc_timer_enable_pps(priv, rq, on); 603 case PTP_CLK_REQ_PEROUT: 604 return net_timer_enable_perout(priv, rq, on); 605 case PTP_CLK_REQ_EXTTS: 606 return netc_timer_enable_extts(priv, rq, on); 607 default: 608 return -EOPNOTSUPP; 609 } 610 } 611 612 static void netc_timer_adjust_period(struct netc_timer *priv, u64 period) 613 { 614 u32 fractional_period = lower_32_bits(period); 615 u32 integral_period = upper_32_bits(period); 616 u32 tmr_ctrl, old_tmr_ctrl; 617 unsigned long flags; 618 619 spin_lock_irqsave(&priv->lock, flags); 620 621 old_tmr_ctrl = netc_timer_rd(priv, NETC_TMR_CTRL); 622 tmr_ctrl = u32_replace_bits(old_tmr_ctrl, integral_period, 623 TMR_CTRL_TCLK_PERIOD); 624 if (tmr_ctrl != old_tmr_ctrl) { 625 netc_timer_disable_fiper(priv); 626 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl); 627 netc_timer_enable_fiper(priv); 628 } 629 630 netc_timer_wr(priv, NETC_TMR_ADD, fractional_period); 631 632 spin_unlock_irqrestore(&priv->lock, flags); 633 } 634 635 static int netc_timer_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 636 { 637 struct netc_timer *priv = ptp_to_netc_timer(ptp); 638 u64 new_period; 639 640 new_period = adjust_by_scaled_ppm(priv->period, scaled_ppm); 641 netc_timer_adjust_period(priv, new_period); 642 643 return 0; 644 } 645 646 static int netc_timer_adjtime(struct ptp_clock_info *ptp, s64 delta) 647 { 648 struct netc_timer *priv = ptp_to_netc_timer(ptp); 649 unsigned long flags; 650 s64 tmr_off; 651 652 spin_lock_irqsave(&priv->lock, flags); 653 654 netc_timer_disable_fiper(priv); 655 656 /* Adjusting TMROFF instead of TMR_CNT is that the timer 657 * counter keeps increasing during reading and writing 658 * TMR_CNT, which will cause latency. 659 */ 660 tmr_off = netc_timer_offset_read(priv); 661 tmr_off += delta; 662 netc_timer_offset_write(priv, tmr_off); 663 664 netc_timer_enable_fiper(priv); 665 666 spin_unlock_irqrestore(&priv->lock, flags); 667 668 return 0; 669 } 670 671 static int netc_timer_gettimex64(struct ptp_clock_info *ptp, 672 struct timespec64 *ts, 673 struct ptp_system_timestamp *sts) 674 { 675 struct netc_timer *priv = ptp_to_netc_timer(ptp); 676 unsigned long flags; 677 u64 ns; 678 679 spin_lock_irqsave(&priv->lock, flags); 680 681 ptp_read_system_prets(sts); 682 ns = netc_timer_cur_time_read(priv); 683 ptp_read_system_postts(sts); 684 685 spin_unlock_irqrestore(&priv->lock, flags); 686 687 *ts = ns_to_timespec64(ns); 688 689 return 0; 690 } 691 692 static int netc_timer_settime64(struct ptp_clock_info *ptp, 693 const struct timespec64 *ts) 694 { 695 struct netc_timer *priv = ptp_to_netc_timer(ptp); 696 u64 ns = timespec64_to_ns(ts); 697 unsigned long flags; 698 699 spin_lock_irqsave(&priv->lock, flags); 700 701 netc_timer_disable_fiper(priv); 702 netc_timer_offset_write(priv, 0); 703 netc_timer_cnt_write(priv, ns); 704 netc_timer_enable_fiper(priv); 705 706 spin_unlock_irqrestore(&priv->lock, flags); 707 708 return 0; 709 } 710 711 static const struct ptp_clock_info netc_timer_ptp_caps = { 712 .owner = THIS_MODULE, 713 .name = "NETC Timer PTP clock", 714 .max_adj = 500000000, 715 .n_pins = 0, 716 .n_alarm = 2, 717 .pps = 1, 718 .n_per_out = 3, 719 .n_ext_ts = 2, 720 .supported_extts_flags = PTP_RISING_EDGE | PTP_FALLING_EDGE | 721 PTP_STRICT_FLAGS, 722 .adjfine = netc_timer_adjfine, 723 .adjtime = netc_timer_adjtime, 724 .gettimex64 = netc_timer_gettimex64, 725 .settime64 = netc_timer_settime64, 726 .enable = netc_timer_enable, 727 }; 728 729 static void netc_timer_init(struct netc_timer *priv) 730 { 731 u32 fractional_period = lower_32_bits(priv->period); 732 u32 integral_period = upper_32_bits(priv->period); 733 u32 tmr_ctrl, fiper_ctrl; 734 struct timespec64 now; 735 u64 ns; 736 int i; 737 738 /* Software must enable timer first and the clock selected must be 739 * active, otherwise, the registers which are in the timer clock 740 * domain are not accessible. 741 */ 742 tmr_ctrl = FIELD_PREP(TMR_CTRL_CK_SEL, priv->clk_select) | 743 TMR_CTRL_TE | TMR_CTRL_FS; 744 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl); 745 netc_timer_wr(priv, NETC_TMR_PRSC, priv->oclk_prsc); 746 747 /* Disable FIPER by default */ 748 fiper_ctrl = netc_timer_rd(priv, NETC_TMR_FIPER_CTRL); 749 for (i = 0; i < NETC_TMR_FIPER_NUM; i++) { 750 fiper_ctrl |= FIPER_CTRL_DIS(i); 751 fiper_ctrl &= ~FIPER_CTRL_PG(i); 752 } 753 netc_timer_wr(priv, NETC_TMR_FIPER_CTRL, fiper_ctrl); 754 netc_timer_wr(priv, NETC_TMR_ECTRL, NETC_TMR_DEFAULT_ETTF_THR); 755 756 ktime_get_real_ts64(&now); 757 ns = timespec64_to_ns(&now); 758 netc_timer_cnt_write(priv, ns); 759 760 /* Allow atomic writes to TCLK_PERIOD and TMR_ADD, An update to 761 * TCLK_PERIOD does not take effect until TMR_ADD is written. 762 */ 763 tmr_ctrl |= FIELD_PREP(TMR_CTRL_TCLK_PERIOD, integral_period) | 764 TMR_COMP_MODE; 765 netc_timer_wr(priv, NETC_TMR_CTRL, tmr_ctrl); 766 netc_timer_wr(priv, NETC_TMR_ADD, fractional_period); 767 } 768 769 static int netc_timer_pci_probe(struct pci_dev *pdev) 770 { 771 struct device *dev = &pdev->dev; 772 struct netc_timer *priv; 773 int err; 774 775 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 776 if (!priv) 777 return -ENOMEM; 778 779 pcie_flr(pdev); 780 err = pci_enable_device_mem(pdev); 781 if (err) 782 return dev_err_probe(dev, err, "Failed to enable device\n"); 783 784 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 785 err = pci_request_mem_regions(pdev, KBUILD_MODNAME); 786 if (err) { 787 dev_err(dev, "pci_request_regions() failed, err:%pe\n", 788 ERR_PTR(err)); 789 goto disable_dev; 790 } 791 792 pci_set_master(pdev); 793 794 priv->pdev = pdev; 795 priv->base = pci_ioremap_bar(pdev, NETC_TMR_REGS_BAR); 796 if (!priv->base) { 797 err = -ENOMEM; 798 goto release_mem_regions; 799 } 800 801 pci_set_drvdata(pdev, priv); 802 803 return 0; 804 805 release_mem_regions: 806 pci_release_mem_regions(pdev); 807 disable_dev: 808 pci_disable_device(pdev); 809 810 return err; 811 } 812 813 static void netc_timer_pci_remove(struct pci_dev *pdev) 814 { 815 struct netc_timer *priv = pci_get_drvdata(pdev); 816 817 iounmap(priv->base); 818 pci_release_mem_regions(pdev); 819 pci_disable_device(pdev); 820 } 821 822 static int netc_timer_get_reference_clk_source(struct netc_timer *priv) 823 { 824 struct device *dev = &priv->pdev->dev; 825 struct clk *clk; 826 int i; 827 828 /* Select NETC system clock as the reference clock by default */ 829 priv->clk_select = NETC_TMR_SYSTEM_CLK; 830 priv->clk_freq = NETC_TMR_SYSCLK_333M; 831 832 /* Update the clock source of the reference clock if the clock 833 * is specified in DT node. 834 */ 835 for (i = 0; i < ARRAY_SIZE(timer_clk_src); i++) { 836 clk = devm_clk_get_optional_enabled(dev, timer_clk_src[i]); 837 if (IS_ERR(clk)) 838 return dev_err_probe(dev, PTR_ERR(clk), 839 "Failed to enable clock\n"); 840 841 if (clk) { 842 priv->clk_freq = clk_get_rate(clk); 843 priv->clk_select = i ? NETC_TMR_EXT_OSC : 844 NETC_TMR_CCM_TIMER1; 845 break; 846 } 847 } 848 849 /* The period is a 64-bit number, the high 32-bit is the integer 850 * part of the period, the low 32-bit is the fractional part of 851 * the period. In order to get the desired 32-bit fixed-point 852 * format, multiply the numerator of the fraction by 2^32. 853 */ 854 priv->period = div_u64((u64)NSEC_PER_SEC << 32, priv->clk_freq); 855 856 return 0; 857 } 858 859 static int netc_timer_parse_dt(struct netc_timer *priv) 860 { 861 return netc_timer_get_reference_clk_source(priv); 862 } 863 864 static irqreturn_t netc_timer_isr(int irq, void *data) 865 { 866 struct netc_timer *priv = data; 867 struct ptp_clock_event event; 868 u32 tmr_event; 869 870 spin_lock(&priv->lock); 871 872 tmr_event = netc_timer_rd(priv, NETC_TMR_TEVENT); 873 tmr_event &= priv->tmr_emask; 874 /* Clear interrupts status */ 875 netc_timer_wr(priv, NETC_TMR_TEVENT, tmr_event); 876 877 if (tmr_event & TMR_TEVENT_ALMEN(0)) 878 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 0); 879 880 if (tmr_event & TMR_TEVENT_ALMEN(1)) 881 netc_timer_alarm_write(priv, NETC_TMR_DEFAULT_ALARM, 1); 882 883 if (tmr_event & TMR_TEVENT_PPEN_ALL) { 884 event.type = PTP_CLOCK_PPS; 885 ptp_clock_event(priv->clock, &event); 886 } 887 888 if (tmr_event & TMR_TEVENT_ETS(0)) 889 netc_timer_handle_etts_event(priv, 0, true); 890 891 if (tmr_event & TMR_TEVENT_ETS(1)) 892 netc_timer_handle_etts_event(priv, 1, true); 893 894 spin_unlock(&priv->lock); 895 896 return IRQ_HANDLED; 897 } 898 899 static int netc_timer_init_msix_irq(struct netc_timer *priv) 900 { 901 struct pci_dev *pdev = priv->pdev; 902 int err, n; 903 904 n = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX); 905 if (n != 1) { 906 err = (n < 0) ? n : -EPERM; 907 dev_err(&pdev->dev, "pci_alloc_irq_vectors() failed\n"); 908 return err; 909 } 910 911 priv->irq = pci_irq_vector(pdev, 0); 912 err = request_irq(priv->irq, netc_timer_isr, 0, priv->irq_name, priv); 913 if (err) { 914 dev_err(&pdev->dev, "request_irq() failed\n"); 915 pci_free_irq_vectors(pdev); 916 917 return err; 918 } 919 920 return 0; 921 } 922 923 static void netc_timer_free_msix_irq(struct netc_timer *priv) 924 { 925 struct pci_dev *pdev = priv->pdev; 926 927 disable_irq(priv->irq); 928 free_irq(priv->irq, priv); 929 pci_free_irq_vectors(pdev); 930 } 931 932 static int netc_timer_get_global_ip_rev(struct netc_timer *priv) 933 { 934 u32 val; 935 936 val = netc_timer_rd(priv, NETC_GLOBAL_OFFSET + NETC_GLOBAL_IPBRR0); 937 938 return val & IPBRR0_IP_REV; 939 } 940 941 static int netc_timer_probe(struct pci_dev *pdev, 942 const struct pci_device_id *id) 943 { 944 struct device *dev = &pdev->dev; 945 struct netc_timer *priv; 946 int err; 947 948 err = netc_timer_pci_probe(pdev); 949 if (err) 950 return err; 951 952 priv = pci_get_drvdata(pdev); 953 priv->revision = netc_timer_get_global_ip_rev(priv); 954 if (priv->revision == NETC_REV_4_1) 955 priv->fs_alarm_num = 1; 956 else 957 priv->fs_alarm_num = NETC_TMR_ALARM_NUM; 958 959 err = netc_timer_parse_dt(priv); 960 if (err) 961 goto timer_pci_remove; 962 963 priv->caps = netc_timer_ptp_caps; 964 priv->oclk_prsc = NETC_TMR_DEFAULT_PRSC; 965 priv->pps_channel = NETC_TMR_INVALID_CHANNEL; 966 spin_lock_init(&priv->lock); 967 snprintf(priv->irq_name, sizeof(priv->irq_name), "ptp-netc %s", 968 pci_name(pdev)); 969 970 err = netc_timer_init_msix_irq(priv); 971 if (err) 972 goto timer_pci_remove; 973 974 netc_timer_init(priv); 975 priv->clock = ptp_clock_register(&priv->caps, dev); 976 if (IS_ERR(priv->clock)) { 977 err = PTR_ERR(priv->clock); 978 goto free_msix_irq; 979 } 980 981 return 0; 982 983 free_msix_irq: 984 netc_timer_free_msix_irq(priv); 985 timer_pci_remove: 986 netc_timer_pci_remove(pdev); 987 988 return err; 989 } 990 991 static void netc_timer_remove(struct pci_dev *pdev) 992 { 993 struct netc_timer *priv = pci_get_drvdata(pdev); 994 995 netc_timer_wr(priv, NETC_TMR_TEMASK, 0); 996 netc_timer_wr(priv, NETC_TMR_CTRL, 0); 997 ptp_clock_unregister(priv->clock); 998 netc_timer_free_msix_irq(priv); 999 netc_timer_pci_remove(pdev); 1000 } 1001 1002 static const struct pci_device_id netc_timer_id_table[] = { 1003 { PCI_DEVICE(NETC_TMR_PCI_VENDOR_NXP, 0xee02) }, 1004 { } 1005 }; 1006 MODULE_DEVICE_TABLE(pci, netc_timer_id_table); 1007 1008 static struct pci_driver netc_timer_driver = { 1009 .name = KBUILD_MODNAME, 1010 .id_table = netc_timer_id_table, 1011 .probe = netc_timer_probe, 1012 .remove = netc_timer_remove, 1013 }; 1014 module_pci_driver(netc_timer_driver); 1015 1016 MODULE_DESCRIPTION("NXP NETC Timer PTP Driver"); 1017 MODULE_LICENSE("Dual BSD/GPL"); 1018