1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright 2017 Broadcom 3 4 #include <linux/err.h> 5 #include <linux/io.h> 6 #include <linux/module.h> 7 #include <linux/platform_device.h> 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/types.h> 10 11 #define DTE_NCO_LOW_TIME_REG 0x00 12 #define DTE_NCO_TIME_REG 0x04 13 #define DTE_NCO_OVERFLOW_REG 0x08 14 #define DTE_NCO_INC_REG 0x0c 15 16 #define DTE_NCO_SUM2_MASK 0xffffffff 17 #define DTE_NCO_SUM2_SHIFT 4ULL 18 19 #define DTE_NCO_SUM3_MASK 0xff 20 #define DTE_NCO_SUM3_SHIFT 36ULL 21 #define DTE_NCO_SUM3_WR_SHIFT 8 22 23 #define DTE_NCO_TS_WRAP_MASK 0xfff 24 #define DTE_NCO_TS_WRAP_LSHIFT 32 25 26 #define DTE_NCO_INC_DEFAULT 0x80000000 27 #define DTE_NUM_REGS_TO_RESTORE 4 28 29 /* Full wrap around is 44bits in ns (~4.887 hrs) */ 30 #define DTE_WRAP_AROUND_NSEC_SHIFT 44 31 32 /* 44 bits NCO */ 33 #define DTE_NCO_MAX_NS 0xFFFFFFFFFFFLL 34 35 /* 125MHz with 3.29 reg cfg */ 36 #define DTE_PPB_ADJ(ppb) (u32)(div64_u64((((u64)abs(ppb) * BIT(28)) +\ 37 62500000ULL), 125000000ULL)) 38 39 /* ptp dte priv structure */ 40 struct ptp_dte { 41 void __iomem *regs; 42 struct ptp_clock *ptp_clk; 43 struct ptp_clock_info caps; 44 struct device *dev; 45 u32 ts_ovf_last; 46 u32 ts_wrap_cnt; 47 spinlock_t lock; 48 u32 reg_val[DTE_NUM_REGS_TO_RESTORE]; 49 }; 50 51 static void dte_write_nco(void __iomem *regs, s64 ns) 52 { 53 u32 sum2, sum3; 54 55 sum2 = (u32)((ns >> DTE_NCO_SUM2_SHIFT) & DTE_NCO_SUM2_MASK); 56 /* compensate for ignoring sum1 */ 57 if (sum2 != DTE_NCO_SUM2_MASK) 58 sum2++; 59 60 /* to write sum3, bits [15:8] needs to be written */ 61 sum3 = (u32)(((ns >> DTE_NCO_SUM3_SHIFT) & DTE_NCO_SUM3_MASK) << 62 DTE_NCO_SUM3_WR_SHIFT); 63 64 writel(0, (regs + DTE_NCO_LOW_TIME_REG)); 65 writel(sum2, (regs + DTE_NCO_TIME_REG)); 66 writel(sum3, (regs + DTE_NCO_OVERFLOW_REG)); 67 } 68 69 static s64 dte_read_nco(void __iomem *regs) 70 { 71 u32 sum2, sum3; 72 s64 ns; 73 74 /* 75 * ignoring sum1 (4 bits) gives a 16ns resolution, which 76 * works due to the async register read. 77 */ 78 sum3 = readl(regs + DTE_NCO_OVERFLOW_REG) & DTE_NCO_SUM3_MASK; 79 sum2 = readl(regs + DTE_NCO_TIME_REG); 80 ns = ((s64)sum3 << DTE_NCO_SUM3_SHIFT) | 81 ((s64)sum2 << DTE_NCO_SUM2_SHIFT); 82 83 return ns; 84 } 85 86 static void dte_write_nco_delta(struct ptp_dte *ptp_dte, s64 delta) 87 { 88 s64 ns; 89 90 ns = dte_read_nco(ptp_dte->regs); 91 92 /* handle wraparound conditions */ 93 if ((delta < 0) && (abs(delta) > ns)) { 94 if (ptp_dte->ts_wrap_cnt) { 95 ns += DTE_NCO_MAX_NS + delta; 96 ptp_dte->ts_wrap_cnt--; 97 } else { 98 ns = 0; 99 } 100 } else { 101 ns += delta; 102 if (ns > DTE_NCO_MAX_NS) { 103 ptp_dte->ts_wrap_cnt++; 104 ns -= DTE_NCO_MAX_NS; 105 } 106 } 107 108 dte_write_nco(ptp_dte->regs, ns); 109 110 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & 111 DTE_NCO_TS_WRAP_MASK; 112 } 113 114 static s64 dte_read_nco_with_ovf(struct ptp_dte *ptp_dte) 115 { 116 u32 ts_ovf; 117 s64 ns = 0; 118 119 ns = dte_read_nco(ptp_dte->regs); 120 121 /*Timestamp overflow: 8 LSB bits of sum3, 4 MSB bits of sum2 */ 122 ts_ovf = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & DTE_NCO_TS_WRAP_MASK; 123 124 /* Check for wrap around */ 125 if (ts_ovf < ptp_dte->ts_ovf_last) 126 ptp_dte->ts_wrap_cnt++; 127 128 ptp_dte->ts_ovf_last = ts_ovf; 129 130 /* adjust for wraparounds */ 131 ns += (s64)(BIT_ULL(DTE_WRAP_AROUND_NSEC_SHIFT) * ptp_dte->ts_wrap_cnt); 132 133 return ns; 134 } 135 136 static int ptp_dte_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 137 { 138 s32 ppb = scaled_ppm_to_ppb(scaled_ppm); 139 u32 nco_incr; 140 unsigned long flags; 141 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 142 143 if (abs(ppb) > ptp_dte->caps.max_adj) { 144 dev_err(ptp_dte->dev, "ppb adj too big\n"); 145 return -EINVAL; 146 } 147 148 if (ppb < 0) 149 nco_incr = DTE_NCO_INC_DEFAULT - DTE_PPB_ADJ(ppb); 150 else 151 nco_incr = DTE_NCO_INC_DEFAULT + DTE_PPB_ADJ(ppb); 152 153 spin_lock_irqsave(&ptp_dte->lock, flags); 154 writel(nco_incr, ptp_dte->regs + DTE_NCO_INC_REG); 155 spin_unlock_irqrestore(&ptp_dte->lock, flags); 156 157 return 0; 158 } 159 160 static int ptp_dte_adjtime(struct ptp_clock_info *ptp, s64 delta) 161 { 162 unsigned long flags; 163 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 164 165 spin_lock_irqsave(&ptp_dte->lock, flags); 166 dte_write_nco_delta(ptp_dte, delta); 167 spin_unlock_irqrestore(&ptp_dte->lock, flags); 168 169 return 0; 170 } 171 172 static int ptp_dte_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 173 { 174 unsigned long flags; 175 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 176 177 spin_lock_irqsave(&ptp_dte->lock, flags); 178 *ts = ns_to_timespec64(dte_read_nco_with_ovf(ptp_dte)); 179 spin_unlock_irqrestore(&ptp_dte->lock, flags); 180 181 return 0; 182 } 183 184 static int ptp_dte_settime(struct ptp_clock_info *ptp, 185 const struct timespec64 *ts) 186 { 187 unsigned long flags; 188 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps); 189 190 spin_lock_irqsave(&ptp_dte->lock, flags); 191 192 /* Disable nco increment */ 193 writel(0, ptp_dte->regs + DTE_NCO_INC_REG); 194 195 dte_write_nco(ptp_dte->regs, timespec64_to_ns(ts)); 196 197 /* reset overflow and wrap counter */ 198 ptp_dte->ts_ovf_last = 0; 199 ptp_dte->ts_wrap_cnt = 0; 200 201 /* Enable nco increment */ 202 writel(DTE_NCO_INC_DEFAULT, ptp_dte->regs + DTE_NCO_INC_REG); 203 204 spin_unlock_irqrestore(&ptp_dte->lock, flags); 205 206 return 0; 207 } 208 209 static int ptp_dte_enable(struct ptp_clock_info *ptp, 210 struct ptp_clock_request *rq, int on) 211 { 212 return -EOPNOTSUPP; 213 } 214 215 static const struct ptp_clock_info ptp_dte_caps = { 216 .owner = THIS_MODULE, 217 .name = "DTE PTP timer", 218 .max_adj = 50000000, 219 .n_ext_ts = 0, 220 .n_pins = 0, 221 .pps = 0, 222 .adjfine = ptp_dte_adjfine, 223 .adjtime = ptp_dte_adjtime, 224 .gettime64 = ptp_dte_gettime, 225 .settime64 = ptp_dte_settime, 226 .enable = ptp_dte_enable, 227 }; 228 229 static int ptp_dte_probe(struct platform_device *pdev) 230 { 231 struct ptp_dte *ptp_dte; 232 struct device *dev = &pdev->dev; 233 234 ptp_dte = devm_kzalloc(dev, sizeof(struct ptp_dte), GFP_KERNEL); 235 if (!ptp_dte) 236 return -ENOMEM; 237 238 ptp_dte->regs = devm_platform_ioremap_resource(pdev, 0); 239 if (IS_ERR(ptp_dte->regs)) 240 return PTR_ERR(ptp_dte->regs); 241 242 spin_lock_init(&ptp_dte->lock); 243 244 ptp_dte->dev = dev; 245 ptp_dte->caps = ptp_dte_caps; 246 ptp_dte->ptp_clk = ptp_clock_register(&ptp_dte->caps, &pdev->dev); 247 if (IS_ERR(ptp_dte->ptp_clk)) { 248 dev_err(dev, 249 "%s: Failed to register ptp clock\n", __func__); 250 return PTR_ERR(ptp_dte->ptp_clk); 251 } 252 253 platform_set_drvdata(pdev, ptp_dte); 254 255 dev_info(dev, "ptp clk probe done\n"); 256 257 return 0; 258 } 259 260 static void ptp_dte_remove(struct platform_device *pdev) 261 { 262 struct ptp_dte *ptp_dte = platform_get_drvdata(pdev); 263 u8 i; 264 265 ptp_clock_unregister(ptp_dte->ptp_clk); 266 267 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) 268 writel(0, ptp_dte->regs + (i * sizeof(u32))); 269 } 270 271 #ifdef CONFIG_PM_SLEEP 272 static int ptp_dte_suspend(struct device *dev) 273 { 274 struct ptp_dte *ptp_dte = dev_get_drvdata(dev); 275 u8 i; 276 277 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) { 278 ptp_dte->reg_val[i] = 279 readl(ptp_dte->regs + (i * sizeof(u32))); 280 } 281 282 /* disable the nco */ 283 writel(0, ptp_dte->regs + DTE_NCO_INC_REG); 284 285 return 0; 286 } 287 288 static int ptp_dte_resume(struct device *dev) 289 { 290 struct ptp_dte *ptp_dte = dev_get_drvdata(dev); 291 u8 i; 292 293 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) { 294 if ((i * sizeof(u32)) != DTE_NCO_OVERFLOW_REG) 295 writel(ptp_dte->reg_val[i], 296 (ptp_dte->regs + (i * sizeof(u32)))); 297 else 298 writel(((ptp_dte->reg_val[i] & 299 DTE_NCO_SUM3_MASK) << DTE_NCO_SUM3_WR_SHIFT), 300 (ptp_dte->regs + (i * sizeof(u32)))); 301 } 302 303 return 0; 304 } 305 306 static const struct dev_pm_ops ptp_dte_pm_ops = { 307 .suspend = ptp_dte_suspend, 308 .resume = ptp_dte_resume 309 }; 310 311 #define PTP_DTE_PM_OPS (&ptp_dte_pm_ops) 312 #else 313 #define PTP_DTE_PM_OPS NULL 314 #endif 315 316 static const struct of_device_id ptp_dte_of_match[] = { 317 { .compatible = "brcm,ptp-dte", }, 318 {}, 319 }; 320 MODULE_DEVICE_TABLE(of, ptp_dte_of_match); 321 322 static struct platform_driver ptp_dte_driver = { 323 .driver = { 324 .name = "ptp-dte", 325 .pm = PTP_DTE_PM_OPS, 326 .of_match_table = ptp_dte_of_match, 327 }, 328 .probe = ptp_dte_probe, 329 .remove = ptp_dte_remove, 330 }; 331 module_platform_driver(ptp_dte_driver); 332 333 MODULE_AUTHOR("Broadcom"); 334 MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver"); 335 MODULE_LICENSE("GPL v2"); 336