1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Common code for Intel Running Average Power Limit (RAPL) support. 4 * Copyright (c) 2019, Intel Corporation. 5 */ 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/bitmap.h> 9 #include <linux/cleanup.h> 10 #include <linux/cpu.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/intel_rapl.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/log2.h> 17 #include <linux/module.h> 18 #include <linux/nospec.h> 19 #include <linux/perf_event.h> 20 #include <linux/platform_device.h> 21 #include <linux/powercap.h> 22 #include <linux/processor.h> 23 #include <linux/slab.h> 24 #include <linux/suspend.h> 25 #include <linux/sysfs.h> 26 #include <linux/types.h> 27 28 #include <asm/cpu_device_id.h> 29 #include <asm/intel-family.h> 30 #include <asm/iosf_mbi.h> 31 #include <asm/msr.h> 32 33 /* bitmasks for RAPL MSRs, used by primitive access functions */ 34 #define ENERGY_STATUS_MASK 0xffffffff 35 36 #define POWER_LIMIT1_MASK 0x7FFF 37 #define POWER_LIMIT1_ENABLE BIT(15) 38 #define POWER_LIMIT1_CLAMP BIT(16) 39 40 #define POWER_LIMIT2_MASK (0x7FFFULL<<32) 41 #define POWER_LIMIT2_ENABLE BIT_ULL(47) 42 #define POWER_LIMIT2_CLAMP BIT_ULL(48) 43 #define POWER_HIGH_LOCK BIT_ULL(63) 44 #define POWER_LOW_LOCK BIT(31) 45 46 #define POWER_LIMIT4_MASK 0x1FFF 47 48 #define TIME_WINDOW1_MASK (0x7FULL<<17) 49 #define TIME_WINDOW2_MASK (0x7FULL<<49) 50 51 #define POWER_UNIT_OFFSET 0 52 #define POWER_UNIT_MASK 0x0F 53 54 #define ENERGY_UNIT_OFFSET 0x08 55 #define ENERGY_UNIT_MASK 0x1F00 56 57 #define TIME_UNIT_OFFSET 0x10 58 #define TIME_UNIT_MASK 0xF0000 59 60 #define POWER_INFO_MAX_MASK (0x7fffULL<<32) 61 #define POWER_INFO_MIN_MASK (0x7fffULL<<16) 62 #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48) 63 #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff 64 65 #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff 66 #define PP_POLICY_MASK 0x1F 67 68 /* 69 * SPR has different layout for Psys Domain PowerLimit registers. 70 * There are 17 bits of PL1 and PL2 instead of 15 bits. 71 * The Enable bits and TimeWindow bits are also shifted as a result. 72 */ 73 #define PSYS_POWER_LIMIT1_MASK 0x1FFFF 74 #define PSYS_POWER_LIMIT1_ENABLE BIT(17) 75 76 #define PSYS_POWER_LIMIT2_MASK (0x1FFFFULL<<32) 77 #define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49) 78 79 #define PSYS_TIME_WINDOW1_MASK (0x7FULL<<19) 80 #define PSYS_TIME_WINDOW2_MASK (0x7FULL<<51) 81 82 /* bitmasks for RAPL TPMI, used by primitive access functions */ 83 #define TPMI_POWER_LIMIT_MASK 0x3FFFF 84 #define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62) 85 #define TPMI_TIME_WINDOW_MASK (0x7FULL<<18) 86 #define TPMI_INFO_SPEC_MASK 0x3FFFF 87 #define TPMI_INFO_MIN_MASK (0x3FFFFULL << 18) 88 #define TPMI_INFO_MAX_MASK (0x3FFFFULL << 36) 89 #define TPMI_INFO_MAX_TIME_WIN_MASK (0x7FULL << 54) 90 91 /* Non HW constants */ 92 #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */ 93 #define RAPL_PRIMITIVE_DUMMY BIT(2) 94 95 #define TIME_WINDOW_MAX_MSEC 40000 96 #define TIME_WINDOW_MIN_MSEC 250 97 #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */ 98 enum unit_type { 99 ARBITRARY_UNIT, /* no translation */ 100 POWER_UNIT, 101 ENERGY_UNIT, 102 TIME_UNIT, 103 }; 104 105 /* per domain data, some are optional */ 106 #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2) 107 108 #define DOMAIN_STATE_INACTIVE BIT(0) 109 #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1) 110 111 static const char *pl_names[NR_POWER_LIMITS] = { 112 [POWER_LIMIT1] = "long_term", 113 [POWER_LIMIT2] = "short_term", 114 [POWER_LIMIT4] = "peak_power", 115 }; 116 117 enum pl_prims { 118 PL_ENABLE, 119 PL_CLAMP, 120 PL_LIMIT, 121 PL_TIME_WINDOW, 122 PL_MAX_POWER, 123 PL_LOCK, 124 }; 125 126 static bool is_pl_valid(struct rapl_domain *rd, int pl) 127 { 128 if (pl < POWER_LIMIT1 || pl > POWER_LIMIT4) 129 return false; 130 return rd->rpl[pl].name ? true : false; 131 } 132 133 static int get_pl_lock_prim(struct rapl_domain *rd, int pl) 134 { 135 if (rd->rp->priv->type == RAPL_IF_TPMI) { 136 if (pl == POWER_LIMIT1) 137 return PL1_LOCK; 138 if (pl == POWER_LIMIT2) 139 return PL2_LOCK; 140 if (pl == POWER_LIMIT4) 141 return PL4_LOCK; 142 } 143 144 /* MSR/MMIO Interface doesn't have Lock bit for PL4 */ 145 if (pl == POWER_LIMIT4) 146 return -EINVAL; 147 148 /* 149 * Power Limit register that supports two power limits has a different 150 * bit position for the Lock bit. 151 */ 152 if (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2)) 153 return FW_HIGH_LOCK; 154 return FW_LOCK; 155 } 156 157 static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim) 158 { 159 switch (pl) { 160 case POWER_LIMIT1: 161 if (prim == PL_ENABLE) 162 return PL1_ENABLE; 163 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) 164 return PL1_CLAMP; 165 if (prim == PL_LIMIT) 166 return POWER_LIMIT1; 167 if (prim == PL_TIME_WINDOW) 168 return TIME_WINDOW1; 169 if (prim == PL_MAX_POWER) 170 return THERMAL_SPEC_POWER; 171 if (prim == PL_LOCK) 172 return get_pl_lock_prim(rd, pl); 173 return -EINVAL; 174 case POWER_LIMIT2: 175 if (prim == PL_ENABLE) 176 return PL2_ENABLE; 177 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) 178 return PL2_CLAMP; 179 if (prim == PL_LIMIT) 180 return POWER_LIMIT2; 181 if (prim == PL_TIME_WINDOW) 182 return TIME_WINDOW2; 183 if (prim == PL_MAX_POWER) 184 return MAX_POWER; 185 if (prim == PL_LOCK) 186 return get_pl_lock_prim(rd, pl); 187 return -EINVAL; 188 case POWER_LIMIT4: 189 if (prim == PL_LIMIT) 190 return POWER_LIMIT4; 191 if (prim == PL_ENABLE) 192 return PL4_ENABLE; 193 /* PL4 would be around two times PL2, use same prim as PL2. */ 194 if (prim == PL_MAX_POWER) 195 return MAX_POWER; 196 if (prim == PL_LOCK) 197 return get_pl_lock_prim(rd, pl); 198 return -EINVAL; 199 default: 200 return -EINVAL; 201 } 202 } 203 204 #define power_zone_to_rapl_domain(_zone) \ 205 container_of(_zone, struct rapl_domain, power_zone) 206 207 struct rapl_defaults { 208 u8 floor_freq_reg_addr; 209 int (*check_unit)(struct rapl_domain *rd); 210 void (*set_floor_freq)(struct rapl_domain *rd, bool mode); 211 u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, 212 bool to_raw); 213 unsigned int dram_domain_energy_unit; 214 unsigned int psys_domain_energy_unit; 215 bool spr_psys_bits; 216 }; 217 static struct rapl_defaults *defaults_msr; 218 static const struct rapl_defaults defaults_tpmi; 219 220 static struct rapl_defaults *get_defaults(struct rapl_package *rp) 221 { 222 return rp->priv->defaults; 223 } 224 225 /* Sideband MBI registers */ 226 #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2) 227 #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf) 228 229 #define PACKAGE_PLN_INT_SAVED BIT(0) 230 #define MAX_PRIM_NAME (32) 231 232 /* per domain data. used to describe individual knobs such that access function 233 * can be consolidated into one instead of many inline functions. 234 */ 235 struct rapl_primitive_info { 236 const char *name; 237 u64 mask; 238 int shift; 239 enum rapl_domain_reg_id id; 240 enum unit_type unit; 241 u32 flag; 242 }; 243 244 #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \ 245 .name = #p, \ 246 .mask = m, \ 247 .shift = s, \ 248 .id = i, \ 249 .unit = u, \ 250 .flag = f \ 251 } 252 253 static void rapl_init_domains(struct rapl_package *rp); 254 static int rapl_read_data_raw(struct rapl_domain *rd, 255 enum rapl_primitives prim, 256 bool xlate, u64 *data); 257 static int rapl_write_data_raw(struct rapl_domain *rd, 258 enum rapl_primitives prim, 259 unsigned long long value); 260 static int rapl_read_pl_data(struct rapl_domain *rd, int pl, 261 enum pl_prims pl_prim, 262 bool xlate, u64 *data); 263 static int rapl_write_pl_data(struct rapl_domain *rd, int pl, 264 enum pl_prims pl_prim, 265 unsigned long long value); 266 static u64 rapl_unit_xlate(struct rapl_domain *rd, 267 enum unit_type type, u64 value, int to_raw); 268 static void package_power_limit_irq_save(struct rapl_package *rp); 269 270 static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */ 271 272 static const char *const rapl_domain_names[] = { 273 "package", 274 "core", 275 "uncore", 276 "dram", 277 "psys", 278 }; 279 280 static int get_energy_counter(struct powercap_zone *power_zone, 281 u64 *energy_raw) 282 { 283 struct rapl_domain *rd; 284 u64 energy_now; 285 286 /* prevent CPU hotplug, make sure the RAPL domain does not go 287 * away while reading the counter. 288 */ 289 cpus_read_lock(); 290 rd = power_zone_to_rapl_domain(power_zone); 291 292 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) { 293 *energy_raw = energy_now; 294 cpus_read_unlock(); 295 296 return 0; 297 } 298 cpus_read_unlock(); 299 300 return -EIO; 301 } 302 303 static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy) 304 { 305 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev); 306 307 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0); 308 return 0; 309 } 310 311 static int release_zone(struct powercap_zone *power_zone) 312 { 313 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 314 struct rapl_package *rp = rd->rp; 315 316 /* package zone is the last zone of a package, we can free 317 * memory here since all children has been unregistered. 318 */ 319 if (rd->id == RAPL_DOMAIN_PACKAGE) { 320 kfree(rd); 321 rp->domains = NULL; 322 } 323 324 return 0; 325 326 } 327 328 static int find_nr_power_limit(struct rapl_domain *rd) 329 { 330 int i, nr_pl = 0; 331 332 for (i = 0; i < NR_POWER_LIMITS; i++) { 333 if (is_pl_valid(rd, i)) 334 nr_pl++; 335 } 336 337 return nr_pl; 338 } 339 340 static int set_domain_enable(struct powercap_zone *power_zone, bool mode) 341 { 342 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 343 struct rapl_defaults *defaults = get_defaults(rd->rp); 344 u64 val; 345 int ret; 346 347 cpus_read_lock(); 348 ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode); 349 if (ret) 350 goto end; 351 352 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, false, &val); 353 if (ret) 354 goto end; 355 356 if (mode != val) { 357 pr_debug("%s cannot be %s\n", power_zone->name, 358 str_enabled_disabled(mode)); 359 goto end; 360 } 361 362 if (defaults->set_floor_freq) 363 defaults->set_floor_freq(rd, mode); 364 365 end: 366 cpus_read_unlock(); 367 368 return ret; 369 } 370 371 static int get_domain_enable(struct powercap_zone *power_zone, bool *mode) 372 { 373 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone); 374 u64 val; 375 int ret; 376 377 if (rd->rpl[POWER_LIMIT1].locked) { 378 *mode = false; 379 return 0; 380 } 381 cpus_read_lock(); 382 ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, true, &val); 383 if (!ret) 384 *mode = val; 385 cpus_read_unlock(); 386 387 return ret; 388 } 389 390 /* per RAPL domain ops, in the order of rapl_domain_type */ 391 static const struct powercap_zone_ops zone_ops[] = { 392 /* RAPL_DOMAIN_PACKAGE */ 393 { 394 .get_energy_uj = get_energy_counter, 395 .get_max_energy_range_uj = get_max_energy_counter, 396 .release = release_zone, 397 .set_enable = set_domain_enable, 398 .get_enable = get_domain_enable, 399 }, 400 /* RAPL_DOMAIN_PP0 */ 401 { 402 .get_energy_uj = get_energy_counter, 403 .get_max_energy_range_uj = get_max_energy_counter, 404 .release = release_zone, 405 .set_enable = set_domain_enable, 406 .get_enable = get_domain_enable, 407 }, 408 /* RAPL_DOMAIN_PP1 */ 409 { 410 .get_energy_uj = get_energy_counter, 411 .get_max_energy_range_uj = get_max_energy_counter, 412 .release = release_zone, 413 .set_enable = set_domain_enable, 414 .get_enable = get_domain_enable, 415 }, 416 /* RAPL_DOMAIN_DRAM */ 417 { 418 .get_energy_uj = get_energy_counter, 419 .get_max_energy_range_uj = get_max_energy_counter, 420 .release = release_zone, 421 .set_enable = set_domain_enable, 422 .get_enable = get_domain_enable, 423 }, 424 /* RAPL_DOMAIN_PLATFORM */ 425 { 426 .get_energy_uj = get_energy_counter, 427 .get_max_energy_range_uj = get_max_energy_counter, 428 .release = release_zone, 429 .set_enable = set_domain_enable, 430 .get_enable = get_domain_enable, 431 }, 432 }; 433 434 /* 435 * Constraint index used by powercap can be different than power limit (PL) 436 * index in that some PLs maybe missing due to non-existent MSRs. So we 437 * need to convert here by finding the valid PLs only (name populated). 438 */ 439 static int contraint_to_pl(struct rapl_domain *rd, int cid) 440 { 441 int i, j; 442 443 for (i = POWER_LIMIT1, j = 0; i < NR_POWER_LIMITS; i++) { 444 if (is_pl_valid(rd, i) && j++ == cid) { 445 pr_debug("%s: index %d\n", __func__, i); 446 return i; 447 } 448 } 449 pr_err("Cannot find matching power limit for constraint %d\n", cid); 450 451 return -EINVAL; 452 } 453 454 static int set_power_limit(struct powercap_zone *power_zone, int cid, 455 u64 power_limit) 456 { 457 struct rapl_domain *rd; 458 struct rapl_package *rp; 459 int ret = 0; 460 int id; 461 462 cpus_read_lock(); 463 rd = power_zone_to_rapl_domain(power_zone); 464 id = contraint_to_pl(rd, cid); 465 rp = rd->rp; 466 467 ret = rapl_write_pl_data(rd, id, PL_LIMIT, power_limit); 468 if (!ret) 469 package_power_limit_irq_save(rp); 470 cpus_read_unlock(); 471 return ret; 472 } 473 474 static int get_current_power_limit(struct powercap_zone *power_zone, int cid, 475 u64 *data) 476 { 477 struct rapl_domain *rd; 478 u64 val; 479 int ret = 0; 480 int id; 481 482 cpus_read_lock(); 483 rd = power_zone_to_rapl_domain(power_zone); 484 id = contraint_to_pl(rd, cid); 485 486 ret = rapl_read_pl_data(rd, id, PL_LIMIT, true, &val); 487 if (!ret) 488 *data = val; 489 490 cpus_read_unlock(); 491 492 return ret; 493 } 494 495 static int set_time_window(struct powercap_zone *power_zone, int cid, 496 u64 window) 497 { 498 struct rapl_domain *rd; 499 int ret = 0; 500 int id; 501 502 cpus_read_lock(); 503 rd = power_zone_to_rapl_domain(power_zone); 504 id = contraint_to_pl(rd, cid); 505 506 ret = rapl_write_pl_data(rd, id, PL_TIME_WINDOW, window); 507 508 cpus_read_unlock(); 509 return ret; 510 } 511 512 static int get_time_window(struct powercap_zone *power_zone, int cid, 513 u64 *data) 514 { 515 struct rapl_domain *rd; 516 u64 val; 517 int ret = 0; 518 int id; 519 520 cpus_read_lock(); 521 rd = power_zone_to_rapl_domain(power_zone); 522 id = contraint_to_pl(rd, cid); 523 524 ret = rapl_read_pl_data(rd, id, PL_TIME_WINDOW, true, &val); 525 if (!ret) 526 *data = val; 527 528 cpus_read_unlock(); 529 530 return ret; 531 } 532 533 static const char *get_constraint_name(struct powercap_zone *power_zone, 534 int cid) 535 { 536 struct rapl_domain *rd; 537 int id; 538 539 rd = power_zone_to_rapl_domain(power_zone); 540 id = contraint_to_pl(rd, cid); 541 if (id >= 0) 542 return rd->rpl[id].name; 543 544 return NULL; 545 } 546 547 static int get_max_power(struct powercap_zone *power_zone, int cid, u64 *data) 548 { 549 struct rapl_domain *rd; 550 u64 val; 551 int ret = 0; 552 int id; 553 554 cpus_read_lock(); 555 rd = power_zone_to_rapl_domain(power_zone); 556 id = contraint_to_pl(rd, cid); 557 558 ret = rapl_read_pl_data(rd, id, PL_MAX_POWER, true, &val); 559 if (!ret) 560 *data = val; 561 562 /* As a generalization rule, PL4 would be around two times PL2. */ 563 if (id == POWER_LIMIT4) 564 *data = *data * 2; 565 566 cpus_read_unlock(); 567 568 return ret; 569 } 570 571 static const struct powercap_zone_constraint_ops constraint_ops = { 572 .set_power_limit_uw = set_power_limit, 573 .get_power_limit_uw = get_current_power_limit, 574 .set_time_window_us = set_time_window, 575 .get_time_window_us = get_time_window, 576 .get_max_power_uw = get_max_power, 577 .get_name = get_constraint_name, 578 }; 579 580 /* Return the id used for read_raw/write_raw callback */ 581 static int get_rid(struct rapl_package *rp) 582 { 583 return rp->lead_cpu >= 0 ? rp->lead_cpu : rp->id; 584 } 585 586 /* called after domain detection and package level data are set */ 587 static void rapl_init_domains(struct rapl_package *rp) 588 { 589 enum rapl_domain_type i; 590 enum rapl_domain_reg_id j; 591 struct rapl_domain *rd = rp->domains; 592 593 for (i = 0; i < RAPL_DOMAIN_MAX; i++) { 594 unsigned int mask = rp->domain_map & (1 << i); 595 int t; 596 597 if (!mask) 598 continue; 599 600 rd->rp = rp; 601 602 if (i == RAPL_DOMAIN_PLATFORM && rp->id > 0) { 603 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "psys-%d", 604 rp->lead_cpu >= 0 ? topology_physical_package_id(rp->lead_cpu) : 605 rp->id); 606 } else { 607 snprintf(rd->name, RAPL_DOMAIN_NAME_LENGTH, "%s", 608 rapl_domain_names[i]); 609 } 610 611 rd->id = i; 612 613 /* PL1 is supported by default */ 614 rp->priv->limits[i] |= BIT(POWER_LIMIT1); 615 616 for (t = POWER_LIMIT1; t < NR_POWER_LIMITS; t++) { 617 if (rp->priv->limits[i] & BIT(t)) 618 rd->rpl[t].name = pl_names[t]; 619 } 620 621 for (j = 0; j < RAPL_DOMAIN_REG_MAX; j++) 622 rd->regs[j] = rp->priv->regs[i][j]; 623 624 rd++; 625 } 626 } 627 628 static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type, 629 u64 value, int to_raw) 630 { 631 u64 units = 1; 632 struct rapl_defaults *defaults = get_defaults(rd->rp); 633 u64 scale = 1; 634 635 switch (type) { 636 case POWER_UNIT: 637 units = rd->power_unit; 638 break; 639 case ENERGY_UNIT: 640 scale = ENERGY_UNIT_SCALE; 641 units = rd->energy_unit; 642 break; 643 case TIME_UNIT: 644 return defaults->compute_time_window(rd, value, to_raw); 645 case ARBITRARY_UNIT: 646 default: 647 return value; 648 } 649 650 if (to_raw) 651 return div64_u64(value, units) * scale; 652 653 value *= units; 654 655 return div64_u64(value, scale); 656 } 657 658 /* RAPL primitives for MSR and MMIO I/F */ 659 static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = { 660 /* name, mask, shift, msr index, unit divisor */ 661 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0, 662 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 663 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32, 664 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 665 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0, 666 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 667 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 668 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 669 [FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31, 670 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 671 [FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63, 672 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 673 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15, 674 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 675 [PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16, 676 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 677 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47, 678 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 679 [PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48, 680 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 681 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17, 682 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 683 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49, 684 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 685 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK, 686 0, RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 687 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32, 688 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 689 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16, 690 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 691 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48, 692 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 693 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 694 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 695 [PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0, 696 RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0), 697 [PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0, 698 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 699 [PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK, 32, 700 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 701 [PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE, 17, 702 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 703 [PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE, 49, 704 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 705 [PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK, 19, 706 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 707 [PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK, 51, 708 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 709 /* non-hardware */ 710 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT, 711 RAPL_PRIMITIVE_DERIVED), 712 }; 713 714 /* RAPL primitives for TPMI I/F */ 715 static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = { 716 /* name, mask, shift, msr index, unit divisor */ 717 [POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0, 718 RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0), 719 [POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0, 720 RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0), 721 [POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0, 722 RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0), 723 [ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0, 724 RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0), 725 [PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, POWER_HIGH_LOCK, 63, 726 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 727 [PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, POWER_HIGH_LOCK, 63, 728 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 729 [PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, POWER_HIGH_LOCK, 63, 730 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 731 [PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 732 RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0), 733 [PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 734 RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0), 735 [PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62, 736 RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0), 737 [TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18, 738 RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0), 739 [TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18, 740 RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0), 741 [THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0, 742 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 743 [MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36, 744 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 745 [MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18, 746 RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0), 747 [MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK, 54, 748 RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0), 749 [THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0, 750 RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0), 751 /* non-hardware */ 752 [AVERAGE_POWER] = PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, 753 POWER_UNIT, RAPL_PRIMITIVE_DERIVED), 754 }; 755 756 static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim) 757 { 758 struct rapl_primitive_info *rpi = rp->priv->rpi; 759 760 if (prim < 0 || prim >= NR_RAPL_PRIMITIVES || !rpi) 761 return NULL; 762 763 return &rpi[prim]; 764 } 765 766 static int rapl_config(struct rapl_package *rp) 767 { 768 switch (rp->priv->type) { 769 /* MMIO I/F shares the same register layout as MSR registers */ 770 case RAPL_IF_MMIO: 771 case RAPL_IF_MSR: 772 rp->priv->defaults = (void *)defaults_msr; 773 rp->priv->rpi = (void *)rpi_msr; 774 break; 775 case RAPL_IF_TPMI: 776 rp->priv->defaults = (void *)&defaults_tpmi; 777 rp->priv->rpi = (void *)rpi_tpmi; 778 break; 779 default: 780 return -EINVAL; 781 } 782 783 /* defaults_msr can be NULL on unsupported platforms */ 784 if (!rp->priv->defaults || !rp->priv->rpi) 785 return -ENODEV; 786 787 return 0; 788 } 789 790 static enum rapl_primitives 791 prim_fixups(struct rapl_domain *rd, enum rapl_primitives prim) 792 { 793 struct rapl_defaults *defaults = get_defaults(rd->rp); 794 795 if (!defaults->spr_psys_bits) 796 return prim; 797 798 if (rd->id != RAPL_DOMAIN_PLATFORM) 799 return prim; 800 801 switch (prim) { 802 case POWER_LIMIT1: 803 return PSYS_POWER_LIMIT1; 804 case POWER_LIMIT2: 805 return PSYS_POWER_LIMIT2; 806 case PL1_ENABLE: 807 return PSYS_PL1_ENABLE; 808 case PL2_ENABLE: 809 return PSYS_PL2_ENABLE; 810 case TIME_WINDOW1: 811 return PSYS_TIME_WINDOW1; 812 case TIME_WINDOW2: 813 return PSYS_TIME_WINDOW2; 814 default: 815 return prim; 816 } 817 } 818 819 /* Read primitive data based on its related struct rapl_primitive_info. 820 * if xlate flag is set, return translated data based on data units, i.e. 821 * time, energy, and power. 822 * RAPL MSRs are non-architectual and are laid out not consistently across 823 * domains. Here we use primitive info to allow writing consolidated access 824 * functions. 825 * For a given primitive, it is processed by MSR mask and shift. Unit conversion 826 * is pre-assigned based on RAPL unit MSRs read at init time. 827 * 63-------------------------- 31--------------------------- 0 828 * | xxxxx (mask) | 829 * | |<- shift ----------------| 830 * 63-------------------------- 31--------------------------- 0 831 */ 832 static int rapl_read_data_raw(struct rapl_domain *rd, 833 enum rapl_primitives prim, bool xlate, u64 *data) 834 { 835 u64 value; 836 enum rapl_primitives prim_fixed = prim_fixups(rd, prim); 837 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed); 838 struct reg_action ra; 839 840 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY) 841 return -EINVAL; 842 843 ra.reg = rd->regs[rpi->id]; 844 if (!ra.reg.val) 845 return -EINVAL; 846 847 /* non-hardware data are collected by the polling thread */ 848 if (rpi->flag & RAPL_PRIMITIVE_DERIVED) { 849 *data = rd->rdd.primitives[prim]; 850 return 0; 851 } 852 853 ra.mask = rpi->mask; 854 855 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 856 pr_debug("failed to read reg 0x%llx for %s:%s\n", ra.reg.val, rd->rp->name, rd->name); 857 return -EIO; 858 } 859 860 value = ra.value >> rpi->shift; 861 862 if (xlate) 863 *data = rapl_unit_xlate(rd, rpi->unit, value, 0); 864 else 865 *data = value; 866 867 return 0; 868 } 869 870 /* Similar use of primitive info in the read counterpart */ 871 static int rapl_write_data_raw(struct rapl_domain *rd, 872 enum rapl_primitives prim, 873 unsigned long long value) 874 { 875 enum rapl_primitives prim_fixed = prim_fixups(rd, prim); 876 struct rapl_primitive_info *rpi = get_rpi(rd->rp, prim_fixed); 877 u64 bits; 878 struct reg_action ra; 879 int ret; 880 881 if (!rpi || !rpi->name || rpi->flag & RAPL_PRIMITIVE_DUMMY) 882 return -EINVAL; 883 884 bits = rapl_unit_xlate(rd, rpi->unit, value, 1); 885 bits <<= rpi->shift; 886 bits &= rpi->mask; 887 888 memset(&ra, 0, sizeof(ra)); 889 890 ra.reg = rd->regs[rpi->id]; 891 ra.mask = rpi->mask; 892 ra.value = bits; 893 894 ret = rd->rp->priv->write_raw(get_rid(rd->rp), &ra); 895 896 return ret; 897 } 898 899 static int rapl_read_pl_data(struct rapl_domain *rd, int pl, 900 enum pl_prims pl_prim, bool xlate, u64 *data) 901 { 902 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim); 903 904 if (!is_pl_valid(rd, pl)) 905 return -EINVAL; 906 907 return rapl_read_data_raw(rd, prim, xlate, data); 908 } 909 910 static int rapl_write_pl_data(struct rapl_domain *rd, int pl, 911 enum pl_prims pl_prim, 912 unsigned long long value) 913 { 914 enum rapl_primitives prim = get_pl_prim(rd, pl, pl_prim); 915 916 if (!is_pl_valid(rd, pl)) 917 return -EINVAL; 918 919 if (rd->rpl[pl].locked) { 920 pr_debug("%s:%s:%s locked by BIOS\n", rd->rp->name, rd->name, pl_names[pl]); 921 return -EACCES; 922 } 923 924 return rapl_write_data_raw(rd, prim, value); 925 } 926 /* 927 * Raw RAPL data stored in MSRs are in certain scales. We need to 928 * convert them into standard units based on the units reported in 929 * the RAPL unit MSRs. This is specific to CPUs as the method to 930 * calculate units differ on different CPUs. 931 * We convert the units to below format based on CPUs. 932 * i.e. 933 * energy unit: picoJoules : Represented in picoJoules by default 934 * power unit : microWatts : Represented in milliWatts by default 935 * time unit : microseconds: Represented in seconds by default 936 */ 937 static int rapl_check_unit_core(struct rapl_domain *rd) 938 { 939 struct reg_action ra; 940 u32 value; 941 942 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 943 ra.mask = ~0; 944 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 945 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 946 ra.reg.val, rd->rp->name, rd->name); 947 return -ENODEV; 948 } 949 950 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 951 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 952 953 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 954 rd->power_unit = 1000000 / (1 << value); 955 956 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 957 rd->time_unit = 1000000 / (1 << value); 958 959 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 960 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 961 962 return 0; 963 } 964 965 static int rapl_check_unit_atom(struct rapl_domain *rd) 966 { 967 struct reg_action ra; 968 u32 value; 969 970 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 971 ra.mask = ~0; 972 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 973 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 974 ra.reg.val, rd->rp->name, rd->name); 975 return -ENODEV; 976 } 977 978 value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; 979 rd->energy_unit = ENERGY_UNIT_SCALE * 1 << value; 980 981 value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; 982 rd->power_unit = (1 << value) * 1000; 983 984 value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; 985 rd->time_unit = 1000000 / (1 << value); 986 987 pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n", 988 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 989 990 return 0; 991 } 992 993 static void power_limit_irq_save_cpu(void *info) 994 { 995 u32 l, h = 0; 996 struct rapl_package *rp = (struct rapl_package *)info; 997 998 /* save the state of PLN irq mask bit before disabling it */ 999 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); 1000 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) { 1001 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE; 1002 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED; 1003 } 1004 l &= ~PACKAGE_THERM_INT_PLN_ENABLE; 1005 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 1006 } 1007 1008 /* REVISIT: 1009 * When package power limit is set artificially low by RAPL, LVT 1010 * thermal interrupt for package power limit should be ignored 1011 * since we are not really exceeding the real limit. The intention 1012 * is to avoid excessive interrupts while we are trying to save power. 1013 * A useful feature might be routing the package_power_limit interrupt 1014 * to userspace via eventfd. once we have a usecase, this is simple 1015 * to do by adding an atomic notifier. 1016 */ 1017 1018 static void package_power_limit_irq_save(struct rapl_package *rp) 1019 { 1020 if (rp->lead_cpu < 0) 1021 return; 1022 1023 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) 1024 return; 1025 1026 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1); 1027 } 1028 1029 /* 1030 * Restore per package power limit interrupt enable state. Called from cpu 1031 * hotplug code on package removal. 1032 */ 1033 static void package_power_limit_irq_restore(struct rapl_package *rp) 1034 { 1035 u32 l, h; 1036 1037 if (rp->lead_cpu < 0) 1038 return; 1039 1040 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN)) 1041 return; 1042 1043 /* irq enable state not saved, nothing to restore */ 1044 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) 1045 return; 1046 1047 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h); 1048 1049 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE) 1050 l |= PACKAGE_THERM_INT_PLN_ENABLE; 1051 else 1052 l &= ~PACKAGE_THERM_INT_PLN_ENABLE; 1053 1054 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 1055 } 1056 1057 static void set_floor_freq_default(struct rapl_domain *rd, bool mode) 1058 { 1059 int i; 1060 1061 /* always enable clamp such that p-state can go below OS requested 1062 * range. power capping priority over guranteed frequency. 1063 */ 1064 rapl_write_pl_data(rd, POWER_LIMIT1, PL_CLAMP, mode); 1065 1066 for (i = POWER_LIMIT2; i < NR_POWER_LIMITS; i++) { 1067 rapl_write_pl_data(rd, i, PL_ENABLE, mode); 1068 rapl_write_pl_data(rd, i, PL_CLAMP, mode); 1069 } 1070 } 1071 1072 static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) 1073 { 1074 static u32 power_ctrl_orig_val; 1075 struct rapl_defaults *defaults = get_defaults(rd->rp); 1076 u32 mdata; 1077 1078 if (!defaults->floor_freq_reg_addr) { 1079 pr_err("Invalid floor frequency config register\n"); 1080 return; 1081 } 1082 1083 if (!power_ctrl_orig_val) 1084 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, 1085 defaults->floor_freq_reg_addr, 1086 &power_ctrl_orig_val); 1087 mdata = power_ctrl_orig_val; 1088 if (enable) { 1089 mdata &= ~(0x7f << 8); 1090 mdata |= 1 << 8; 1091 } 1092 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, 1093 defaults->floor_freq_reg_addr, mdata); 1094 } 1095 1096 static u64 rapl_compute_time_window_core(struct rapl_domain *rd, u64 value, 1097 bool to_raw) 1098 { 1099 u64 f, y; /* fraction and exp. used for time unit */ 1100 1101 /* 1102 * Special processing based on 2^Y*(1+F/4), refer 1103 * to Intel Software Developer's manual Vol.3B: CH 14.9.3. 1104 */ 1105 if (!to_raw) { 1106 f = (value & 0x60) >> 5; 1107 y = value & 0x1f; 1108 value = (1 << y) * (4 + f) * rd->time_unit / 4; 1109 } else { 1110 if (value < rd->time_unit) 1111 return 0; 1112 1113 do_div(value, rd->time_unit); 1114 y = ilog2(value); 1115 1116 /* 1117 * The target hardware field is 7 bits wide, so return all ones 1118 * if the exponent is too large. 1119 */ 1120 if (y > 0x1f) 1121 return 0x7f; 1122 1123 f = div64_u64(4 * (value - (1ULL << y)), 1ULL << y); 1124 value = (y & 0x1f) | ((f & 0x3) << 5); 1125 } 1126 return value; 1127 } 1128 1129 static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, 1130 bool to_raw) 1131 { 1132 /* 1133 * Atom time unit encoding is straight forward val * time_unit, 1134 * where time_unit is default to 1 sec. Never 0. 1135 */ 1136 if (!to_raw) 1137 return (value) ? value * rd->time_unit : rd->time_unit; 1138 1139 value = div64_u64(value, rd->time_unit); 1140 1141 return value; 1142 } 1143 1144 /* TPMI Unit register has different layout */ 1145 #define TPMI_POWER_UNIT_OFFSET POWER_UNIT_OFFSET 1146 #define TPMI_POWER_UNIT_MASK POWER_UNIT_MASK 1147 #define TPMI_ENERGY_UNIT_OFFSET 0x06 1148 #define TPMI_ENERGY_UNIT_MASK 0x7C0 1149 #define TPMI_TIME_UNIT_OFFSET 0x0C 1150 #define TPMI_TIME_UNIT_MASK 0xF000 1151 1152 static int rapl_check_unit_tpmi(struct rapl_domain *rd) 1153 { 1154 struct reg_action ra; 1155 u32 value; 1156 1157 ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; 1158 ra.mask = ~0; 1159 if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra)) { 1160 pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", 1161 ra.reg.val, rd->rp->name, rd->name); 1162 return -ENODEV; 1163 } 1164 1165 value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET; 1166 rd->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value); 1167 1168 value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET; 1169 rd->power_unit = 1000000 / (1 << value); 1170 1171 value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET; 1172 rd->time_unit = 1000000 / (1 << value); 1173 1174 pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n", 1175 rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); 1176 1177 return 0; 1178 } 1179 1180 static const struct rapl_defaults defaults_tpmi = { 1181 .check_unit = rapl_check_unit_tpmi, 1182 /* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */ 1183 .set_floor_freq = set_floor_freq_default, 1184 .compute_time_window = rapl_compute_time_window_core, 1185 }; 1186 1187 static const struct rapl_defaults rapl_defaults_core = { 1188 .floor_freq_reg_addr = 0, 1189 .check_unit = rapl_check_unit_core, 1190 .set_floor_freq = set_floor_freq_default, 1191 .compute_time_window = rapl_compute_time_window_core, 1192 }; 1193 1194 static const struct rapl_defaults rapl_defaults_hsw_server = { 1195 .check_unit = rapl_check_unit_core, 1196 .set_floor_freq = set_floor_freq_default, 1197 .compute_time_window = rapl_compute_time_window_core, 1198 .dram_domain_energy_unit = 15300, 1199 }; 1200 1201 static const struct rapl_defaults rapl_defaults_spr_server = { 1202 .check_unit = rapl_check_unit_core, 1203 .set_floor_freq = set_floor_freq_default, 1204 .compute_time_window = rapl_compute_time_window_core, 1205 .psys_domain_energy_unit = 1000000000, 1206 .spr_psys_bits = true, 1207 }; 1208 1209 static const struct rapl_defaults rapl_defaults_byt = { 1210 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, 1211 .check_unit = rapl_check_unit_atom, 1212 .set_floor_freq = set_floor_freq_atom, 1213 .compute_time_window = rapl_compute_time_window_atom, 1214 }; 1215 1216 static const struct rapl_defaults rapl_defaults_tng = { 1217 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, 1218 .check_unit = rapl_check_unit_atom, 1219 .set_floor_freq = set_floor_freq_atom, 1220 .compute_time_window = rapl_compute_time_window_atom, 1221 }; 1222 1223 static const struct rapl_defaults rapl_defaults_ann = { 1224 .floor_freq_reg_addr = 0, 1225 .check_unit = rapl_check_unit_atom, 1226 .set_floor_freq = NULL, 1227 .compute_time_window = rapl_compute_time_window_atom, 1228 }; 1229 1230 static const struct rapl_defaults rapl_defaults_cht = { 1231 .floor_freq_reg_addr = 0, 1232 .check_unit = rapl_check_unit_atom, 1233 .set_floor_freq = NULL, 1234 .compute_time_window = rapl_compute_time_window_atom, 1235 }; 1236 1237 static const struct rapl_defaults rapl_defaults_amd = { 1238 .check_unit = rapl_check_unit_core, 1239 }; 1240 1241 static const struct x86_cpu_id rapl_ids[] __initconst = { 1242 X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), 1243 X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), 1244 1245 X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), 1246 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), 1247 1248 X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), 1249 X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), 1250 X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), 1251 X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), 1252 1253 X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), 1254 X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), 1255 X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), 1256 X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), 1257 1258 X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), 1259 X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), 1260 X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), 1261 X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), 1262 X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), 1263 X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), 1264 X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), 1265 X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), 1266 X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), 1267 X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), 1268 X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), 1269 X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), 1270 X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), 1271 X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), 1272 X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), 1273 X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), 1274 X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), 1275 X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), 1276 X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), 1277 X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), 1278 X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), 1279 X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), 1280 X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), 1281 X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), 1282 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), 1283 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), 1284 X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), 1285 X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), 1286 X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), 1287 X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), 1288 X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), 1289 X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), 1290 1291 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), 1292 X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), 1293 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), 1294 X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2,&rapl_defaults_ann), 1295 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), 1296 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), 1297 X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), 1298 X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), 1299 X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), 1300 X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), 1301 1302 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), 1303 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), 1304 1305 X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), 1306 X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), 1307 X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), 1308 X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), 1309 {} 1310 }; 1311 MODULE_DEVICE_TABLE(x86cpu, rapl_ids); 1312 1313 /* Read once for all raw primitive data for domains */ 1314 static void rapl_update_domain_data(struct rapl_package *rp) 1315 { 1316 int dmn, prim; 1317 u64 val; 1318 1319 for (dmn = 0; dmn < rp->nr_domains; dmn++) { 1320 pr_debug("update %s domain %s data\n", rp->name, 1321 rp->domains[dmn].name); 1322 /* exclude non-raw primitives */ 1323 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++) { 1324 struct rapl_primitive_info *rpi = get_rpi(rp, prim); 1325 1326 if (!rapl_read_data_raw(&rp->domains[dmn], prim, 1327 rpi->unit, &val)) 1328 rp->domains[dmn].rdd.primitives[prim] = val; 1329 } 1330 } 1331 1332 } 1333 1334 static int rapl_package_register_powercap(struct rapl_package *rp) 1335 { 1336 struct rapl_domain *rd; 1337 struct powercap_zone *power_zone = NULL; 1338 int nr_pl, ret; 1339 1340 /* Update the domain data of the new package */ 1341 rapl_update_domain_data(rp); 1342 1343 /* first we register package domain as the parent zone */ 1344 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1345 if (rd->id == RAPL_DOMAIN_PACKAGE) { 1346 nr_pl = find_nr_power_limit(rd); 1347 pr_debug("register package domain %s\n", rp->name); 1348 power_zone = powercap_register_zone(&rd->power_zone, 1349 rp->priv->control_type, rp->name, 1350 NULL, &zone_ops[rd->id], nr_pl, 1351 &constraint_ops); 1352 if (IS_ERR(power_zone)) { 1353 pr_debug("failed to register power zone %s\n", 1354 rp->name); 1355 return PTR_ERR(power_zone); 1356 } 1357 /* track parent zone in per package/socket data */ 1358 rp->power_zone = power_zone; 1359 /* done, only one package domain per socket */ 1360 break; 1361 } 1362 } 1363 if (!power_zone) { 1364 pr_err("no package domain found, unknown topology!\n"); 1365 return -ENODEV; 1366 } 1367 /* now register domains as children of the socket/package */ 1368 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1369 struct powercap_zone *parent = rp->power_zone; 1370 1371 if (rd->id == RAPL_DOMAIN_PACKAGE) 1372 continue; 1373 if (rd->id == RAPL_DOMAIN_PLATFORM) 1374 parent = NULL; 1375 /* number of power limits per domain varies */ 1376 nr_pl = find_nr_power_limit(rd); 1377 power_zone = powercap_register_zone(&rd->power_zone, 1378 rp->priv->control_type, 1379 rd->name, parent, 1380 &zone_ops[rd->id], nr_pl, 1381 &constraint_ops); 1382 1383 if (IS_ERR(power_zone)) { 1384 pr_debug("failed to register power_zone, %s:%s\n", 1385 rp->name, rd->name); 1386 ret = PTR_ERR(power_zone); 1387 goto err_cleanup; 1388 } 1389 } 1390 return 0; 1391 1392 err_cleanup: 1393 /* 1394 * Clean up previously initialized domains within the package if we 1395 * failed after the first domain setup. 1396 */ 1397 while (--rd >= rp->domains) { 1398 pr_debug("unregister %s domain %s\n", rp->name, rd->name); 1399 powercap_unregister_zone(rp->priv->control_type, 1400 &rd->power_zone); 1401 } 1402 1403 return ret; 1404 } 1405 1406 static int rapl_check_domain(int domain, struct rapl_package *rp) 1407 { 1408 struct reg_action ra; 1409 1410 switch (domain) { 1411 case RAPL_DOMAIN_PACKAGE: 1412 case RAPL_DOMAIN_PP0: 1413 case RAPL_DOMAIN_PP1: 1414 case RAPL_DOMAIN_DRAM: 1415 case RAPL_DOMAIN_PLATFORM: 1416 ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS]; 1417 break; 1418 default: 1419 pr_err("invalid domain id %d\n", domain); 1420 return -EINVAL; 1421 } 1422 /* make sure domain counters are available and contains non-zero 1423 * values, otherwise skip it. 1424 */ 1425 1426 ra.mask = ENERGY_STATUS_MASK; 1427 if (rp->priv->read_raw(get_rid(rp), &ra) || !ra.value) 1428 return -ENODEV; 1429 1430 return 0; 1431 } 1432 1433 /* 1434 * Get per domain energy/power/time unit. 1435 * RAPL Interfaces without per domain unit register will use the package 1436 * scope unit register to set per domain units. 1437 */ 1438 static int rapl_get_domain_unit(struct rapl_domain *rd) 1439 { 1440 struct rapl_defaults *defaults = get_defaults(rd->rp); 1441 int ret; 1442 1443 if (!rd->regs[RAPL_DOMAIN_REG_UNIT].val) { 1444 if (!rd->rp->priv->reg_unit.val) { 1445 pr_err("No valid Unit register found\n"); 1446 return -ENODEV; 1447 } 1448 rd->regs[RAPL_DOMAIN_REG_UNIT] = rd->rp->priv->reg_unit; 1449 } 1450 1451 if (!defaults->check_unit) { 1452 pr_err("missing .check_unit() callback\n"); 1453 return -ENODEV; 1454 } 1455 1456 ret = defaults->check_unit(rd); 1457 if (ret) 1458 return ret; 1459 1460 if (rd->id == RAPL_DOMAIN_DRAM && defaults->dram_domain_energy_unit) 1461 rd->energy_unit = defaults->dram_domain_energy_unit; 1462 if (rd->id == RAPL_DOMAIN_PLATFORM && defaults->psys_domain_energy_unit) 1463 rd->energy_unit = defaults->psys_domain_energy_unit; 1464 return 0; 1465 } 1466 1467 /* 1468 * Check if power limits are available. Two cases when they are not available: 1469 * 1. Locked by BIOS, in this case we still provide read-only access so that 1470 * users can see what limit is set by the BIOS. 1471 * 2. Some CPUs make some domains monitoring only which means PLx MSRs may not 1472 * exist at all. In this case, we do not show the constraints in powercap. 1473 * 1474 * Called after domains are detected and initialized. 1475 */ 1476 static void rapl_detect_powerlimit(struct rapl_domain *rd) 1477 { 1478 u64 val64; 1479 int i; 1480 1481 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 1482 if (!rapl_read_pl_data(rd, i, PL_LOCK, false, &val64)) { 1483 if (val64) { 1484 rd->rpl[i].locked = true; 1485 pr_info("%s:%s:%s locked by BIOS\n", 1486 rd->rp->name, rd->name, pl_names[i]); 1487 } 1488 } 1489 1490 if (rapl_read_pl_data(rd, i, PL_LIMIT, false, &val64)) 1491 rd->rpl[i].name = NULL; 1492 } 1493 } 1494 1495 /* Detect active and valid domains for the given CPU, caller must 1496 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled. 1497 */ 1498 static int rapl_detect_domains(struct rapl_package *rp) 1499 { 1500 struct rapl_domain *rd; 1501 int i; 1502 1503 for (i = 0; i < RAPL_DOMAIN_MAX; i++) { 1504 /* use physical package id to read counters */ 1505 if (!rapl_check_domain(i, rp)) { 1506 rp->domain_map |= 1 << i; 1507 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]); 1508 } 1509 } 1510 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX); 1511 if (!rp->nr_domains) { 1512 pr_debug("no valid rapl domains found in %s\n", rp->name); 1513 return -ENODEV; 1514 } 1515 pr_debug("found %d domains on %s\n", rp->nr_domains, rp->name); 1516 1517 rp->domains = kcalloc(rp->nr_domains, sizeof(struct rapl_domain), 1518 GFP_KERNEL); 1519 if (!rp->domains) 1520 return -ENOMEM; 1521 1522 rapl_init_domains(rp); 1523 1524 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 1525 rapl_get_domain_unit(rd); 1526 rapl_detect_powerlimit(rd); 1527 } 1528 1529 return 0; 1530 } 1531 1532 #ifdef CONFIG_PERF_EVENTS 1533 1534 /* 1535 * Support for RAPL PMU 1536 * 1537 * Register a PMU if any of the registered RAPL Packages have the requirement 1538 * of exposing its energy counters via Perf PMU. 1539 * 1540 * PMU Name: 1541 * power 1542 * 1543 * Events: 1544 * Name Event id RAPL Domain 1545 * energy_cores 0x01 RAPL_DOMAIN_PP0 1546 * energy_pkg 0x02 RAPL_DOMAIN_PACKAGE 1547 * energy_ram 0x03 RAPL_DOMAIN_DRAM 1548 * energy_gpu 0x04 RAPL_DOMAIN_PP1 1549 * energy_psys 0x05 RAPL_DOMAIN_PLATFORM 1550 * 1551 * Unit: 1552 * Joules 1553 * 1554 * Scale: 1555 * 2.3283064365386962890625e-10 1556 * The same RAPL domain in different RAPL Packages may have different 1557 * energy units. Use 2.3283064365386962890625e-10 (2^-32) Joules as 1558 * the fixed unit for all energy counters, and covert each hardware 1559 * counter increase to N times of PMU event counter increases. 1560 * 1561 * This is fully compatible with the current MSR RAPL PMU. This means that 1562 * userspace programs like turbostat can use the same code to handle RAPL Perf 1563 * PMU, no matter what RAPL Interface driver (MSR/TPMI, etc) is running 1564 * underlying on the platform. 1565 * 1566 * Note that RAPL Packages can be probed/removed dynamically, and the events 1567 * supported by each TPMI RAPL device can be different. Thus the RAPL PMU 1568 * support is done on demand, which means 1569 * 1. PMU is registered only if it is needed by a RAPL Package. PMU events for 1570 * unsupported counters are not exposed. 1571 * 2. PMU is unregistered and registered when a new RAPL Package is probed and 1572 * supports new counters that are not supported by current PMU. 1573 * 3. PMU is unregistered when all registered RAPL Packages don't need PMU. 1574 */ 1575 1576 struct rapl_pmu { 1577 struct pmu pmu; /* Perf PMU structure */ 1578 u64 timer_ms; /* Maximum expiration time to avoid counter overflow */ 1579 unsigned long domain_map; /* Events supported by current registered PMU */ 1580 bool registered; /* Whether the PMU has been registered or not */ 1581 }; 1582 1583 static struct rapl_pmu rapl_pmu; 1584 1585 /* PMU helpers */ 1586 1587 static int get_pmu_cpu(struct rapl_package *rp) 1588 { 1589 int cpu; 1590 1591 if (!rp->has_pmu) 1592 return nr_cpu_ids; 1593 1594 /* Only TPMI RAPL is supported for now */ 1595 if (rp->priv->type != RAPL_IF_TPMI) 1596 return nr_cpu_ids; 1597 1598 /* TPMI RAPL uses any CPU in the package for PMU */ 1599 for_each_online_cpu(cpu) 1600 if (topology_physical_package_id(cpu) == rp->id) 1601 return cpu; 1602 1603 return nr_cpu_ids; 1604 } 1605 1606 static bool is_rp_pmu_cpu(struct rapl_package *rp, int cpu) 1607 { 1608 if (!rp->has_pmu) 1609 return false; 1610 1611 /* Only TPMI RAPL is supported for now */ 1612 if (rp->priv->type != RAPL_IF_TPMI) 1613 return false; 1614 1615 /* TPMI RAPL uses any CPU in the package for PMU */ 1616 return topology_physical_package_id(cpu) == rp->id; 1617 } 1618 1619 static struct rapl_package_pmu_data *event_to_pmu_data(struct perf_event *event) 1620 { 1621 struct rapl_package *rp = event->pmu_private; 1622 1623 return &rp->pmu_data; 1624 } 1625 1626 /* PMU event callbacks */ 1627 1628 static u64 event_read_counter(struct perf_event *event) 1629 { 1630 struct rapl_package *rp = event->pmu_private; 1631 u64 val; 1632 int ret; 1633 1634 /* Return 0 for unsupported events */ 1635 if (event->hw.idx < 0) 1636 return 0; 1637 1638 ret = rapl_read_data_raw(&rp->domains[event->hw.idx], ENERGY_COUNTER, false, &val); 1639 1640 /* Return 0 for failed read */ 1641 if (ret) 1642 return 0; 1643 1644 return val; 1645 } 1646 1647 static void __rapl_pmu_event_start(struct perf_event *event) 1648 { 1649 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1650 1651 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) 1652 return; 1653 1654 event->hw.state = 0; 1655 1656 list_add_tail(&event->active_entry, &data->active_list); 1657 1658 local64_set(&event->hw.prev_count, event_read_counter(event)); 1659 if (++data->n_active == 1) 1660 hrtimer_start(&data->hrtimer, data->timer_interval, 1661 HRTIMER_MODE_REL_PINNED); 1662 } 1663 1664 static void rapl_pmu_event_start(struct perf_event *event, int mode) 1665 { 1666 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1667 unsigned long flags; 1668 1669 raw_spin_lock_irqsave(&data->lock, flags); 1670 __rapl_pmu_event_start(event); 1671 raw_spin_unlock_irqrestore(&data->lock, flags); 1672 } 1673 1674 static u64 rapl_event_update(struct perf_event *event) 1675 { 1676 struct hw_perf_event *hwc = &event->hw; 1677 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1678 u64 prev_raw_count, new_raw_count; 1679 s64 delta, sdelta; 1680 1681 /* 1682 * Follow the generic code to drain hwc->prev_count. 1683 * The loop is not expected to run for multiple times. 1684 */ 1685 prev_raw_count = local64_read(&hwc->prev_count); 1686 do { 1687 new_raw_count = event_read_counter(event); 1688 } while (!local64_try_cmpxchg(&hwc->prev_count, 1689 &prev_raw_count, new_raw_count)); 1690 1691 1692 /* 1693 * Now we have the new raw value and have updated the prev 1694 * timestamp already. We can now calculate the elapsed delta 1695 * (event-)time and add that to the generic event. 1696 */ 1697 delta = new_raw_count - prev_raw_count; 1698 1699 /* 1700 * Scale delta to smallest unit (2^-32) 1701 * users must then scale back: count * 1/(1e9*2^32) to get Joules 1702 * or use ldexp(count, -32). 1703 * Watts = Joules/Time delta 1704 */ 1705 sdelta = delta * data->scale[event->hw.flags]; 1706 1707 local64_add(sdelta, &event->count); 1708 1709 return new_raw_count; 1710 } 1711 1712 static void rapl_pmu_event_stop(struct perf_event *event, int mode) 1713 { 1714 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1715 struct hw_perf_event *hwc = &event->hw; 1716 unsigned long flags; 1717 1718 raw_spin_lock_irqsave(&data->lock, flags); 1719 1720 /* Mark event as deactivated and stopped */ 1721 if (!(hwc->state & PERF_HES_STOPPED)) { 1722 WARN_ON_ONCE(data->n_active <= 0); 1723 if (--data->n_active == 0) 1724 hrtimer_cancel(&data->hrtimer); 1725 1726 list_del(&event->active_entry); 1727 1728 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); 1729 hwc->state |= PERF_HES_STOPPED; 1730 } 1731 1732 /* Check if update of sw counter is necessary */ 1733 if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { 1734 /* 1735 * Drain the remaining delta count out of a event 1736 * that we are disabling: 1737 */ 1738 rapl_event_update(event); 1739 hwc->state |= PERF_HES_UPTODATE; 1740 } 1741 1742 raw_spin_unlock_irqrestore(&data->lock, flags); 1743 } 1744 1745 static int rapl_pmu_event_add(struct perf_event *event, int mode) 1746 { 1747 struct rapl_package_pmu_data *data = event_to_pmu_data(event); 1748 struct hw_perf_event *hwc = &event->hw; 1749 unsigned long flags; 1750 1751 raw_spin_lock_irqsave(&data->lock, flags); 1752 1753 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; 1754 1755 if (mode & PERF_EF_START) 1756 __rapl_pmu_event_start(event); 1757 1758 raw_spin_unlock_irqrestore(&data->lock, flags); 1759 1760 return 0; 1761 } 1762 1763 static void rapl_pmu_event_del(struct perf_event *event, int flags) 1764 { 1765 rapl_pmu_event_stop(event, PERF_EF_UPDATE); 1766 } 1767 1768 /* RAPL PMU event ids, same as shown in sysfs */ 1769 enum perf_rapl_events { 1770 PERF_RAPL_PP0 = 1, /* all cores */ 1771 PERF_RAPL_PKG, /* entire package */ 1772 PERF_RAPL_RAM, /* DRAM */ 1773 PERF_RAPL_PP1, /* gpu */ 1774 PERF_RAPL_PSYS, /* psys */ 1775 PERF_RAPL_MAX 1776 }; 1777 #define RAPL_EVENT_MASK GENMASK(7, 0) 1778 1779 static const int event_to_domain[PERF_RAPL_MAX] = { 1780 [PERF_RAPL_PP0] = RAPL_DOMAIN_PP0, 1781 [PERF_RAPL_PKG] = RAPL_DOMAIN_PACKAGE, 1782 [PERF_RAPL_RAM] = RAPL_DOMAIN_DRAM, 1783 [PERF_RAPL_PP1] = RAPL_DOMAIN_PP1, 1784 [PERF_RAPL_PSYS] = RAPL_DOMAIN_PLATFORM, 1785 }; 1786 1787 static int rapl_pmu_event_init(struct perf_event *event) 1788 { 1789 struct rapl_package *pos, *rp = NULL; 1790 u64 cfg = event->attr.config & RAPL_EVENT_MASK; 1791 int domain, idx; 1792 1793 /* Only look at RAPL events */ 1794 if (event->attr.type != event->pmu->type) 1795 return -ENOENT; 1796 1797 /* Check for supported events only */ 1798 if (!cfg || cfg >= PERF_RAPL_MAX) 1799 return -EINVAL; 1800 1801 if (event->cpu < 0) 1802 return -EINVAL; 1803 1804 /* Find out which Package the event belongs to */ 1805 list_for_each_entry(pos, &rapl_packages, plist) { 1806 if (is_rp_pmu_cpu(pos, event->cpu)) { 1807 rp = pos; 1808 break; 1809 } 1810 } 1811 if (!rp) 1812 return -ENODEV; 1813 1814 /* Find out which RAPL Domain the event belongs to */ 1815 domain = event_to_domain[cfg]; 1816 1817 event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; 1818 event->pmu_private = rp; /* Which package */ 1819 event->hw.flags = domain; /* Which domain */ 1820 1821 event->hw.idx = -1; 1822 /* Find out the index in rp->domains[] to get domain pointer */ 1823 for (idx = 0; idx < rp->nr_domains; idx++) { 1824 if (rp->domains[idx].id == domain) { 1825 event->hw.idx = idx; 1826 break; 1827 } 1828 } 1829 1830 return 0; 1831 } 1832 1833 static void rapl_pmu_event_read(struct perf_event *event) 1834 { 1835 rapl_event_update(event); 1836 } 1837 1838 static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) 1839 { 1840 struct rapl_package_pmu_data *data = 1841 container_of(hrtimer, struct rapl_package_pmu_data, hrtimer); 1842 struct perf_event *event; 1843 unsigned long flags; 1844 1845 if (!data->n_active) 1846 return HRTIMER_NORESTART; 1847 1848 raw_spin_lock_irqsave(&data->lock, flags); 1849 1850 list_for_each_entry(event, &data->active_list, active_entry) 1851 rapl_event_update(event); 1852 1853 raw_spin_unlock_irqrestore(&data->lock, flags); 1854 1855 hrtimer_forward_now(hrtimer, data->timer_interval); 1856 1857 return HRTIMER_RESTART; 1858 } 1859 1860 /* PMU sysfs attributes */ 1861 1862 /* 1863 * There are no default events, but we need to create "events" group (with 1864 * empty attrs) before updating it with detected events. 1865 */ 1866 static struct attribute *attrs_empty[] = { 1867 NULL, 1868 }; 1869 1870 static struct attribute_group pmu_events_group = { 1871 .name = "events", 1872 .attrs = attrs_empty, 1873 }; 1874 1875 static ssize_t cpumask_show(struct device *dev, 1876 struct device_attribute *attr, char *buf) 1877 { 1878 struct rapl_package *rp; 1879 cpumask_var_t cpu_mask; 1880 int cpu; 1881 int ret; 1882 1883 if (!alloc_cpumask_var(&cpu_mask, GFP_KERNEL)) 1884 return -ENOMEM; 1885 1886 cpus_read_lock(); 1887 1888 cpumask_clear(cpu_mask); 1889 1890 /* Choose a cpu for each RAPL Package */ 1891 list_for_each_entry(rp, &rapl_packages, plist) { 1892 cpu = get_pmu_cpu(rp); 1893 if (cpu < nr_cpu_ids) 1894 cpumask_set_cpu(cpu, cpu_mask); 1895 } 1896 cpus_read_unlock(); 1897 1898 ret = cpumap_print_to_pagebuf(true, buf, cpu_mask); 1899 1900 free_cpumask_var(cpu_mask); 1901 1902 return ret; 1903 } 1904 1905 static DEVICE_ATTR_RO(cpumask); 1906 1907 static struct attribute *pmu_cpumask_attrs[] = { 1908 &dev_attr_cpumask.attr, 1909 NULL 1910 }; 1911 1912 static struct attribute_group pmu_cpumask_group = { 1913 .attrs = pmu_cpumask_attrs, 1914 }; 1915 1916 PMU_FORMAT_ATTR(event, "config:0-7"); 1917 static struct attribute *pmu_format_attr[] = { 1918 &format_attr_event.attr, 1919 NULL 1920 }; 1921 1922 static struct attribute_group pmu_format_group = { 1923 .name = "format", 1924 .attrs = pmu_format_attr, 1925 }; 1926 1927 static const struct attribute_group *pmu_attr_groups[] = { 1928 &pmu_events_group, 1929 &pmu_cpumask_group, 1930 &pmu_format_group, 1931 NULL 1932 }; 1933 1934 #define RAPL_EVENT_ATTR_STR(_name, v, str) \ 1935 static struct perf_pmu_events_attr event_attr_##v = { \ 1936 .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ 1937 .event_str = str, \ 1938 } 1939 1940 RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); 1941 RAPL_EVENT_ATTR_STR(energy-pkg, rapl_pkg, "event=0x02"); 1942 RAPL_EVENT_ATTR_STR(energy-ram, rapl_ram, "event=0x03"); 1943 RAPL_EVENT_ATTR_STR(energy-gpu, rapl_gpu, "event=0x04"); 1944 RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05"); 1945 1946 RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_unit_cores, "Joules"); 1947 RAPL_EVENT_ATTR_STR(energy-pkg.unit, rapl_unit_pkg, "Joules"); 1948 RAPL_EVENT_ATTR_STR(energy-ram.unit, rapl_unit_ram, "Joules"); 1949 RAPL_EVENT_ATTR_STR(energy-gpu.unit, rapl_unit_gpu, "Joules"); 1950 RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_unit_psys, "Joules"); 1951 1952 RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_scale_cores, "2.3283064365386962890625e-10"); 1953 RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_scale_pkg, "2.3283064365386962890625e-10"); 1954 RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_scale_ram, "2.3283064365386962890625e-10"); 1955 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_scale_gpu, "2.3283064365386962890625e-10"); 1956 RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_scale_psys, "2.3283064365386962890625e-10"); 1957 1958 #define RAPL_EVENT_GROUP(_name, domain) \ 1959 static struct attribute *pmu_attr_##_name[] = { \ 1960 &event_attr_rapl_##_name.attr.attr, \ 1961 &event_attr_rapl_unit_##_name.attr.attr, \ 1962 &event_attr_rapl_scale_##_name.attr.attr, \ 1963 NULL \ 1964 }; \ 1965 static umode_t is_visible_##_name(struct kobject *kobj, struct attribute *attr, int event) \ 1966 { \ 1967 return rapl_pmu.domain_map & BIT(domain) ? attr->mode : 0; \ 1968 } \ 1969 static struct attribute_group pmu_group_##_name = { \ 1970 .name = "events", \ 1971 .attrs = pmu_attr_##_name, \ 1972 .is_visible = is_visible_##_name, \ 1973 } 1974 1975 RAPL_EVENT_GROUP(cores, RAPL_DOMAIN_PP0); 1976 RAPL_EVENT_GROUP(pkg, RAPL_DOMAIN_PACKAGE); 1977 RAPL_EVENT_GROUP(ram, RAPL_DOMAIN_DRAM); 1978 RAPL_EVENT_GROUP(gpu, RAPL_DOMAIN_PP1); 1979 RAPL_EVENT_GROUP(psys, RAPL_DOMAIN_PLATFORM); 1980 1981 static const struct attribute_group *pmu_attr_update[] = { 1982 &pmu_group_cores, 1983 &pmu_group_pkg, 1984 &pmu_group_ram, 1985 &pmu_group_gpu, 1986 &pmu_group_psys, 1987 NULL 1988 }; 1989 1990 static int rapl_pmu_update(struct rapl_package *rp) 1991 { 1992 int ret = 0; 1993 1994 /* Return if PMU already covers all events supported by current RAPL Package */ 1995 if (rapl_pmu.registered && !(rp->domain_map & (~rapl_pmu.domain_map))) 1996 goto end; 1997 1998 /* Unregister previous registered PMU */ 1999 if (rapl_pmu.registered) 2000 perf_pmu_unregister(&rapl_pmu.pmu); 2001 2002 rapl_pmu.registered = false; 2003 rapl_pmu.domain_map |= rp->domain_map; 2004 2005 memset(&rapl_pmu.pmu, 0, sizeof(struct pmu)); 2006 rapl_pmu.pmu.attr_groups = pmu_attr_groups; 2007 rapl_pmu.pmu.attr_update = pmu_attr_update; 2008 rapl_pmu.pmu.task_ctx_nr = perf_invalid_context; 2009 rapl_pmu.pmu.event_init = rapl_pmu_event_init; 2010 rapl_pmu.pmu.add = rapl_pmu_event_add; 2011 rapl_pmu.pmu.del = rapl_pmu_event_del; 2012 rapl_pmu.pmu.start = rapl_pmu_event_start; 2013 rapl_pmu.pmu.stop = rapl_pmu_event_stop; 2014 rapl_pmu.pmu.read = rapl_pmu_event_read; 2015 rapl_pmu.pmu.module = THIS_MODULE; 2016 rapl_pmu.pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT; 2017 ret = perf_pmu_register(&rapl_pmu.pmu, "power", -1); 2018 if (ret) { 2019 pr_info("Failed to register PMU\n"); 2020 return ret; 2021 } 2022 2023 rapl_pmu.registered = true; 2024 end: 2025 rp->has_pmu = true; 2026 return ret; 2027 } 2028 2029 int rapl_package_add_pmu(struct rapl_package *rp) 2030 { 2031 struct rapl_package_pmu_data *data = &rp->pmu_data; 2032 int idx; 2033 2034 if (rp->has_pmu) 2035 return -EEXIST; 2036 2037 guard(cpus_read_lock)(); 2038 2039 for (idx = 0; idx < rp->nr_domains; idx++) { 2040 struct rapl_domain *rd = &rp->domains[idx]; 2041 int domain = rd->id; 2042 u64 val; 2043 2044 if (!test_bit(domain, &rp->domain_map)) 2045 continue; 2046 2047 /* 2048 * The RAPL PMU granularity is 2^-32 Joules 2049 * data->scale[]: times of 2^-32 Joules for each ENERGY COUNTER increase 2050 */ 2051 val = rd->energy_unit * (1ULL << 32); 2052 do_div(val, ENERGY_UNIT_SCALE * 1000000); 2053 data->scale[domain] = val; 2054 2055 if (!rapl_pmu.timer_ms) { 2056 struct rapl_primitive_info *rpi = get_rpi(rp, ENERGY_COUNTER); 2057 2058 /* 2059 * Calculate the timer rate: 2060 * Use reference of 200W for scaling the timeout to avoid counter 2061 * overflows. 2062 * 2063 * max_count = rpi->mask >> rpi->shift + 1 2064 * max_energy_pj = max_count * rd->energy_unit 2065 * max_time_sec = (max_energy_pj / 1000000000) / 200w 2066 * 2067 * rapl_pmu.timer_ms = max_time_sec * 1000 / 2 2068 */ 2069 val = (rpi->mask >> rpi->shift) + 1; 2070 val *= rd->energy_unit; 2071 do_div(val, 1000000 * 200 * 2); 2072 rapl_pmu.timer_ms = val; 2073 2074 pr_debug("%llu ms overflow timer\n", rapl_pmu.timer_ms); 2075 } 2076 2077 pr_debug("Domain %s: hw unit %lld * 2^-32 Joules\n", rd->name, data->scale[domain]); 2078 } 2079 2080 /* Initialize per package PMU data */ 2081 raw_spin_lock_init(&data->lock); 2082 INIT_LIST_HEAD(&data->active_list); 2083 data->timer_interval = ms_to_ktime(rapl_pmu.timer_ms); 2084 hrtimer_setup(&data->hrtimer, rapl_hrtimer_handle, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2085 2086 return rapl_pmu_update(rp); 2087 } 2088 EXPORT_SYMBOL_GPL(rapl_package_add_pmu); 2089 2090 void rapl_package_remove_pmu(struct rapl_package *rp) 2091 { 2092 struct rapl_package *pos; 2093 2094 if (!rp->has_pmu) 2095 return; 2096 2097 guard(cpus_read_lock)(); 2098 2099 list_for_each_entry(pos, &rapl_packages, plist) { 2100 /* PMU is still needed */ 2101 if (pos->has_pmu && pos != rp) 2102 return; 2103 } 2104 2105 perf_pmu_unregister(&rapl_pmu.pmu); 2106 memset(&rapl_pmu, 0, sizeof(struct rapl_pmu)); 2107 } 2108 EXPORT_SYMBOL_GPL(rapl_package_remove_pmu); 2109 #endif 2110 2111 /* called from CPU hotplug notifier, hotplug lock held */ 2112 void rapl_remove_package_cpuslocked(struct rapl_package *rp) 2113 { 2114 struct rapl_domain *rd, *rd_package = NULL; 2115 2116 package_power_limit_irq_restore(rp); 2117 2118 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) { 2119 int i; 2120 2121 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 2122 rapl_write_pl_data(rd, i, PL_ENABLE, 0); 2123 rapl_write_pl_data(rd, i, PL_CLAMP, 0); 2124 } 2125 2126 if (rd->id == RAPL_DOMAIN_PACKAGE) { 2127 rd_package = rd; 2128 continue; 2129 } 2130 pr_debug("remove package, undo power limit on %s: %s\n", 2131 rp->name, rd->name); 2132 powercap_unregister_zone(rp->priv->control_type, 2133 &rd->power_zone); 2134 } 2135 /* do parent zone last */ 2136 powercap_unregister_zone(rp->priv->control_type, 2137 &rd_package->power_zone); 2138 list_del(&rp->plist); 2139 kfree(rp); 2140 } 2141 EXPORT_SYMBOL_GPL(rapl_remove_package_cpuslocked); 2142 2143 void rapl_remove_package(struct rapl_package *rp) 2144 { 2145 guard(cpus_read_lock)(); 2146 rapl_remove_package_cpuslocked(rp); 2147 } 2148 EXPORT_SYMBOL_GPL(rapl_remove_package); 2149 2150 /* 2151 * RAPL Package energy counter scope: 2152 * 1. AMD/HYGON platforms use per-PKG package energy counter 2153 * 2. For Intel platforms 2154 * 2.1 CLX-AP platform has per-DIE package energy counter 2155 * 2.2 Other platforms that uses MSR RAPL are single die systems so the 2156 * package energy counter can be considered as per-PKG/per-DIE, 2157 * here it is considered as per-DIE. 2158 * 2.3 New platforms that use TPMI RAPL doesn't care about the 2159 * scope because they are not MSR/CPU based. 2160 */ 2161 #define rapl_msrs_are_pkg_scope() \ 2162 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \ 2163 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 2164 2165 /* caller to ensure CPU hotplug lock is held */ 2166 struct rapl_package *rapl_find_package_domain_cpuslocked(int id, struct rapl_if_priv *priv, 2167 bool id_is_cpu) 2168 { 2169 struct rapl_package *rp; 2170 int uid; 2171 2172 if (id_is_cpu) { 2173 uid = rapl_msrs_are_pkg_scope() ? 2174 topology_physical_package_id(id) : topology_logical_die_id(id); 2175 if (uid < 0) { 2176 pr_err("topology_logical_(package/die)_id() returned a negative value"); 2177 return NULL; 2178 } 2179 } 2180 else 2181 uid = id; 2182 2183 list_for_each_entry(rp, &rapl_packages, plist) { 2184 if (rp->id == uid 2185 && rp->priv->control_type == priv->control_type) 2186 return rp; 2187 } 2188 2189 return NULL; 2190 } 2191 EXPORT_SYMBOL_GPL(rapl_find_package_domain_cpuslocked); 2192 2193 struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2194 { 2195 guard(cpus_read_lock)(); 2196 return rapl_find_package_domain_cpuslocked(id, priv, id_is_cpu); 2197 } 2198 EXPORT_SYMBOL_GPL(rapl_find_package_domain); 2199 2200 /* called from CPU hotplug notifier, hotplug lock held */ 2201 struct rapl_package *rapl_add_package_cpuslocked(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2202 { 2203 struct rapl_package *rp; 2204 int ret; 2205 2206 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL); 2207 if (!rp) 2208 return ERR_PTR(-ENOMEM); 2209 2210 if (id_is_cpu) { 2211 rp->id = rapl_msrs_are_pkg_scope() ? 2212 topology_physical_package_id(id) : topology_logical_die_id(id); 2213 if ((int)(rp->id) < 0) { 2214 pr_err("topology_logical_(package/die)_id() returned a negative value"); 2215 return ERR_PTR(-EINVAL); 2216 } 2217 rp->lead_cpu = id; 2218 if (!rapl_msrs_are_pkg_scope() && topology_max_dies_per_package() > 1) 2219 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d-die-%d", 2220 topology_physical_package_id(id), topology_die_id(id)); 2221 else 2222 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", 2223 topology_physical_package_id(id)); 2224 } else { 2225 rp->id = id; 2226 rp->lead_cpu = -1; 2227 snprintf(rp->name, PACKAGE_DOMAIN_NAME_LENGTH, "package-%d", id); 2228 } 2229 2230 rp->priv = priv; 2231 ret = rapl_config(rp); 2232 if (ret) 2233 goto err_free_package; 2234 2235 /* check if the package contains valid domains */ 2236 if (rapl_detect_domains(rp)) { 2237 ret = -ENODEV; 2238 goto err_free_package; 2239 } 2240 ret = rapl_package_register_powercap(rp); 2241 if (!ret) { 2242 INIT_LIST_HEAD(&rp->plist); 2243 list_add(&rp->plist, &rapl_packages); 2244 return rp; 2245 } 2246 2247 err_free_package: 2248 kfree(rp->domains); 2249 kfree(rp); 2250 return ERR_PTR(ret); 2251 } 2252 EXPORT_SYMBOL_GPL(rapl_add_package_cpuslocked); 2253 2254 struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu) 2255 { 2256 guard(cpus_read_lock)(); 2257 return rapl_add_package_cpuslocked(id, priv, id_is_cpu); 2258 } 2259 EXPORT_SYMBOL_GPL(rapl_add_package); 2260 2261 static void power_limit_state_save(void) 2262 { 2263 struct rapl_package *rp; 2264 struct rapl_domain *rd; 2265 int ret, i; 2266 2267 cpus_read_lock(); 2268 list_for_each_entry(rp, &rapl_packages, plist) { 2269 if (!rp->power_zone) 2270 continue; 2271 rd = power_zone_to_rapl_domain(rp->power_zone); 2272 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) { 2273 ret = rapl_read_pl_data(rd, i, PL_LIMIT, true, 2274 &rd->rpl[i].last_power_limit); 2275 if (ret) 2276 rd->rpl[i].last_power_limit = 0; 2277 } 2278 } 2279 cpus_read_unlock(); 2280 } 2281 2282 static void power_limit_state_restore(void) 2283 { 2284 struct rapl_package *rp; 2285 struct rapl_domain *rd; 2286 int i; 2287 2288 cpus_read_lock(); 2289 list_for_each_entry(rp, &rapl_packages, plist) { 2290 if (!rp->power_zone) 2291 continue; 2292 rd = power_zone_to_rapl_domain(rp->power_zone); 2293 for (i = POWER_LIMIT1; i < NR_POWER_LIMITS; i++) 2294 if (rd->rpl[i].last_power_limit) 2295 rapl_write_pl_data(rd, i, PL_LIMIT, 2296 rd->rpl[i].last_power_limit); 2297 } 2298 cpus_read_unlock(); 2299 } 2300 2301 static int rapl_pm_callback(struct notifier_block *nb, 2302 unsigned long mode, void *_unused) 2303 { 2304 switch (mode) { 2305 case PM_SUSPEND_PREPARE: 2306 power_limit_state_save(); 2307 break; 2308 case PM_POST_SUSPEND: 2309 power_limit_state_restore(); 2310 break; 2311 } 2312 return NOTIFY_OK; 2313 } 2314 2315 static struct notifier_block rapl_pm_notifier = { 2316 .notifier_call = rapl_pm_callback, 2317 }; 2318 2319 static struct platform_device *rapl_msr_platdev; 2320 2321 static int __init rapl_init(void) 2322 { 2323 const struct x86_cpu_id *id; 2324 int ret; 2325 2326 id = x86_match_cpu(rapl_ids); 2327 if (id) { 2328 defaults_msr = (struct rapl_defaults *)id->driver_data; 2329 2330 rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0); 2331 if (!rapl_msr_platdev) 2332 return -ENOMEM; 2333 2334 ret = platform_device_add(rapl_msr_platdev); 2335 if (ret) { 2336 platform_device_put(rapl_msr_platdev); 2337 return ret; 2338 } 2339 } 2340 2341 ret = register_pm_notifier(&rapl_pm_notifier); 2342 if (ret && rapl_msr_platdev) { 2343 platform_device_del(rapl_msr_platdev); 2344 platform_device_put(rapl_msr_platdev); 2345 } 2346 2347 return ret; 2348 } 2349 2350 static void __exit rapl_exit(void) 2351 { 2352 platform_device_unregister(rapl_msr_platdev); 2353 unregister_pm_notifier(&rapl_pm_notifier); 2354 } 2355 2356 fs_initcall(rapl_init); 2357 module_exit(rapl_exit); 2358 2359 MODULE_DESCRIPTION("Intel Runtime Average Power Limit (RAPL) common code"); 2360 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 2361 MODULE_LICENSE("GPL v2"); 2362