1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi MIPS SoC reset driver 4 * 5 * License: Dual MIT/GPL 6 * Copyright (c) 2017 Microsemi Corporation 7 */ 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/notifier.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/platform_device.h> 13 #include <linux/property.h> 14 #include <linux/reboot.h> 15 #include <linux/regmap.h> 16 17 struct reset_props { 18 const char *syscon; 19 u32 protect_reg; 20 u32 vcore_protect; 21 u32 if_si_owner_bit; 22 }; 23 24 struct ocelot_reset_context { 25 void __iomem *base; 26 struct regmap *cpu_ctrl; 27 const struct reset_props *props; 28 struct notifier_block restart_handler; 29 }; 30 31 #define BIT_OFF_INVALID 32 32 33 #define SOFT_CHIP_RST BIT(0) 34 35 #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24 36 #define IF_SI_OWNER_MASK GENMASK(1, 0) 37 #define IF_SI_OWNER_SISL 0 38 #define IF_SI_OWNER_SIBM 1 39 #define IF_SI_OWNER_SIMC 2 40 41 static int ocelot_restart_handle(struct notifier_block *this, 42 unsigned long mode, void *cmd) 43 { 44 struct ocelot_reset_context *ctx = container_of(this, struct 45 ocelot_reset_context, 46 restart_handler); 47 u32 if_si_owner_bit = ctx->props->if_si_owner_bit; 48 49 /* Make sure the core is not protected from reset */ 50 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, 51 ctx->props->vcore_protect, 0); 52 53 /* Make the SI back to boot mode */ 54 if (if_si_owner_bit != BIT_OFF_INVALID) 55 regmap_update_bits(ctx->cpu_ctrl, 56 ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL, 57 IF_SI_OWNER_MASK << if_si_owner_bit, 58 IF_SI_OWNER_SIBM << if_si_owner_bit); 59 60 pr_emerg("Resetting SoC\n"); 61 62 writel(SOFT_CHIP_RST, ctx->base); 63 64 pr_emerg("Unable to restart system\n"); 65 return NOTIFY_DONE; 66 } 67 68 static int ocelot_reset_probe(struct platform_device *pdev) 69 { 70 struct ocelot_reset_context *ctx; 71 struct device *dev = &pdev->dev; 72 int err; 73 74 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); 75 if (!ctx) 76 return -ENOMEM; 77 78 ctx->base = devm_platform_ioremap_resource(pdev, 0); 79 if (IS_ERR(ctx->base)) 80 return PTR_ERR(ctx->base); 81 82 ctx->props = device_get_match_data(dev); 83 84 ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon); 85 if (IS_ERR(ctx->cpu_ctrl)) { 86 dev_err(dev, "No syscon map: %s\n", ctx->props->syscon); 87 return PTR_ERR(ctx->cpu_ctrl); 88 } 89 90 ctx->restart_handler.notifier_call = ocelot_restart_handle; 91 ctx->restart_handler.priority = 192; 92 err = register_restart_handler(&ctx->restart_handler); 93 if (err) 94 dev_err(dev, "can't register restart notifier (err=%d)\n", err); 95 96 return err; 97 } 98 99 static const struct reset_props reset_props_jaguar2 = { 100 .syscon = "mscc,ocelot-cpu-syscon", 101 .protect_reg = 0x20, 102 .vcore_protect = BIT(2), 103 .if_si_owner_bit = 6, 104 }; 105 106 static const struct reset_props reset_props_luton = { 107 .syscon = "mscc,ocelot-cpu-syscon", 108 .protect_reg = 0x20, 109 .vcore_protect = BIT(2), 110 .if_si_owner_bit = BIT_OFF_INVALID, /* n/a */ 111 }; 112 113 static const struct reset_props reset_props_ocelot = { 114 .syscon = "mscc,ocelot-cpu-syscon", 115 .protect_reg = 0x20, 116 .vcore_protect = BIT(2), 117 .if_si_owner_bit = 4, 118 }; 119 120 static const struct reset_props reset_props_sparx5 = { 121 .syscon = "microchip,sparx5-cpu-syscon", 122 .protect_reg = 0x84, 123 .vcore_protect = BIT(10), 124 .if_si_owner_bit = 6, 125 }; 126 127 static const struct of_device_id ocelot_reset_of_match[] = { 128 { 129 .compatible = "mscc,jaguar2-chip-reset", 130 .data = &reset_props_jaguar2 131 }, { 132 .compatible = "mscc,luton-chip-reset", 133 .data = &reset_props_luton 134 }, { 135 .compatible = "mscc,ocelot-chip-reset", 136 .data = &reset_props_ocelot 137 }, { 138 .compatible = "microchip,sparx5-chip-reset", 139 .data = &reset_props_sparx5 140 }, 141 { /*sentinel*/ } 142 }; 143 144 static struct platform_driver ocelot_reset_driver = { 145 .probe = ocelot_reset_probe, 146 .driver = { 147 .name = "ocelot-chip-reset", 148 .of_match_table = ocelot_reset_of_match, 149 }, 150 }; 151 builtin_platform_driver(ocelot_reset_driver); 152