1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip Generic power domain support. 4 * 5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd. 6 */ 7 8 #include <linux/arm-smccc.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/err.h> 12 #include <linux/mutex.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_clock.h> 15 #include <linux/pm_domain.h> 16 #include <linux/property.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_clk.h> 20 #include <linux/clk.h> 21 #include <linux/regmap.h> 22 #include <linux/mfd/syscon.h> 23 #include <soc/rockchip/pm_domains.h> 24 #include <soc/rockchip/rockchip_sip.h> 25 #include <dt-bindings/power/px30-power.h> 26 #include <dt-bindings/power/rockchip,rv1126-power.h> 27 #include <dt-bindings/power/rk3036-power.h> 28 #include <dt-bindings/power/rk3066-power.h> 29 #include <dt-bindings/power/rk3128-power.h> 30 #include <dt-bindings/power/rk3188-power.h> 31 #include <dt-bindings/power/rk3228-power.h> 32 #include <dt-bindings/power/rk3288-power.h> 33 #include <dt-bindings/power/rk3328-power.h> 34 #include <dt-bindings/power/rk3366-power.h> 35 #include <dt-bindings/power/rk3368-power.h> 36 #include <dt-bindings/power/rk3399-power.h> 37 #include <dt-bindings/power/rk3568-power.h> 38 #include <dt-bindings/power/rockchip,rk3576-power.h> 39 #include <dt-bindings/power/rk3588-power.h> 40 41 struct rockchip_domain_info { 42 const char *name; 43 int pwr_mask; 44 int status_mask; 45 int req_mask; 46 int idle_mask; 47 int ack_mask; 48 bool active_wakeup; 49 int pwr_w_mask; 50 int req_w_mask; 51 int clk_ungate_mask; 52 int mem_status_mask; 53 int repair_status_mask; 54 u32 pwr_offset; 55 u32 mem_offset; 56 u32 req_offset; 57 }; 58 59 struct rockchip_pmu_info { 60 u32 pwr_offset; 61 u32 status_offset; 62 u32 req_offset; 63 u32 idle_offset; 64 u32 ack_offset; 65 u32 mem_pwr_offset; 66 u32 chain_status_offset; 67 u32 mem_status_offset; 68 u32 repair_status_offset; 69 u32 clk_ungate_offset; 70 71 u32 core_pwrcnt_offset; 72 u32 gpu_pwrcnt_offset; 73 74 unsigned int core_power_transition_time; 75 unsigned int gpu_power_transition_time; 76 77 int num_domains; 78 const struct rockchip_domain_info *domain_info; 79 }; 80 81 #define MAX_QOS_REGS_NUM 5 82 #define QOS_PRIORITY 0x08 83 #define QOS_MODE 0x0c 84 #define QOS_BANDWIDTH 0x10 85 #define QOS_SATURATION 0x14 86 #define QOS_EXTCONTROL 0x18 87 88 struct rockchip_pm_domain { 89 struct generic_pm_domain genpd; 90 const struct rockchip_domain_info *info; 91 struct rockchip_pmu *pmu; 92 int num_qos; 93 struct regmap **qos_regmap; 94 u32 *qos_save_regs[MAX_QOS_REGS_NUM]; 95 int num_clks; 96 struct clk_bulk_data *clks; 97 }; 98 99 struct rockchip_pmu { 100 struct device *dev; 101 struct regmap *regmap; 102 const struct rockchip_pmu_info *info; 103 struct mutex mutex; /* mutex lock for pmu */ 104 struct genpd_onecell_data genpd_data; 105 struct generic_pm_domain *domains[]; 106 }; 107 108 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd) 109 110 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \ 111 { \ 112 .name = _name, \ 113 .pwr_mask = (pwr), \ 114 .status_mask = (status), \ 115 .req_mask = (req), \ 116 .idle_mask = (idle), \ 117 .ack_mask = (ack), \ 118 .active_wakeup = (wakeup), \ 119 } 120 121 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \ 122 { \ 123 .name = _name, \ 124 .pwr_w_mask = (pwr) << 16, \ 125 .pwr_mask = (pwr), \ 126 .status_mask = (status), \ 127 .req_w_mask = (req) << 16, \ 128 .req_mask = (req), \ 129 .idle_mask = (idle), \ 130 .ack_mask = (ack), \ 131 .active_wakeup = wakeup, \ 132 } 133 134 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup) \ 135 { \ 136 .name = _name, \ 137 .pwr_offset = p_offset, \ 138 .pwr_w_mask = (pwr) << 16, \ 139 .pwr_mask = (pwr), \ 140 .status_mask = (status), \ 141 .mem_offset = m_offset, \ 142 .mem_status_mask = (m_status), \ 143 .repair_status_mask = (r_status), \ 144 .req_offset = r_offset, \ 145 .req_w_mask = (req) << 16, \ 146 .req_mask = (req), \ 147 .idle_mask = (idle), \ 148 .ack_mask = (ack), \ 149 .active_wakeup = wakeup, \ 150 } 151 152 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \ 153 { \ 154 .name = _name, \ 155 .pwr_offset = p_offset, \ 156 .pwr_w_mask = (pwr) << 16, \ 157 .pwr_mask = (pwr), \ 158 .status_mask = (status), \ 159 .mem_offset = m_offset, \ 160 .mem_status_mask = (m_status), \ 161 .repair_status_mask = (r_status), \ 162 .req_offset = r_offset, \ 163 .req_w_mask = (req) << 16, \ 164 .req_mask = (req), \ 165 .idle_mask = (idle), \ 166 .clk_ungate_mask = (g_mask), \ 167 .ack_mask = (ack), \ 168 .active_wakeup = wakeup, \ 169 } 170 171 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \ 172 { \ 173 .name = _name, \ 174 .req_mask = (req), \ 175 .req_w_mask = (req) << 16, \ 176 .ack_mask = (ack), \ 177 .idle_mask = (idle), \ 178 .active_wakeup = wakeup, \ 179 } 180 181 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \ 182 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup) 183 184 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \ 185 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup) 186 187 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \ 188 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup) 189 190 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \ 191 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup) 192 193 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \ 194 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup) 195 196 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \ 197 DOMAIN(name, pwr, status, req, req, req, wakeup) 198 199 #define DOMAIN_RK3568(name, pwr, req, wakeup) \ 200 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup) 201 202 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \ 203 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup) 204 205 /* 206 * Dynamic Memory Controller may need to coordinate with us -- see 207 * rockchip_pmu_block(). 208 * 209 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to 210 * block() while we're initializing the PMU. 211 */ 212 static DEFINE_MUTEX(dmc_pmu_mutex); 213 static struct rockchip_pmu *dmc_pmu; 214 215 /* 216 * Block PMU transitions and make sure they don't interfere with ARM Trusted 217 * Firmware operations. There are two conflicts, noted in the comments below. 218 * 219 * Caller must unblock PMU transitions via rockchip_pmu_unblock(). 220 */ 221 int rockchip_pmu_block(void) 222 { 223 struct rockchip_pmu *pmu; 224 struct generic_pm_domain *genpd; 225 struct rockchip_pm_domain *pd; 226 int i, ret; 227 228 mutex_lock(&dmc_pmu_mutex); 229 230 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */ 231 if (!dmc_pmu) 232 return 0; 233 pmu = dmc_pmu; 234 235 /* 236 * mutex blocks all idle transitions: we can't touch the 237 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted 238 * Firmware might be using it. 239 */ 240 mutex_lock(&pmu->mutex); 241 242 /* 243 * Power domain clocks: Per Rockchip, we *must* keep certain clocks 244 * enabled for the duration of power-domain transitions. Most 245 * transitions are handled by this driver, but some cases (in 246 * particular, DRAM DVFS / memory-controller idle) must be handled by 247 * firmware. Firmware can handle most clock management via a special 248 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this 249 * doesn't handle PLLs. We can assist this transition by doing the 250 * clock management on behalf of firmware. 251 */ 252 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 253 genpd = pmu->genpd_data.domains[i]; 254 if (genpd) { 255 pd = to_rockchip_pd(genpd); 256 ret = clk_bulk_enable(pd->num_clks, pd->clks); 257 if (ret < 0) { 258 dev_err(pmu->dev, 259 "failed to enable clks for domain '%s': %d\n", 260 genpd->name, ret); 261 goto err; 262 } 263 } 264 } 265 266 return 0; 267 268 err: 269 for (i = i - 1; i >= 0; i--) { 270 genpd = pmu->genpd_data.domains[i]; 271 if (genpd) { 272 pd = to_rockchip_pd(genpd); 273 clk_bulk_disable(pd->num_clks, pd->clks); 274 } 275 } 276 mutex_unlock(&pmu->mutex); 277 mutex_unlock(&dmc_pmu_mutex); 278 279 return ret; 280 } 281 EXPORT_SYMBOL_GPL(rockchip_pmu_block); 282 283 /* Unblock PMU transitions. */ 284 void rockchip_pmu_unblock(void) 285 { 286 struct rockchip_pmu *pmu; 287 struct generic_pm_domain *genpd; 288 struct rockchip_pm_domain *pd; 289 int i; 290 291 if (dmc_pmu) { 292 pmu = dmc_pmu; 293 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 294 genpd = pmu->genpd_data.domains[i]; 295 if (genpd) { 296 pd = to_rockchip_pd(genpd); 297 clk_bulk_disable(pd->num_clks, pd->clks); 298 } 299 } 300 301 mutex_unlock(&pmu->mutex); 302 } 303 304 mutex_unlock(&dmc_pmu_mutex); 305 } 306 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock); 307 308 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup) \ 309 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup) 310 311 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd) 312 { 313 struct rockchip_pmu *pmu = pd->pmu; 314 const struct rockchip_domain_info *pd_info = pd->info; 315 unsigned int val; 316 317 regmap_read(pmu->regmap, pmu->info->idle_offset, &val); 318 return (val & pd_info->idle_mask) == pd_info->idle_mask; 319 } 320 321 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu) 322 { 323 unsigned int val; 324 325 regmap_read(pmu->regmap, pmu->info->ack_offset, &val); 326 return val; 327 } 328 329 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate) 330 { 331 const struct rockchip_domain_info *pd_info = pd->info; 332 struct rockchip_pmu *pmu = pd->pmu; 333 unsigned int val; 334 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16; 335 336 if (!pd_info->clk_ungate_mask) 337 return 0; 338 339 if (!pmu->info->clk_ungate_offset) 340 return 0; 341 342 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) : 343 clk_ungate_w_mask; 344 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val); 345 346 return 0; 347 } 348 349 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, 350 bool idle) 351 { 352 const struct rockchip_domain_info *pd_info = pd->info; 353 struct generic_pm_domain *genpd = &pd->genpd; 354 struct rockchip_pmu *pmu = pd->pmu; 355 u32 pd_req_offset = pd_info->req_offset; 356 unsigned int target_ack; 357 unsigned int val; 358 bool is_idle; 359 int ret; 360 361 if (pd_info->req_mask == 0) 362 return 0; 363 else if (pd_info->req_w_mask) 364 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset, 365 idle ? (pd_info->req_mask | pd_info->req_w_mask) : 366 pd_info->req_w_mask); 367 else 368 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset, 369 pd_info->req_mask, idle ? -1U : 0); 370 371 wmb(); 372 373 /* Wait util idle_ack = 1 */ 374 target_ack = idle ? pd_info->ack_mask : 0; 375 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val, 376 (val & pd_info->ack_mask) == target_ack, 377 0, 10000); 378 if (ret) { 379 dev_err(pmu->dev, 380 "failed to get ack on domain '%s', val=0x%x\n", 381 genpd->name, val); 382 return ret; 383 } 384 385 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd, 386 is_idle, is_idle == idle, 0, 10000); 387 if (ret) { 388 dev_err(pmu->dev, 389 "failed to set idle on domain '%s', val=%d\n", 390 genpd->name, is_idle); 391 return ret; 392 } 393 394 return 0; 395 } 396 397 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) 398 { 399 int i; 400 401 for (i = 0; i < pd->num_qos; i++) { 402 regmap_read(pd->qos_regmap[i], 403 QOS_PRIORITY, 404 &pd->qos_save_regs[0][i]); 405 regmap_read(pd->qos_regmap[i], 406 QOS_MODE, 407 &pd->qos_save_regs[1][i]); 408 regmap_read(pd->qos_regmap[i], 409 QOS_BANDWIDTH, 410 &pd->qos_save_regs[2][i]); 411 regmap_read(pd->qos_regmap[i], 412 QOS_SATURATION, 413 &pd->qos_save_regs[3][i]); 414 regmap_read(pd->qos_regmap[i], 415 QOS_EXTCONTROL, 416 &pd->qos_save_regs[4][i]); 417 } 418 return 0; 419 } 420 421 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd) 422 { 423 int i; 424 425 for (i = 0; i < pd->num_qos; i++) { 426 regmap_write(pd->qos_regmap[i], 427 QOS_PRIORITY, 428 pd->qos_save_regs[0][i]); 429 regmap_write(pd->qos_regmap[i], 430 QOS_MODE, 431 pd->qos_save_regs[1][i]); 432 regmap_write(pd->qos_regmap[i], 433 QOS_BANDWIDTH, 434 pd->qos_save_regs[2][i]); 435 regmap_write(pd->qos_regmap[i], 436 QOS_SATURATION, 437 pd->qos_save_regs[3][i]); 438 regmap_write(pd->qos_regmap[i], 439 QOS_EXTCONTROL, 440 pd->qos_save_regs[4][i]); 441 } 442 443 return 0; 444 } 445 446 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd) 447 { 448 struct rockchip_pmu *pmu = pd->pmu; 449 unsigned int val; 450 451 if (pd->info->repair_status_mask) { 452 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val); 453 /* 1'b1: power on, 1'b0: power off */ 454 return val & pd->info->repair_status_mask; 455 } 456 457 /* check idle status for idle-only domains */ 458 if (pd->info->status_mask == 0) 459 return !rockchip_pmu_domain_is_idle(pd); 460 461 regmap_read(pmu->regmap, pmu->info->status_offset, &val); 462 463 /* 1'b0: power on, 1'b1: power off */ 464 return !(val & pd->info->status_mask); 465 } 466 467 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd) 468 { 469 struct rockchip_pmu *pmu = pd->pmu; 470 unsigned int val; 471 472 regmap_read(pmu->regmap, 473 pmu->info->mem_status_offset + pd->info->mem_offset, &val); 474 475 /* 1'b0: power on, 1'b1: power off */ 476 return !(val & pd->info->mem_status_mask); 477 } 478 479 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd) 480 { 481 struct rockchip_pmu *pmu = pd->pmu; 482 unsigned int val; 483 484 regmap_read(pmu->regmap, 485 pmu->info->chain_status_offset + pd->info->mem_offset, &val); 486 487 /* 1'b1: power on, 1'b0: power off */ 488 return val & pd->info->mem_status_mask; 489 } 490 491 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd) 492 { 493 struct rockchip_pmu *pmu = pd->pmu; 494 struct generic_pm_domain *genpd = &pd->genpd; 495 bool is_on; 496 int ret = 0; 497 498 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on, 499 is_on == true, 0, 10000); 500 if (ret) { 501 dev_err(pmu->dev, 502 "failed to get chain status '%s', target_on=1, val=%d\n", 503 genpd->name, is_on); 504 goto error; 505 } 506 507 udelay(20); 508 509 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, 510 (pd->info->pwr_mask | pd->info->pwr_w_mask)); 511 wmb(); 512 513 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, 514 is_on == false, 0, 10000); 515 if (ret) { 516 dev_err(pmu->dev, 517 "failed to get mem status '%s', target_on=0, val=%d\n", 518 genpd->name, is_on); 519 goto error; 520 } 521 522 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset, 523 pd->info->pwr_w_mask); 524 wmb(); 525 526 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on, 527 is_on == true, 0, 10000); 528 if (ret) { 529 dev_err(pmu->dev, 530 "failed to get mem status '%s', target_on=1, val=%d\n", 531 genpd->name, is_on); 532 } 533 534 error: 535 return ret; 536 } 537 538 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd, 539 bool on) 540 { 541 struct rockchip_pmu *pmu = pd->pmu; 542 struct generic_pm_domain *genpd = &pd->genpd; 543 u32 pd_pwr_offset = pd->info->pwr_offset; 544 bool is_on, is_mem_on = false; 545 struct arm_smccc_res res; 546 int ret; 547 548 if (pd->info->pwr_mask == 0) 549 return 0; 550 551 if (on && pd->info->mem_status_mask) 552 is_mem_on = rockchip_pmu_domain_is_mem_on(pd); 553 554 if (pd->info->pwr_w_mask) 555 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, 556 on ? pd->info->pwr_w_mask : 557 (pd->info->pwr_mask | pd->info->pwr_w_mask)); 558 else 559 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset, 560 pd->info->pwr_mask, on ? 0 : -1U); 561 562 wmb(); 563 564 if (is_mem_on) { 565 ret = rockchip_pmu_domain_mem_reset(pd); 566 if (ret) 567 return ret; 568 } 569 570 571 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on, 572 is_on == on, 0, 10000); 573 if (ret) { 574 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n", 575 genpd->name, on ? "on" : "off", is_on); 576 return ret; 577 } 578 579 /* Inform firmware to keep this pd on or off */ 580 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE) 581 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG, 582 pmu->info->pwr_offset + pd_pwr_offset, 583 pd->info->pwr_mask, on, 0, 0, 0, &res); 584 585 return 0; 586 } 587 588 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on) 589 { 590 struct rockchip_pmu *pmu = pd->pmu; 591 int ret; 592 593 guard(mutex)(&pmu->mutex); 594 595 if (rockchip_pmu_domain_is_on(pd) == power_on) 596 return 0; 597 598 ret = clk_bulk_enable(pd->num_clks, pd->clks); 599 if (ret < 0) { 600 dev_err(pmu->dev, "failed to enable clocks\n"); 601 return ret; 602 } 603 604 rockchip_pmu_ungate_clk(pd, true); 605 606 if (!power_on) { 607 rockchip_pmu_save_qos(pd); 608 609 /* if powering down, idle request to NIU first */ 610 rockchip_pmu_set_idle_request(pd, true); 611 } 612 613 ret = rockchip_do_pmu_set_power_domain(pd, power_on); 614 if (ret < 0) { 615 clk_bulk_disable(pd->num_clks, pd->clks); 616 return ret; 617 } 618 619 if (power_on) { 620 /* if powering up, leave idle mode */ 621 rockchip_pmu_set_idle_request(pd, false); 622 623 rockchip_pmu_restore_qos(pd); 624 } 625 626 rockchip_pmu_ungate_clk(pd, false); 627 clk_bulk_disable(pd->num_clks, pd->clks); 628 629 return 0; 630 } 631 632 static int rockchip_pd_power_on(struct generic_pm_domain *domain) 633 { 634 struct rockchip_pm_domain *pd = to_rockchip_pd(domain); 635 636 return rockchip_pd_power(pd, true); 637 } 638 639 static int rockchip_pd_power_off(struct generic_pm_domain *domain) 640 { 641 struct rockchip_pm_domain *pd = to_rockchip_pd(domain); 642 643 return rockchip_pd_power(pd, false); 644 } 645 646 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd, 647 struct device *dev) 648 { 649 struct clk *clk; 650 int i; 651 int error; 652 653 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name); 654 655 error = pm_clk_create(dev); 656 if (error) { 657 dev_err(dev, "pm_clk_create failed %d\n", error); 658 return error; 659 } 660 661 i = 0; 662 while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) { 663 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk); 664 error = pm_clk_add_clk(dev, clk); 665 if (error) { 666 dev_err(dev, "pm_clk_add_clk failed %d\n", error); 667 clk_put(clk); 668 pm_clk_destroy(dev); 669 return error; 670 } 671 } 672 673 return 0; 674 } 675 676 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd, 677 struct device *dev) 678 { 679 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name); 680 681 pm_clk_destroy(dev); 682 } 683 684 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu, 685 struct device_node *node) 686 { 687 const struct rockchip_domain_info *pd_info; 688 struct rockchip_pm_domain *pd; 689 struct device_node *qos_node; 690 int i, j; 691 u32 id; 692 int error; 693 694 error = of_property_read_u32(node, "reg", &id); 695 if (error) { 696 dev_err(pmu->dev, 697 "%pOFn: failed to retrieve domain id (reg): %d\n", 698 node, error); 699 return -EINVAL; 700 } 701 702 if (id >= pmu->info->num_domains) { 703 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n", 704 node, id); 705 return -EINVAL; 706 } 707 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */ 708 if (pmu->genpd_data.domains[id]) 709 return 0; 710 711 pd_info = &pmu->info->domain_info[id]; 712 if (!pd_info) { 713 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n", 714 node, id); 715 return -EINVAL; 716 } 717 718 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL); 719 if (!pd) 720 return -ENOMEM; 721 722 pd->info = pd_info; 723 pd->pmu = pmu; 724 725 pd->num_clks = of_clk_get_parent_count(node); 726 if (pd->num_clks > 0) { 727 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks, 728 sizeof(*pd->clks), GFP_KERNEL); 729 if (!pd->clks) 730 return -ENOMEM; 731 } else { 732 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n", 733 node, pd->num_clks); 734 pd->num_clks = 0; 735 } 736 737 for (i = 0; i < pd->num_clks; i++) { 738 pd->clks[i].clk = of_clk_get(node, i); 739 if (IS_ERR(pd->clks[i].clk)) { 740 error = PTR_ERR(pd->clks[i].clk); 741 dev_err(pmu->dev, 742 "%pOFn: failed to get clk at index %d: %d\n", 743 node, i, error); 744 return error; 745 } 746 } 747 748 error = clk_bulk_prepare(pd->num_clks, pd->clks); 749 if (error) 750 goto err_put_clocks; 751 752 pd->num_qos = of_count_phandle_with_args(node, "pm_qos", 753 NULL); 754 755 if (pd->num_qos > 0) { 756 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos, 757 sizeof(*pd->qos_regmap), 758 GFP_KERNEL); 759 if (!pd->qos_regmap) { 760 error = -ENOMEM; 761 goto err_unprepare_clocks; 762 } 763 764 for (j = 0; j < MAX_QOS_REGS_NUM; j++) { 765 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev, 766 pd->num_qos, 767 sizeof(u32), 768 GFP_KERNEL); 769 if (!pd->qos_save_regs[j]) { 770 error = -ENOMEM; 771 goto err_unprepare_clocks; 772 } 773 } 774 775 for (j = 0; j < pd->num_qos; j++) { 776 qos_node = of_parse_phandle(node, "pm_qos", j); 777 if (!qos_node) { 778 error = -ENODEV; 779 goto err_unprepare_clocks; 780 } 781 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node); 782 of_node_put(qos_node); 783 if (IS_ERR(pd->qos_regmap[j])) { 784 error = -ENODEV; 785 goto err_unprepare_clocks; 786 } 787 } 788 } 789 790 if (pd->info->name) 791 pd->genpd.name = pd->info->name; 792 else 793 pd->genpd.name = kbasename(node->full_name); 794 pd->genpd.power_off = rockchip_pd_power_off; 795 pd->genpd.power_on = rockchip_pd_power_on; 796 pd->genpd.attach_dev = rockchip_pd_attach_dev; 797 pd->genpd.detach_dev = rockchip_pd_detach_dev; 798 pd->genpd.flags = GENPD_FLAG_PM_CLK; 799 if (pd_info->active_wakeup) 800 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; 801 pm_genpd_init(&pd->genpd, NULL, 802 !rockchip_pmu_domain_is_on(pd) || 803 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd))); 804 805 pmu->genpd_data.domains[id] = &pd->genpd; 806 return 0; 807 808 err_unprepare_clocks: 809 clk_bulk_unprepare(pd->num_clks, pd->clks); 810 err_put_clocks: 811 clk_bulk_put(pd->num_clks, pd->clks); 812 return error; 813 } 814 815 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd) 816 { 817 int ret; 818 819 /* 820 * We're in the error cleanup already, so we only complain, 821 * but won't emit another error on top of the original one. 822 */ 823 ret = pm_genpd_remove(&pd->genpd); 824 if (ret < 0) 825 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n", 826 pd->genpd.name, ret); 827 828 clk_bulk_unprepare(pd->num_clks, pd->clks); 829 clk_bulk_put(pd->num_clks, pd->clks); 830 831 /* protect the zeroing of pm->num_clks */ 832 mutex_lock(&pd->pmu->mutex); 833 pd->num_clks = 0; 834 mutex_unlock(&pd->pmu->mutex); 835 836 /* devm will free our memory */ 837 } 838 839 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu) 840 { 841 struct generic_pm_domain *genpd; 842 struct rockchip_pm_domain *pd; 843 int i; 844 845 for (i = 0; i < pmu->genpd_data.num_domains; i++) { 846 genpd = pmu->genpd_data.domains[i]; 847 if (genpd) { 848 pd = to_rockchip_pd(genpd); 849 rockchip_pm_remove_one_domain(pd); 850 } 851 } 852 853 /* devm will free our memory */ 854 } 855 856 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu, 857 u32 domain_reg_offset, 858 unsigned int count) 859 { 860 /* First configure domain power down transition count ... */ 861 regmap_write(pmu->regmap, domain_reg_offset, count); 862 /* ... and then power up count. */ 863 regmap_write(pmu->regmap, domain_reg_offset + 4, count); 864 } 865 866 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu, 867 struct device_node *parent) 868 { 869 struct generic_pm_domain *child_domain, *parent_domain; 870 int error; 871 872 for_each_child_of_node_scoped(parent, np) { 873 u32 idx; 874 875 error = of_property_read_u32(parent, "reg", &idx); 876 if (error) { 877 dev_err(pmu->dev, 878 "%pOFn: failed to retrieve domain id (reg): %d\n", 879 parent, error); 880 return error; 881 } 882 parent_domain = pmu->genpd_data.domains[idx]; 883 884 error = rockchip_pm_add_one_domain(pmu, np); 885 if (error) { 886 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n", 887 np, error); 888 return error; 889 } 890 891 error = of_property_read_u32(np, "reg", &idx); 892 if (error) { 893 dev_err(pmu->dev, 894 "%pOFn: failed to retrieve domain id (reg): %d\n", 895 np, error); 896 return error; 897 } 898 child_domain = pmu->genpd_data.domains[idx]; 899 900 error = pm_genpd_add_subdomain(parent_domain, child_domain); 901 if (error) { 902 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n", 903 parent_domain->name, child_domain->name, error); 904 return error; 905 } else { 906 dev_dbg(pmu->dev, "%s add subdomain: %s\n", 907 parent_domain->name, child_domain->name); 908 } 909 910 rockchip_pm_add_subdomain(pmu, np); 911 } 912 913 return 0; 914 } 915 916 static int rockchip_pm_domain_probe(struct platform_device *pdev) 917 { 918 struct device *dev = &pdev->dev; 919 struct device_node *np = dev->of_node; 920 struct device *parent; 921 struct rockchip_pmu *pmu; 922 const struct rockchip_pmu_info *pmu_info; 923 int error; 924 925 if (!np) { 926 dev_err(dev, "device tree node not found\n"); 927 return -ENODEV; 928 } 929 930 pmu_info = device_get_match_data(dev); 931 932 pmu = devm_kzalloc(dev, 933 struct_size(pmu, domains, pmu_info->num_domains), 934 GFP_KERNEL); 935 if (!pmu) 936 return -ENOMEM; 937 938 pmu->dev = &pdev->dev; 939 mutex_init(&pmu->mutex); 940 941 pmu->info = pmu_info; 942 943 pmu->genpd_data.domains = pmu->domains; 944 pmu->genpd_data.num_domains = pmu_info->num_domains; 945 946 parent = dev->parent; 947 if (!parent) { 948 dev_err(dev, "no parent for syscon devices\n"); 949 return -ENODEV; 950 } 951 952 pmu->regmap = syscon_node_to_regmap(parent->of_node); 953 if (IS_ERR(pmu->regmap)) { 954 dev_err(dev, "no regmap available\n"); 955 return PTR_ERR(pmu->regmap); 956 } 957 958 /* 959 * Configure power up and down transition delays for CORE 960 * and GPU domains. 961 */ 962 if (pmu_info->core_power_transition_time) 963 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset, 964 pmu_info->core_power_transition_time); 965 if (pmu_info->gpu_pwrcnt_offset) 966 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset, 967 pmu_info->gpu_power_transition_time); 968 969 error = -ENODEV; 970 971 /* 972 * Prevent any rockchip_pmu_block() from racing with the remainder of 973 * setup (clocks, register initialization). 974 */ 975 guard(mutex)(&dmc_pmu_mutex); 976 977 for_each_available_child_of_node_scoped(np, node) { 978 error = rockchip_pm_add_one_domain(pmu, node); 979 if (error) { 980 dev_err(dev, "failed to handle node %pOFn: %d\n", 981 node, error); 982 goto err_out; 983 } 984 985 error = rockchip_pm_add_subdomain(pmu, node); 986 if (error < 0) { 987 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n", 988 node, error); 989 goto err_out; 990 } 991 } 992 993 if (error) { 994 dev_dbg(dev, "no power domains defined\n"); 995 goto err_out; 996 } 997 998 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data); 999 if (error) { 1000 dev_err(dev, "failed to add provider: %d\n", error); 1001 goto err_out; 1002 } 1003 1004 /* We only expect one PMU. */ 1005 if (!WARN_ON_ONCE(dmc_pmu)) 1006 dmc_pmu = pmu; 1007 1008 return 0; 1009 1010 err_out: 1011 rockchip_pm_domain_cleanup(pmu); 1012 return error; 1013 } 1014 1015 static const struct rockchip_domain_info px30_pm_domains[] = { 1016 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false), 1017 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false), 1018 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false), 1019 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false), 1020 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false), 1021 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false), 1022 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false), 1023 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false), 1024 }; 1025 1026 static const struct rockchip_domain_info rv1126_pm_domains[] = { 1027 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false), 1028 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false), 1029 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false), 1030 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false), 1031 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false), 1032 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false), 1033 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false), 1034 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false), 1035 }; 1036 1037 static const struct rockchip_domain_info rk3036_pm_domains[] = { 1038 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true), 1039 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false), 1040 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false), 1041 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false), 1042 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false), 1043 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false), 1044 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false), 1045 }; 1046 1047 static const struct rockchip_domain_info rk3066_pm_domains[] = { 1048 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), 1049 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), 1050 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), 1051 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), 1052 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false), 1053 }; 1054 1055 static const struct rockchip_domain_info rk3128_pm_domains[] = { 1056 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false), 1057 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true), 1058 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false), 1059 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false), 1060 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false), 1061 }; 1062 1063 static const struct rockchip_domain_info rk3188_pm_domains[] = { 1064 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false), 1065 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false), 1066 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false), 1067 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false), 1068 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false), 1069 }; 1070 1071 static const struct rockchip_domain_info rk3228_pm_domains[] = { 1072 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true), 1073 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true), 1074 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true), 1075 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true), 1076 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false), 1077 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false), 1078 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false), 1079 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false), 1080 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false), 1081 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true), 1082 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false), 1083 }; 1084 1085 static const struct rockchip_domain_info rk3288_pm_domains[] = { 1086 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false), 1087 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false), 1088 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false), 1089 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false), 1090 }; 1091 1092 static const struct rockchip_domain_info rk3328_pm_domains[] = { 1093 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false), 1094 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false), 1095 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true), 1096 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true), 1097 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true), 1098 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false), 1099 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false), 1100 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false), 1101 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false), 1102 }; 1103 1104 static const struct rockchip_domain_info rk3366_pm_domains[] = { 1105 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true), 1106 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false), 1107 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false), 1108 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false), 1109 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false), 1110 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false), 1111 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false), 1112 }; 1113 1114 static const struct rockchip_domain_info rk3368_pm_domains[] = { 1115 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true), 1116 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false), 1117 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false), 1118 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false), 1119 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false), 1120 }; 1121 1122 static const struct rockchip_domain_info rk3399_pm_domains[] = { 1123 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false), 1124 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false), 1125 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true), 1126 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true), 1127 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true), 1128 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true), 1129 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true), 1130 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true), 1131 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false), 1132 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false), 1133 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false), 1134 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false), 1135 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false), 1136 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false), 1137 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false), 1138 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false), 1139 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false), 1140 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false), 1141 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false), 1142 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false), 1143 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true), 1144 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true), 1145 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true), 1146 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false), 1147 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true), 1148 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true), 1149 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true), 1150 }; 1151 1152 static const struct rockchip_domain_info rk3568_pm_domains[] = { 1153 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false), 1154 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false), 1155 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false), 1156 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false), 1157 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false), 1158 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false), 1159 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false), 1160 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false), 1161 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false), 1162 }; 1163 1164 static const struct rockchip_domain_info rk3576_pm_domains[] = { 1165 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false), 1166 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false), 1167 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false), 1168 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false), 1169 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false), 1170 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false), 1171 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false), 1172 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false), 1173 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false), 1174 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true), 1175 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false), 1176 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false), 1177 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false), 1178 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false), 1179 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false), 1180 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false), 1181 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false), 1182 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false), 1183 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false), 1184 }; 1185 1186 static const struct rockchip_domain_info rk3588_pm_domains[] = { 1187 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false), 1188 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false), 1189 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false), 1190 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false), 1191 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false), 1192 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false), 1193 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false), 1194 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false), 1195 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false), 1196 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false), 1197 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false), 1198 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false), 1199 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false), 1200 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false), 1201 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false), 1202 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false), 1203 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false), 1204 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false), 1205 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false), 1206 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false), 1207 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false), 1208 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false), 1209 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false), 1210 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true), 1211 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false), 1212 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false), 1213 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false), 1214 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true), 1215 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false), 1216 }; 1217 1218 static const struct rockchip_pmu_info px30_pmu = { 1219 .pwr_offset = 0x18, 1220 .status_offset = 0x20, 1221 .req_offset = 0x64, 1222 .idle_offset = 0x6c, 1223 .ack_offset = 0x6c, 1224 1225 .num_domains = ARRAY_SIZE(px30_pm_domains), 1226 .domain_info = px30_pm_domains, 1227 }; 1228 1229 static const struct rockchip_pmu_info rk3036_pmu = { 1230 .req_offset = 0x148, 1231 .idle_offset = 0x14c, 1232 .ack_offset = 0x14c, 1233 1234 .num_domains = ARRAY_SIZE(rk3036_pm_domains), 1235 .domain_info = rk3036_pm_domains, 1236 }; 1237 1238 static const struct rockchip_pmu_info rk3066_pmu = { 1239 .pwr_offset = 0x08, 1240 .status_offset = 0x0c, 1241 .req_offset = 0x38, /* PMU_MISC_CON1 */ 1242 .idle_offset = 0x0c, 1243 .ack_offset = 0x0c, 1244 1245 .num_domains = ARRAY_SIZE(rk3066_pm_domains), 1246 .domain_info = rk3066_pm_domains, 1247 }; 1248 1249 static const struct rockchip_pmu_info rk3128_pmu = { 1250 .pwr_offset = 0x04, 1251 .status_offset = 0x08, 1252 .req_offset = 0x0c, 1253 .idle_offset = 0x10, 1254 .ack_offset = 0x10, 1255 1256 .num_domains = ARRAY_SIZE(rk3128_pm_domains), 1257 .domain_info = rk3128_pm_domains, 1258 }; 1259 1260 static const struct rockchip_pmu_info rk3188_pmu = { 1261 .pwr_offset = 0x08, 1262 .status_offset = 0x0c, 1263 .req_offset = 0x38, /* PMU_MISC_CON1 */ 1264 .idle_offset = 0x0c, 1265 .ack_offset = 0x0c, 1266 1267 .num_domains = ARRAY_SIZE(rk3188_pm_domains), 1268 .domain_info = rk3188_pm_domains, 1269 }; 1270 1271 static const struct rockchip_pmu_info rk3228_pmu = { 1272 .req_offset = 0x40c, 1273 .idle_offset = 0x488, 1274 .ack_offset = 0x488, 1275 1276 .num_domains = ARRAY_SIZE(rk3228_pm_domains), 1277 .domain_info = rk3228_pm_domains, 1278 }; 1279 1280 static const struct rockchip_pmu_info rk3288_pmu = { 1281 .pwr_offset = 0x08, 1282 .status_offset = 0x0c, 1283 .req_offset = 0x10, 1284 .idle_offset = 0x14, 1285 .ack_offset = 0x14, 1286 1287 .core_pwrcnt_offset = 0x34, 1288 .gpu_pwrcnt_offset = 0x3c, 1289 1290 .core_power_transition_time = 24, /* 1us */ 1291 .gpu_power_transition_time = 24, /* 1us */ 1292 1293 .num_domains = ARRAY_SIZE(rk3288_pm_domains), 1294 .domain_info = rk3288_pm_domains, 1295 }; 1296 1297 static const struct rockchip_pmu_info rk3328_pmu = { 1298 .req_offset = 0x414, 1299 .idle_offset = 0x484, 1300 .ack_offset = 0x484, 1301 1302 .num_domains = ARRAY_SIZE(rk3328_pm_domains), 1303 .domain_info = rk3328_pm_domains, 1304 }; 1305 1306 static const struct rockchip_pmu_info rk3366_pmu = { 1307 .pwr_offset = 0x0c, 1308 .status_offset = 0x10, 1309 .req_offset = 0x3c, 1310 .idle_offset = 0x40, 1311 .ack_offset = 0x40, 1312 1313 .core_pwrcnt_offset = 0x48, 1314 .gpu_pwrcnt_offset = 0x50, 1315 1316 .core_power_transition_time = 24, 1317 .gpu_power_transition_time = 24, 1318 1319 .num_domains = ARRAY_SIZE(rk3366_pm_domains), 1320 .domain_info = rk3366_pm_domains, 1321 }; 1322 1323 static const struct rockchip_pmu_info rk3368_pmu = { 1324 .pwr_offset = 0x0c, 1325 .status_offset = 0x10, 1326 .req_offset = 0x3c, 1327 .idle_offset = 0x40, 1328 .ack_offset = 0x40, 1329 1330 .core_pwrcnt_offset = 0x48, 1331 .gpu_pwrcnt_offset = 0x50, 1332 1333 .core_power_transition_time = 24, 1334 .gpu_power_transition_time = 24, 1335 1336 .num_domains = ARRAY_SIZE(rk3368_pm_domains), 1337 .domain_info = rk3368_pm_domains, 1338 }; 1339 1340 static const struct rockchip_pmu_info rk3399_pmu = { 1341 .pwr_offset = 0x14, 1342 .status_offset = 0x18, 1343 .req_offset = 0x60, 1344 .idle_offset = 0x64, 1345 .ack_offset = 0x68, 1346 1347 /* ARM Trusted Firmware manages power transition times */ 1348 1349 .num_domains = ARRAY_SIZE(rk3399_pm_domains), 1350 .domain_info = rk3399_pm_domains, 1351 }; 1352 1353 static const struct rockchip_pmu_info rk3568_pmu = { 1354 .pwr_offset = 0xa0, 1355 .status_offset = 0x98, 1356 .req_offset = 0x50, 1357 .idle_offset = 0x68, 1358 .ack_offset = 0x60, 1359 1360 .num_domains = ARRAY_SIZE(rk3568_pm_domains), 1361 .domain_info = rk3568_pm_domains, 1362 }; 1363 1364 static const struct rockchip_pmu_info rk3576_pmu = { 1365 .pwr_offset = 0x210, 1366 .status_offset = 0x230, 1367 .chain_status_offset = 0x248, 1368 .mem_status_offset = 0x250, 1369 .mem_pwr_offset = 0x300, 1370 .req_offset = 0x110, 1371 .idle_offset = 0x128, 1372 .ack_offset = 0x120, 1373 .repair_status_offset = 0x570, 1374 .clk_ungate_offset = 0x140, 1375 1376 .num_domains = ARRAY_SIZE(rk3576_pm_domains), 1377 .domain_info = rk3576_pm_domains, 1378 }; 1379 1380 static const struct rockchip_pmu_info rk3588_pmu = { 1381 .pwr_offset = 0x14c, 1382 .status_offset = 0x180, 1383 .req_offset = 0x10c, 1384 .idle_offset = 0x120, 1385 .ack_offset = 0x118, 1386 .mem_pwr_offset = 0x1a0, 1387 .chain_status_offset = 0x1f0, 1388 .mem_status_offset = 0x1f8, 1389 .repair_status_offset = 0x290, 1390 1391 .num_domains = ARRAY_SIZE(rk3588_pm_domains), 1392 .domain_info = rk3588_pm_domains, 1393 }; 1394 1395 static const struct rockchip_pmu_info rv1126_pmu = { 1396 .pwr_offset = 0x110, 1397 .status_offset = 0x108, 1398 .req_offset = 0xc0, 1399 .idle_offset = 0xd8, 1400 .ack_offset = 0xd0, 1401 1402 .num_domains = ARRAY_SIZE(rv1126_pm_domains), 1403 .domain_info = rv1126_pm_domains, 1404 }; 1405 1406 static const struct of_device_id rockchip_pm_domain_dt_match[] = { 1407 { 1408 .compatible = "rockchip,px30-power-controller", 1409 .data = (void *)&px30_pmu, 1410 }, 1411 { 1412 .compatible = "rockchip,rk3036-power-controller", 1413 .data = (void *)&rk3036_pmu, 1414 }, 1415 { 1416 .compatible = "rockchip,rk3066-power-controller", 1417 .data = (void *)&rk3066_pmu, 1418 }, 1419 { 1420 .compatible = "rockchip,rk3128-power-controller", 1421 .data = (void *)&rk3128_pmu, 1422 }, 1423 { 1424 .compatible = "rockchip,rk3188-power-controller", 1425 .data = (void *)&rk3188_pmu, 1426 }, 1427 { 1428 .compatible = "rockchip,rk3228-power-controller", 1429 .data = (void *)&rk3228_pmu, 1430 }, 1431 { 1432 .compatible = "rockchip,rk3288-power-controller", 1433 .data = (void *)&rk3288_pmu, 1434 }, 1435 { 1436 .compatible = "rockchip,rk3328-power-controller", 1437 .data = (void *)&rk3328_pmu, 1438 }, 1439 { 1440 .compatible = "rockchip,rk3366-power-controller", 1441 .data = (void *)&rk3366_pmu, 1442 }, 1443 { 1444 .compatible = "rockchip,rk3368-power-controller", 1445 .data = (void *)&rk3368_pmu, 1446 }, 1447 { 1448 .compatible = "rockchip,rk3399-power-controller", 1449 .data = (void *)&rk3399_pmu, 1450 }, 1451 { 1452 .compatible = "rockchip,rk3568-power-controller", 1453 .data = (void *)&rk3568_pmu, 1454 }, 1455 { 1456 .compatible = "rockchip,rk3576-power-controller", 1457 .data = (void *)&rk3576_pmu, 1458 }, 1459 { 1460 .compatible = "rockchip,rk3588-power-controller", 1461 .data = (void *)&rk3588_pmu, 1462 }, 1463 { 1464 .compatible = "rockchip,rv1126-power-controller", 1465 .data = (void *)&rv1126_pmu, 1466 }, 1467 { /* sentinel */ }, 1468 }; 1469 1470 static struct platform_driver rockchip_pm_domain_driver = { 1471 .probe = rockchip_pm_domain_probe, 1472 .driver = { 1473 .name = "rockchip-pm-domain", 1474 .of_match_table = rockchip_pm_domain_dt_match, 1475 /* 1476 * We can't forcibly eject devices from the power 1477 * domain, so we can't really remove power domains 1478 * once they were added. 1479 */ 1480 .suppress_bind_attrs = true, 1481 }, 1482 }; 1483 1484 static int __init rockchip_pm_domain_drv_register(void) 1485 { 1486 return platform_driver_register(&rockchip_pm_domain_driver); 1487 } 1488 postcore_initcall(rockchip_pm_domain_drv_register); 1489