1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H 5 6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) 7 #define MTK_SCPD_FWAIT_SRAM BIT(1) 8 #define MTK_SCPD_SRAM_ISO BIT(2) 9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) 10 #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) 11 /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ 12 #define MTK_SCPD_ALWAYS_ON BIT(5) 13 #define MTK_SCPD_EXT_BUCK_ISO BIT(6) 14 #define MTK_SCPD_HAS_INFRA_NAO BIT(7) 15 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) 16 17 #define SPM_VDE_PWR_CON 0x0210 18 #define SPM_MFG_PWR_CON 0x0214 19 #define SPM_VEN_PWR_CON 0x0230 20 #define SPM_ISP_PWR_CON 0x0238 21 #define SPM_DIS_PWR_CON 0x023c 22 #define SPM_CONN_PWR_CON 0x0280 23 #define SPM_VEN2_PWR_CON 0x0298 24 #define SPM_AUDIO_PWR_CON 0x029c 25 #define SPM_MFG_2D_PWR_CON 0x02c0 26 #define SPM_MFG_ASYNC_PWR_CON 0x02c4 27 #define SPM_USB_PWR_CON 0x02cc 28 29 #define SPM_PWR_STATUS 0x060c 30 #define SPM_PWR_STATUS_2ND 0x0610 31 32 #define PWR_STATUS_CONN BIT(1) 33 #define PWR_STATUS_DISP BIT(3) 34 #define PWR_STATUS_MFG BIT(4) 35 #define PWR_STATUS_ISP BIT(5) 36 #define PWR_STATUS_VDEC BIT(7) 37 #define PWR_STATUS_VENC_LT BIT(20) 38 #define PWR_STATUS_VENC BIT(21) 39 #define PWR_STATUS_MFG_2D BIT(22) 40 #define PWR_STATUS_MFG_ASYNC BIT(23) 41 #define PWR_STATUS_AUDIO BIT(24) 42 #define PWR_STATUS_USB BIT(25) 43 44 #define SPM_MAX_BUS_PROT_DATA 6 45 46 enum scpsys_bus_prot_flags { 47 BUS_PROT_REG_UPDATE = BIT(1), 48 BUS_PROT_IGNORE_CLR_ACK = BIT(2), 49 BUS_PROT_INVERTED = BIT(3), 50 BUS_PROT_COMPONENT_INFRA = BIT(4), 51 BUS_PROT_COMPONENT_SMI = BIT(5), 52 BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6), 53 }; 54 55 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ 56 .bus_prot_set_clr_mask = (_set_clr_mask), \ 57 .bus_prot_set = _set, \ 58 .bus_prot_clr = _clr, \ 59 .bus_prot_sta_mask = (_sta_mask), \ 60 .bus_prot_sta = _sta, \ 61 .flags = _flags \ 62 } 63 64 #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ 65 _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) 66 67 #define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ 68 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 69 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) 70 71 #define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ 72 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 73 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) 74 75 #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ 76 BUS_PROT_UPDATE(INFRA, _mask, \ 77 INFRA_TOPAXI_PROTECTEN, \ 78 INFRA_TOPAXI_PROTECTEN, \ 79 INFRA_TOPAXI_PROTECTSTA1) 80 81 struct scpsys_bus_prot_data { 82 u32 bus_prot_set_clr_mask; 83 u32 bus_prot_set; 84 u32 bus_prot_clr; 85 u32 bus_prot_sta_mask; 86 u32 bus_prot_sta; 87 u8 flags; 88 }; 89 90 /** 91 * struct scpsys_domain_data - scp domain data for power on/off flow 92 * @name: The name of the power domain. 93 * @sta_mask: The mask for power on/off status bit. 94 * @ctl_offs: The offset for main power control register. 95 * @sram_pdn_bits: The mask for sram power control bits. 96 * @sram_pdn_ack_bits: The mask for sram power control acked bits. 97 * @ext_buck_iso_offs: The offset for external buck isolation 98 * @ext_buck_iso_mask: The mask for external buck isolation 99 * @caps: The flag for active wake-up action. 100 * @bp_cfg: bus protection configuration for any subsystem 101 */ 102 struct scpsys_domain_data { 103 const char *name; 104 u32 sta_mask; 105 int ctl_offs; 106 u32 sram_pdn_bits; 107 u32 sram_pdn_ack_bits; 108 int ext_buck_iso_offs; 109 u32 ext_buck_iso_mask; 110 u8 caps; 111 const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; 112 int pwr_sta_offs; 113 int pwr_sta2nd_offs; 114 }; 115 116 struct scpsys_soc_data { 117 const struct scpsys_domain_data *domains_data; 118 int num_domains; 119 }; 120 121 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ 122