1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H 5 6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) 7 #define MTK_SCPD_FWAIT_SRAM BIT(1) 8 #define MTK_SCPD_SRAM_ISO BIT(2) 9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) 10 #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) 11 /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ 12 #define MTK_SCPD_ALWAYS_ON BIT(5) 13 #define MTK_SCPD_EXT_BUCK_ISO BIT(6) 14 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) 15 16 #define SPM_VDE_PWR_CON 0x0210 17 #define SPM_MFG_PWR_CON 0x0214 18 #define SPM_VEN_PWR_CON 0x0230 19 #define SPM_ISP_PWR_CON 0x0238 20 #define SPM_DIS_PWR_CON 0x023c 21 #define SPM_CONN_PWR_CON 0x0280 22 #define SPM_VEN2_PWR_CON 0x0298 23 #define SPM_AUDIO_PWR_CON 0x029c 24 #define SPM_MFG_2D_PWR_CON 0x02c0 25 #define SPM_MFG_ASYNC_PWR_CON 0x02c4 26 #define SPM_USB_PWR_CON 0x02cc 27 28 #define SPM_PWR_STATUS 0x060c 29 #define SPM_PWR_STATUS_2ND 0x0610 30 31 #define PWR_STATUS_CONN BIT(1) 32 #define PWR_STATUS_DISP BIT(3) 33 #define PWR_STATUS_MFG BIT(4) 34 #define PWR_STATUS_ISP BIT(5) 35 #define PWR_STATUS_VDEC BIT(7) 36 #define PWR_STATUS_VENC_LT BIT(20) 37 #define PWR_STATUS_VENC BIT(21) 38 #define PWR_STATUS_MFG_2D BIT(22) 39 #define PWR_STATUS_MFG_ASYNC BIT(23) 40 #define PWR_STATUS_AUDIO BIT(24) 41 #define PWR_STATUS_USB BIT(25) 42 43 #define SPM_MAX_BUS_PROT_DATA 6 44 45 enum scpsys_bus_prot_flags { 46 BUS_PROT_REG_UPDATE = BIT(1), 47 BUS_PROT_IGNORE_CLR_ACK = BIT(2), 48 }; 49 50 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ 51 .bus_prot_set_clr_mask = (_set_clr_mask), \ 52 .bus_prot_set = _set, \ 53 .bus_prot_clr = _clr, \ 54 .bus_prot_sta_mask = (_sta_mask), \ 55 .bus_prot_sta = _sta, \ 56 .flags = _flags \ 57 } 58 59 #define BUS_PROT_WR(_mask, _set, _clr, _sta) \ 60 _BUS_PROT(_mask, _set, _clr, _mask, _sta, 0) 61 62 #define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ 63 _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_IGNORE_CLR_ACK) 64 65 #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ 66 _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_REG_UPDATE) 67 68 #define BUS_PROT_UPDATE_TOPAXI(_mask) \ 69 BUS_PROT_UPDATE(_mask, \ 70 INFRA_TOPAXI_PROTECTEN, \ 71 INFRA_TOPAXI_PROTECTEN, \ 72 INFRA_TOPAXI_PROTECTSTA1) 73 74 struct scpsys_bus_prot_data { 75 u32 bus_prot_set_clr_mask; 76 u32 bus_prot_set; 77 u32 bus_prot_clr; 78 u32 bus_prot_sta_mask; 79 u32 bus_prot_sta; 80 u8 flags; 81 }; 82 83 /** 84 * struct scpsys_domain_data - scp domain data for power on/off flow 85 * @name: The name of the power domain. 86 * @sta_mask: The mask for power on/off status bit. 87 * @ctl_offs: The offset for main power control register. 88 * @sram_pdn_bits: The mask for sram power control bits. 89 * @sram_pdn_ack_bits: The mask for sram power control acked bits. 90 * @ext_buck_iso_offs: The offset for external buck isolation 91 * @ext_buck_iso_mask: The mask for external buck isolation 92 * @caps: The flag for active wake-up action. 93 * @bp_infracfg: bus protection for infracfg subsystem 94 * @bp_smi: bus protection for smi subsystem 95 */ 96 struct scpsys_domain_data { 97 const char *name; 98 u32 sta_mask; 99 int ctl_offs; 100 u32 sram_pdn_bits; 101 u32 sram_pdn_ack_bits; 102 int ext_buck_iso_offs; 103 u32 ext_buck_iso_mask; 104 u8 caps; 105 const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; 106 const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; 107 int pwr_sta_offs; 108 int pwr_sta2nd_offs; 109 }; 110 111 struct scpsys_soc_data { 112 const struct scpsys_domain_data *domains_data; 113 int num_domains; 114 }; 115 116 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ 117