1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H 5 6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) 7 #define MTK_SCPD_FWAIT_SRAM BIT(1) 8 #define MTK_SCPD_SRAM_ISO BIT(2) 9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) 10 #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) 11 /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ 12 #define MTK_SCPD_ALWAYS_ON BIT(5) 13 #define MTK_SCPD_EXT_BUCK_ISO BIT(6) 14 #define MTK_SCPD_HAS_INFRA_NAO BIT(7) 15 #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) 16 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) 17 18 #define SPM_VDE_PWR_CON 0x0210 19 #define SPM_MFG_PWR_CON 0x0214 20 #define SPM_VEN_PWR_CON 0x0230 21 #define SPM_ISP_PWR_CON 0x0238 22 #define SPM_DIS_PWR_CON 0x023c 23 #define SPM_CONN_PWR_CON 0x0280 24 #define SPM_MD1_PWR_CON 0x0284 25 #define SPM_VEN2_PWR_CON 0x0298 26 #define SPM_AUDIO_PWR_CON 0x029c 27 #define SPM_MFG_2D_PWR_CON 0x02c0 28 #define SPM_MFG_ASYNC_PWR_CON 0x02c4 29 #define SPM_USB_PWR_CON 0x02cc 30 31 #define SPM_PWR_STATUS 0x060c 32 #define SPM_PWR_STATUS_2ND 0x0610 33 34 #define PWR_STATUS_MD1 BIT(0) 35 #define PWR_STATUS_CONN BIT(1) 36 #define PWR_STATUS_DISP BIT(3) 37 #define PWR_STATUS_MFG BIT(4) 38 #define PWR_STATUS_ISP BIT(5) 39 #define PWR_STATUS_VDEC BIT(7) 40 #define PWR_STATUS_VENC_LT BIT(20) 41 #define PWR_STATUS_VENC BIT(21) 42 #define PWR_STATUS_MFG_2D BIT(22) 43 #define PWR_STATUS_MFG_ASYNC BIT(23) 44 #define PWR_STATUS_AUDIO BIT(24) 45 #define PWR_STATUS_USB BIT(25) 46 47 #define SPM_MAX_BUS_PROT_DATA 6 48 49 enum scpsys_bus_prot_flags { 50 BUS_PROT_REG_UPDATE = BIT(1), 51 BUS_PROT_IGNORE_CLR_ACK = BIT(2), 52 BUS_PROT_INVERTED = BIT(3), 53 BUS_PROT_COMPONENT_INFRA = BIT(4), 54 BUS_PROT_COMPONENT_SMI = BIT(5), 55 BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6), 56 }; 57 58 #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ 59 .bus_prot_set_clr_mask = (_set_clr_mask), \ 60 .bus_prot_set = _set, \ 61 .bus_prot_clr = _clr, \ 62 .bus_prot_sta_mask = (_sta_mask), \ 63 .bus_prot_sta = _sta, \ 64 .flags = _flags \ 65 } 66 67 #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ 68 _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) 69 70 #define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ 71 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 72 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) 73 74 #define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ 75 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 76 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) 77 78 #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ 79 BUS_PROT_UPDATE(INFRA, _mask, \ 80 INFRA_TOPAXI_PROTECTEN, \ 81 INFRA_TOPAXI_PROTECTEN, \ 82 INFRA_TOPAXI_PROTECTSTA1) 83 84 struct scpsys_bus_prot_data { 85 u32 bus_prot_set_clr_mask; 86 u32 bus_prot_set; 87 u32 bus_prot_clr; 88 u32 bus_prot_sta_mask; 89 u32 bus_prot_sta; 90 u8 flags; 91 }; 92 93 /** 94 * struct scpsys_domain_data - scp domain data for power on/off flow 95 * @name: The name of the power domain. 96 * @sta_mask: The mask for power on/off status bit. 97 * @ctl_offs: The offset for main power control register. 98 * @sram_pdn_bits: The mask for sram power control bits. 99 * @sram_pdn_ack_bits: The mask for sram power control acked bits. 100 * @ext_buck_iso_offs: The offset for external buck isolation 101 * @ext_buck_iso_mask: The mask for external buck isolation 102 * @caps: The flag for active wake-up action. 103 * @bp_cfg: bus protection configuration for any subsystem 104 */ 105 struct scpsys_domain_data { 106 const char *name; 107 u32 sta_mask; 108 int ctl_offs; 109 u32 sram_pdn_bits; 110 u32 sram_pdn_ack_bits; 111 int ext_buck_iso_offs; 112 u32 ext_buck_iso_mask; 113 u16 caps; 114 const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; 115 int pwr_sta_offs; 116 int pwr_sta2nd_offs; 117 }; 118 119 struct scpsys_soc_data { 120 const struct scpsys_domain_data *domains_data; 121 int num_domains; 122 }; 123 124 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ 125