1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H 5 6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) 7 #define MTK_SCPD_FWAIT_SRAM BIT(1) 8 #define MTK_SCPD_SRAM_ISO BIT(2) 9 #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) 10 #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) 11 /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ 12 #define MTK_SCPD_ALWAYS_ON BIT(5) 13 #define MTK_SCPD_EXT_BUCK_ISO BIT(6) 14 #define MTK_SCPD_HAS_INFRA_NAO BIT(7) 15 #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) 16 #define MTK_SCPD_SRAM_PDN_INVERTED BIT(9) 17 #define MTK_SCPD_MODEM_PWRSEQ BIT(10) 18 #define MTK_SCPD_SKIP_RESET_B BIT(11) 19 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) 20 21 #define SPM_VDE_PWR_CON 0x0210 22 #define SPM_MFG_PWR_CON 0x0214 23 #define SPM_VEN_PWR_CON 0x0230 24 #define SPM_ISP_PWR_CON 0x0238 25 #define SPM_DIS_PWR_CON 0x023c 26 #define SPM_CONN_PWR_CON 0x0280 27 #define SPM_MD1_PWR_CON 0x0284 28 #define SPM_VEN2_PWR_CON 0x0298 29 #define SPM_AUDIO_PWR_CON 0x029c 30 #define SPM_MFG_2D_PWR_CON 0x02c0 31 #define SPM_MFG_ASYNC_PWR_CON 0x02c4 32 #define SPM_USB_PWR_CON 0x02cc 33 34 #define SPM_PWR_STATUS 0x060c 35 #define SPM_PWR_STATUS_2ND 0x0610 36 37 #define PWR_STATUS_MD1 BIT(0) 38 #define PWR_STATUS_CONN BIT(1) 39 #define PWR_STATUS_DISP BIT(3) 40 #define PWR_STATUS_MFG BIT(4) 41 #define PWR_STATUS_ISP BIT(5) 42 #define PWR_STATUS_VDEC BIT(7) 43 #define PWR_STATUS_VENC_LT BIT(20) 44 #define PWR_STATUS_VENC BIT(21) 45 #define PWR_STATUS_MFG_2D BIT(22) 46 #define PWR_STATUS_MFG_ASYNC BIT(23) 47 #define PWR_STATUS_AUDIO BIT(24) 48 #define PWR_STATUS_USB BIT(25) 49 50 #define SPM_MAX_BUS_PROT_DATA 7 51 52 enum scpsys_bus_prot_flags { 53 BUS_PROT_REG_UPDATE = BIT(1), 54 BUS_PROT_IGNORE_CLR_ACK = BIT(2), 55 BUS_PROT_INVERTED = BIT(3), 56 }; 57 58 enum scpsys_bus_prot_block { 59 BUS_PROT_BLOCK_INFRA, 60 BUS_PROT_BLOCK_INFRA_NAO, 61 BUS_PROT_BLOCK_SMI, 62 BUS_PROT_BLOCK_COUNT, 63 }; 64 65 #define _BUS_PROT_STA(_hwip, _sta_hwip, _set_clr_mask, _set, _clr, \ 66 _sta_mask, _sta, _flags) \ 67 { \ 68 .bus_prot_block = BUS_PROT_BLOCK_##_hwip, \ 69 .bus_prot_sta_block = BUS_PROT_BLOCK_##_sta_hwip, \ 70 .bus_prot_set_clr_mask = (_set_clr_mask), \ 71 .bus_prot_set = _set, \ 72 .bus_prot_clr = _clr, \ 73 .bus_prot_sta_mask = (_sta_mask), \ 74 .bus_prot_sta = _sta, \ 75 .flags = _flags \ 76 } 77 78 #define _BUS_PROT(_hwip, _set_clr_mask, _set, _clr, _sta_mask, \ 79 _sta, _flags) \ 80 _BUS_PROT_STA(_hwip, _hwip, _set_clr_mask, _set, _clr, \ 81 _sta_mask, _sta, _flags) 82 83 #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ 84 _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, 0) 85 86 #define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ 87 _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ 88 BUS_PROT_IGNORE_CLR_ACK) 89 90 #define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ 91 _BUS_PROT(_hwip, _mask, _set, _clr, _mask, _sta, \ 92 BUS_PROT_REG_UPDATE) 93 94 #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ 95 BUS_PROT_UPDATE(INFRA, _mask, \ 96 INFRA_TOPAXI_PROTECTEN, \ 97 INFRA_TOPAXI_PROTECTEN, \ 98 INFRA_TOPAXI_PROTECTSTA1) 99 100 struct scpsys_bus_prot_data { 101 u8 bus_prot_block; 102 u8 bus_prot_sta_block; 103 u32 bus_prot_set_clr_mask; 104 u32 bus_prot_set; 105 u32 bus_prot_clr; 106 u32 bus_prot_sta_mask; 107 u32 bus_prot_sta; 108 u8 flags; 109 }; 110 111 /** 112 * enum scpsys_rtff_type - Type of RTFF Hardware for power domain 113 * @SCPSYS_RTFF_NONE: RTFF HW not present or domain not RTFF managed 114 * @SCPSYS_RTFF_TYPE_GENERIC: Non-CPU, peripheral-generic RTFF HW 115 * @SCPSYS_RTFF_TYPE_PCIE_PHY: PCI-Express PHY specific RTFF HW 116 * @SCPSYS_RTFF_TYPE_STOR_UFS: Storage (UFS) specific RTFF HW 117 * @SCPSYS_RTFF_TYPE_MAX: Number of supported RTFF HW Types 118 */ 119 enum scpsys_rtff_type { 120 SCPSYS_RTFF_NONE = 0, 121 SCPSYS_RTFF_TYPE_GENERIC, 122 SCPSYS_RTFF_TYPE_PCIE_PHY, 123 SCPSYS_RTFF_TYPE_STOR_UFS, 124 SCPSYS_RTFF_TYPE_MAX 125 }; 126 127 /** 128 * struct scpsys_domain_data - scp domain data for power on/off flow 129 * @name: The name of the power domain. 130 * @sta_mask: The mask for power on/off status bit. 131 * @ctl_offs: The offset for main power control register. 132 * @sram_pdn_bits: The mask for sram power control bits. 133 * @sram_pdn_ack_bits: The mask for sram power control acked bits. 134 * @ext_buck_iso_offs: The offset for external buck isolation 135 * @ext_buck_iso_mask: The mask for external buck isolation 136 * @caps: The flag for active wake-up action. 137 * @rtff_type: The power domain RTFF HW type 138 * @bp_cfg: bus protection configuration for any subsystem 139 */ 140 struct scpsys_domain_data { 141 const char *name; 142 u32 sta_mask; 143 int ctl_offs; 144 u32 sram_pdn_bits; 145 u32 sram_pdn_ack_bits; 146 int ext_buck_iso_offs; 147 u32 ext_buck_iso_mask; 148 u16 caps; 149 enum scpsys_rtff_type rtff_type; 150 const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; 151 int pwr_sta_offs; 152 int pwr_sta2nd_offs; 153 }; 154 155 struct scpsys_soc_data { 156 const struct scpsys_domain_data *domains_data; 157 int num_domains; 158 enum scpsys_bus_prot_block *bus_prot_blocks; 159 int num_bus_prot_blocks; 160 }; 161 162 #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ 163