1e2ad626fSUlf Hansson /* SPDX-License-Identifier: GPL-2.0-only */ 2e2ad626fSUlf Hansson 3e2ad626fSUlf Hansson #ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H 4e2ad626fSUlf Hansson #define __SOC_MEDIATEK_MTK_PM_DOMAINS_H 5e2ad626fSUlf Hansson 6e2ad626fSUlf Hansson #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) 7e2ad626fSUlf Hansson #define MTK_SCPD_FWAIT_SRAM BIT(1) 8e2ad626fSUlf Hansson #define MTK_SCPD_SRAM_ISO BIT(2) 9e2ad626fSUlf Hansson #define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) 10e2ad626fSUlf Hansson #define MTK_SCPD_DOMAIN_SUPPLY BIT(4) 11e2ad626fSUlf Hansson /* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */ 12e2ad626fSUlf Hansson #define MTK_SCPD_ALWAYS_ON BIT(5) 13e2ad626fSUlf Hansson #define MTK_SCPD_EXT_BUCK_ISO BIT(6) 14ecaf11aaSAlexandre Bailon #define MTK_SCPD_HAS_INFRA_NAO BIT(7) 15*d2567a84SAlexandre Bailon #define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8) 16e2ad626fSUlf Hansson #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) 17e2ad626fSUlf Hansson 18e2ad626fSUlf Hansson #define SPM_VDE_PWR_CON 0x0210 19e2ad626fSUlf Hansson #define SPM_MFG_PWR_CON 0x0214 20e2ad626fSUlf Hansson #define SPM_VEN_PWR_CON 0x0230 21e2ad626fSUlf Hansson #define SPM_ISP_PWR_CON 0x0238 22e2ad626fSUlf Hansson #define SPM_DIS_PWR_CON 0x023c 23e2ad626fSUlf Hansson #define SPM_CONN_PWR_CON 0x0280 24e2ad626fSUlf Hansson #define SPM_VEN2_PWR_CON 0x0298 25e2ad626fSUlf Hansson #define SPM_AUDIO_PWR_CON 0x029c 26e2ad626fSUlf Hansson #define SPM_MFG_2D_PWR_CON 0x02c0 27e2ad626fSUlf Hansson #define SPM_MFG_ASYNC_PWR_CON 0x02c4 28e2ad626fSUlf Hansson #define SPM_USB_PWR_CON 0x02cc 29e2ad626fSUlf Hansson 30e2ad626fSUlf Hansson #define SPM_PWR_STATUS 0x060c 31e2ad626fSUlf Hansson #define SPM_PWR_STATUS_2ND 0x0610 32e2ad626fSUlf Hansson 33e2ad626fSUlf Hansson #define PWR_STATUS_CONN BIT(1) 34e2ad626fSUlf Hansson #define PWR_STATUS_DISP BIT(3) 35e2ad626fSUlf Hansson #define PWR_STATUS_MFG BIT(4) 36e2ad626fSUlf Hansson #define PWR_STATUS_ISP BIT(5) 37e2ad626fSUlf Hansson #define PWR_STATUS_VDEC BIT(7) 38e2ad626fSUlf Hansson #define PWR_STATUS_VENC_LT BIT(20) 39e2ad626fSUlf Hansson #define PWR_STATUS_VENC BIT(21) 40e2ad626fSUlf Hansson #define PWR_STATUS_MFG_2D BIT(22) 41e2ad626fSUlf Hansson #define PWR_STATUS_MFG_ASYNC BIT(23) 42e2ad626fSUlf Hansson #define PWR_STATUS_AUDIO BIT(24) 43e2ad626fSUlf Hansson #define PWR_STATUS_USB BIT(25) 44e2ad626fSUlf Hansson 45e2ad626fSUlf Hansson #define SPM_MAX_BUS_PROT_DATA 6 46e2ad626fSUlf Hansson 47c6bee732SMarkus Schneider-Pargmann enum scpsys_bus_prot_flags { 48c6bee732SMarkus Schneider-Pargmann BUS_PROT_REG_UPDATE = BIT(1), 49c6bee732SMarkus Schneider-Pargmann BUS_PROT_IGNORE_CLR_ACK = BIT(2), 50ecaf11aaSAlexandre Bailon BUS_PROT_INVERTED = BIT(3), 51151bd6c5SMarkus Schneider-Pargmann BUS_PROT_COMPONENT_INFRA = BIT(4), 52151bd6c5SMarkus Schneider-Pargmann BUS_PROT_COMPONENT_SMI = BIT(5), 53ecaf11aaSAlexandre Bailon BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6), 54c6bee732SMarkus Schneider-Pargmann }; 55c6bee732SMarkus Schneider-Pargmann 56ae442ba8SMarkus Schneider-Pargmann #define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \ 57ae442ba8SMarkus Schneider-Pargmann .bus_prot_set_clr_mask = (_set_clr_mask), \ 58e2ad626fSUlf Hansson .bus_prot_set = _set, \ 59e2ad626fSUlf Hansson .bus_prot_clr = _clr, \ 60ae442ba8SMarkus Schneider-Pargmann .bus_prot_sta_mask = (_sta_mask), \ 61e2ad626fSUlf Hansson .bus_prot_sta = _sta, \ 62c6bee732SMarkus Schneider-Pargmann .flags = _flags \ 63e2ad626fSUlf Hansson } 64e2ad626fSUlf Hansson 65151bd6c5SMarkus Schneider-Pargmann #define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \ 66151bd6c5SMarkus Schneider-Pargmann _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip) 67e2ad626fSUlf Hansson 68151bd6c5SMarkus Schneider-Pargmann #define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \ 69151bd6c5SMarkus Schneider-Pargmann _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 70151bd6c5SMarkus Schneider-Pargmann BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK) 71e2ad626fSUlf Hansson 72151bd6c5SMarkus Schneider-Pargmann #define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \ 73151bd6c5SMarkus Schneider-Pargmann _BUS_PROT(_mask, _set, _clr, _mask, _sta, \ 74151bd6c5SMarkus Schneider-Pargmann BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE) 75e2ad626fSUlf Hansson 76151bd6c5SMarkus Schneider-Pargmann #define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \ 77151bd6c5SMarkus Schneider-Pargmann BUS_PROT_UPDATE(INFRA, _mask, \ 78e2ad626fSUlf Hansson INFRA_TOPAXI_PROTECTEN, \ 79e2ad626fSUlf Hansson INFRA_TOPAXI_PROTECTEN, \ 80e2ad626fSUlf Hansson INFRA_TOPAXI_PROTECTSTA1) 81e2ad626fSUlf Hansson 82e2ad626fSUlf Hansson struct scpsys_bus_prot_data { 83ae442ba8SMarkus Schneider-Pargmann u32 bus_prot_set_clr_mask; 84e2ad626fSUlf Hansson u32 bus_prot_set; 85e2ad626fSUlf Hansson u32 bus_prot_clr; 86ae442ba8SMarkus Schneider-Pargmann u32 bus_prot_sta_mask; 87e2ad626fSUlf Hansson u32 bus_prot_sta; 88c6bee732SMarkus Schneider-Pargmann u8 flags; 89e2ad626fSUlf Hansson }; 90e2ad626fSUlf Hansson 91e2ad626fSUlf Hansson /** 92e2ad626fSUlf Hansson * struct scpsys_domain_data - scp domain data for power on/off flow 93e2ad626fSUlf Hansson * @name: The name of the power domain. 94e2ad626fSUlf Hansson * @sta_mask: The mask for power on/off status bit. 95e2ad626fSUlf Hansson * @ctl_offs: The offset for main power control register. 96e2ad626fSUlf Hansson * @sram_pdn_bits: The mask for sram power control bits. 97e2ad626fSUlf Hansson * @sram_pdn_ack_bits: The mask for sram power control acked bits. 98e2ad626fSUlf Hansson * @ext_buck_iso_offs: The offset for external buck isolation 99e2ad626fSUlf Hansson * @ext_buck_iso_mask: The mask for external buck isolation 100e2ad626fSUlf Hansson * @caps: The flag for active wake-up action. 101151bd6c5SMarkus Schneider-Pargmann * @bp_cfg: bus protection configuration for any subsystem 102e2ad626fSUlf Hansson */ 103e2ad626fSUlf Hansson struct scpsys_domain_data { 104e2ad626fSUlf Hansson const char *name; 105e2ad626fSUlf Hansson u32 sta_mask; 106e2ad626fSUlf Hansson int ctl_offs; 107e2ad626fSUlf Hansson u32 sram_pdn_bits; 108e2ad626fSUlf Hansson u32 sram_pdn_ack_bits; 109e2ad626fSUlf Hansson int ext_buck_iso_offs; 110e2ad626fSUlf Hansson u32 ext_buck_iso_mask; 111*d2567a84SAlexandre Bailon u16 caps; 112151bd6c5SMarkus Schneider-Pargmann const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA]; 113e2ad626fSUlf Hansson int pwr_sta_offs; 114e2ad626fSUlf Hansson int pwr_sta2nd_offs; 115e2ad626fSUlf Hansson }; 116e2ad626fSUlf Hansson 117e2ad626fSUlf Hansson struct scpsys_soc_data { 118e2ad626fSUlf Hansson const struct scpsys_domain_data *domains_data; 119e2ad626fSUlf Hansson int num_domains; 120e2ad626fSUlf Hansson }; 121e2ad626fSUlf Hansson 122e2ad626fSUlf Hansson #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ 123