1*c5b5831fSFabien Parent /* SPDX-License-Identifier: GPL-2.0-only */ 2*c5b5831fSFabien Parent 3*c5b5831fSFabien Parent #ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H 4*c5b5831fSFabien Parent #define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H 5*c5b5831fSFabien Parent 6*c5b5831fSFabien Parent #include "mtk-pm-domains.h" 7*c5b5831fSFabien Parent #include <dt-bindings/power/mediatek,mt8365-power.h> 8*c5b5831fSFabien Parent 9*c5b5831fSFabien Parent /* 10*c5b5831fSFabien Parent * MT8365 power domain support 11*c5b5831fSFabien Parent */ 12*c5b5831fSFabien Parent 13*c5b5831fSFabien Parent #define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \ 14*c5b5831fSFabien Parent BUS_PROT_WR(INFRA, _mask, \ 15*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_SET, \ 16*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \ 17*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_STA1) 18*c5b5831fSFabien Parent 19*c5b5831fSFabien Parent #define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \ 20*c5b5831fSFabien Parent BUS_PROT_WR(INFRA, _mask, \ 21*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \ 22*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \ 23*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1) 24*c5b5831fSFabien Parent 25*c5b5831fSFabien Parent #define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \ 26*c5b5831fSFabien Parent BUS_PROT_WR(SMI, BIT(port), \ 27*c5b5831fSFabien Parent MT8365_SMI_COMMON_CLAMP_EN_SET, \ 28*c5b5831fSFabien Parent MT8365_SMI_COMMON_CLAMP_EN_CLR, \ 29*c5b5831fSFabien Parent MT8365_SMI_COMMON_CLAMP_EN) 30*c5b5831fSFabien Parent 31*c5b5831fSFabien Parent #define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \ 32*c5b5831fSFabien Parent _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \ 33*c5b5831fSFabien Parent BUS_PROT_COMPONENT_INFRA | \ 34*c5b5831fSFabien Parent BUS_PROT_STA_COMPONENT_INFRA_NAO | \ 35*c5b5831fSFabien Parent BUS_PROT_INVERTED | \ 36*c5b5831fSFabien Parent BUS_PROT_REG_UPDATE) 37*c5b5831fSFabien Parent 38*c5b5831fSFabien Parent static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = { 39*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_MM] = { 40*c5b5831fSFabien Parent .name = "mm", 41*c5b5831fSFabien Parent .sta_mask = PWR_STATUS_DISP, 42*c5b5831fSFabien Parent .ctl_offs = 0x30c, 43*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 44*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 45*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(8, 8), 46*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(12, 12), 47*c5b5831fSFabien Parent .bp_cfg = { 48*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 49*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 | 50*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1), 51*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI( 52*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 | 53*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 | 54*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 | 55*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1), 56*c5b5831fSFabien Parent MT8365_BUS_PROT_WAY_EN( 57*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S, 58*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_SI0_CTL, 59*c5b5831fSFabien Parent MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED, 60*c5b5831fSFabien Parent MT8365_INFRA_NAO_TOPAXI_SI0_STA), 61*c5b5831fSFabien Parent MT8365_BUS_PROT_WAY_EN( 62*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1, 63*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_SI2_CTL, 64*c5b5831fSFabien Parent MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED, 65*c5b5831fSFabien Parent MT8365_INFRA_NAO_TOPAXI_SI2_STA), 66*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI( 67*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S), 68*c5b5831fSFabien Parent }, 69*c5b5831fSFabien Parent .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO, 70*c5b5831fSFabien Parent }, 71*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_VENC] = { 72*c5b5831fSFabien Parent .name = "venc", 73*c5b5831fSFabien Parent .sta_mask = PWR_STATUS_VENC, 74*c5b5831fSFabien Parent .ctl_offs = 0x0304, 75*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 76*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 77*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(8, 8), 78*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(12, 12), 79*c5b5831fSFabien Parent .bp_cfg = { 80*c5b5831fSFabien Parent MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1), 81*c5b5831fSFabien Parent }, 82*c5b5831fSFabien Parent }, 83*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_AUDIO] = { 84*c5b5831fSFabien Parent .name = "audio", 85*c5b5831fSFabien Parent .sta_mask = PWR_STATUS_AUDIO, 86*c5b5831fSFabien Parent .ctl_offs = 0x0314, 87*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 88*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 89*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(12, 8), 90*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(17, 13), 91*c5b5831fSFabien Parent .bp_cfg = { 92*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 93*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO | 94*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M), 95*c5b5831fSFabien Parent }, 96*c5b5831fSFabien Parent .caps = MTK_SCPD_ACTIVE_WAKEUP, 97*c5b5831fSFabien Parent }, 98*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_CONN] = { 99*c5b5831fSFabien Parent .name = "conn", 100*c5b5831fSFabien Parent .sta_mask = PWR_STATUS_CONN, 101*c5b5831fSFabien Parent .ctl_offs = 0x032c, 102*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 103*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 104*c5b5831fSFabien Parent .sram_pdn_bits = 0, 105*c5b5831fSFabien Parent .sram_pdn_ack_bits = 0, 106*c5b5831fSFabien Parent .bp_cfg = { 107*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI( 108*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB), 109*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 110*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST), 111*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI( 112*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB), 113*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 114*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV), 115*c5b5831fSFabien Parent }, 116*c5b5831fSFabien Parent .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF, 117*c5b5831fSFabien Parent }, 118*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_MFG] = { 119*c5b5831fSFabien Parent .name = "mfg", 120*c5b5831fSFabien Parent .sta_mask = PWR_STATUS_MFG, 121*c5b5831fSFabien Parent .ctl_offs = 0x0338, 122*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 123*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 124*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(9, 8), 125*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(13, 12), 126*c5b5831fSFabien Parent .bp_cfg = { 127*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)), 128*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI( 129*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 | 130*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG), 131*c5b5831fSFabien Parent }, 132*c5b5831fSFabien Parent }, 133*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_CAM] = { 134*c5b5831fSFabien Parent .name = "cam", 135*c5b5831fSFabien Parent .sta_mask = BIT(25), 136*c5b5831fSFabien Parent .ctl_offs = 0x0344, 137*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 138*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 139*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(9, 8), 140*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(13, 12), 141*c5b5831fSFabien Parent .bp_cfg = { 142*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 143*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST), 144*c5b5831fSFabien Parent MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2), 145*c5b5831fSFabien Parent }, 146*c5b5831fSFabien Parent }, 147*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_VDEC] = { 148*c5b5831fSFabien Parent .name = "vdec", 149*c5b5831fSFabien Parent .sta_mask = BIT(31), 150*c5b5831fSFabien Parent .ctl_offs = 0x0370, 151*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 152*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 153*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(8, 8), 154*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(12, 12), 155*c5b5831fSFabien Parent .bp_cfg = { 156*c5b5831fSFabien Parent MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3), 157*c5b5831fSFabien Parent }, 158*c5b5831fSFabien Parent }, 159*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_APU] = { 160*c5b5831fSFabien Parent .name = "apu", 161*c5b5831fSFabien Parent .sta_mask = BIT(16), 162*c5b5831fSFabien Parent .ctl_offs = 0x0378, 163*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 164*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 165*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(14, 8), 166*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(21, 15), 167*c5b5831fSFabien Parent .bp_cfg = { 168*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 169*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP | 170*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST), 171*c5b5831fSFabien Parent MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4), 172*c5b5831fSFabien Parent }, 173*c5b5831fSFabien Parent }, 174*c5b5831fSFabien Parent [MT8365_POWER_DOMAIN_DSP] = { 175*c5b5831fSFabien Parent .name = "dsp", 176*c5b5831fSFabien Parent .sta_mask = BIT(17), 177*c5b5831fSFabien Parent .ctl_offs = 0x037C, 178*c5b5831fSFabien Parent .pwr_sta_offs = 0x0180, 179*c5b5831fSFabien Parent .pwr_sta2nd_offs = 0x0184, 180*c5b5831fSFabien Parent .sram_pdn_bits = GENMASK(11, 8), 181*c5b5831fSFabien Parent .sram_pdn_ack_bits = GENMASK(15, 12), 182*c5b5831fSFabien Parent .bp_cfg = { 183*c5b5831fSFabien Parent MT8365_BUS_PROT_INFRA_WR_TOPAXI_1( 184*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB | 185*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M | 186*c5b5831fSFabien Parent MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S), 187*c5b5831fSFabien Parent }, 188*c5b5831fSFabien Parent .caps = MTK_SCPD_ACTIVE_WAKEUP, 189*c5b5831fSFabien Parent }, 190*c5b5831fSFabien Parent }; 191*c5b5831fSFabien Parent 192*c5b5831fSFabien Parent static const struct scpsys_soc_data mt8365_scpsys_data = { 193*c5b5831fSFabien Parent .domains_data = scpsys_domain_data_mt8365, 194*c5b5831fSFabien Parent .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365), 195*c5b5831fSFabien Parent }; 196*c5b5831fSFabien Parent 197*c5b5831fSFabien Parent #endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */ 198