1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7 #ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 8 #define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H 9 10 #include "mtk-pm-domains.h" 11 #include <dt-bindings/power/mt8195-power.h> 12 13 /* 14 * MT8195 power domain support 15 */ 16 17 static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { 18 [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { 19 .name = "pcie_mac_p0", 20 .sta_mask = BIT(11), 21 .ctl_offs = 0x328, 22 .pwr_sta_offs = 0x174, 23 .pwr_sta2nd_offs = 0x178, 24 .sram_pdn_bits = GENMASK(8, 8), 25 .sram_pdn_ack_bits = GENMASK(12, 12), 26 .bp_cfg = { 27 BUS_PROT_WR(INFRA, 28 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, 29 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 30 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 31 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 32 BUS_PROT_WR(INFRA, 33 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, 34 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 35 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 36 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 37 }, 38 }, 39 [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { 40 .name = "pcie_mac_p1", 41 .sta_mask = BIT(12), 42 .ctl_offs = 0x32C, 43 .pwr_sta_offs = 0x174, 44 .pwr_sta2nd_offs = 0x178, 45 .sram_pdn_bits = GENMASK(8, 8), 46 .sram_pdn_ack_bits = GENMASK(12, 12), 47 .bp_cfg = { 48 BUS_PROT_WR(INFRA, 49 MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, 50 MT8195_TOP_AXI_PROT_EN_VDNR_SET, 51 MT8195_TOP_AXI_PROT_EN_VDNR_CLR, 52 MT8195_TOP_AXI_PROT_EN_VDNR_STA1), 53 BUS_PROT_WR(INFRA, 54 MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, 55 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 56 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 57 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 58 }, 59 }, 60 [MT8195_POWER_DOMAIN_PCIE_PHY] = { 61 .name = "pcie_phy", 62 .sta_mask = BIT(13), 63 .ctl_offs = 0x330, 64 .pwr_sta_offs = 0x174, 65 .pwr_sta2nd_offs = 0x178, 66 .caps = MTK_SCPD_ACTIVE_WAKEUP, 67 }, 68 [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { 69 .name = "ssusb_pcie_phy", 70 .sta_mask = BIT(14), 71 .ctl_offs = 0x334, 72 .pwr_sta_offs = 0x174, 73 .pwr_sta2nd_offs = 0x178, 74 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON, 75 }, 76 [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { 77 .name = "csi_rx_top", 78 .sta_mask = BIT(18), 79 .ctl_offs = 0x3C4, 80 .pwr_sta_offs = 0x174, 81 .pwr_sta2nd_offs = 0x178, 82 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 83 }, 84 [MT8195_POWER_DOMAIN_ETHER] = { 85 .name = "ether", 86 .sta_mask = BIT(3), 87 .ctl_offs = 0x344, 88 .pwr_sta_offs = 0x16c, 89 .pwr_sta2nd_offs = 0x170, 90 .sram_pdn_bits = GENMASK(8, 8), 91 .sram_pdn_ack_bits = GENMASK(12, 12), 92 .caps = MTK_SCPD_ACTIVE_WAKEUP, 93 }, 94 [MT8195_POWER_DOMAIN_ADSP] = { 95 .name = "adsp", 96 .sta_mask = BIT(10), 97 .ctl_offs = 0x360, 98 .pwr_sta_offs = 0x16c, 99 .pwr_sta2nd_offs = 0x170, 100 .sram_pdn_bits = GENMASK(8, 8), 101 .sram_pdn_ack_bits = GENMASK(12, 12), 102 .bp_cfg = { 103 BUS_PROT_WR(INFRA, 104 MT8195_TOP_AXI_PROT_EN_2_ADSP, 105 MT8195_TOP_AXI_PROT_EN_2_SET, 106 MT8195_TOP_AXI_PROT_EN_2_CLR, 107 MT8195_TOP_AXI_PROT_EN_2_STA1), 108 }, 109 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 110 }, 111 [MT8195_POWER_DOMAIN_AUDIO] = { 112 .name = "audio", 113 .sta_mask = BIT(8), 114 .ctl_offs = 0x358, 115 .pwr_sta_offs = 0x16c, 116 .pwr_sta2nd_offs = 0x170, 117 .sram_pdn_bits = GENMASK(8, 8), 118 .sram_pdn_ack_bits = GENMASK(12, 12), 119 .bp_cfg = { 120 BUS_PROT_WR(INFRA, 121 MT8195_TOP_AXI_PROT_EN_2_AUDIO, 122 MT8195_TOP_AXI_PROT_EN_2_SET, 123 MT8195_TOP_AXI_PROT_EN_2_CLR, 124 MT8195_TOP_AXI_PROT_EN_2_STA1), 125 }, 126 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 127 }, 128 [MT8195_POWER_DOMAIN_MFG0] = { 129 .name = "mfg0", 130 .sta_mask = BIT(1), 131 .ctl_offs = 0x300, 132 .pwr_sta_offs = 0x174, 133 .pwr_sta2nd_offs = 0x178, 134 .sram_pdn_bits = GENMASK(8, 8), 135 .sram_pdn_ack_bits = GENMASK(12, 12), 136 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 137 }, 138 [MT8195_POWER_DOMAIN_MFG1] = { 139 .name = "mfg1", 140 .sta_mask = BIT(2), 141 .ctl_offs = 0x304, 142 .pwr_sta_offs = 0x174, 143 .pwr_sta2nd_offs = 0x178, 144 .sram_pdn_bits = GENMASK(8, 8), 145 .sram_pdn_ack_bits = GENMASK(12, 12), 146 .bp_cfg = { 147 BUS_PROT_WR(INFRA, 148 MT8195_TOP_AXI_PROT_EN_MFG1, 149 MT8195_TOP_AXI_PROT_EN_SET, 150 MT8195_TOP_AXI_PROT_EN_CLR, 151 MT8195_TOP_AXI_PROT_EN_STA1), 152 BUS_PROT_WR(INFRA, 153 MT8195_TOP_AXI_PROT_EN_2_MFG1, 154 MT8195_TOP_AXI_PROT_EN_2_SET, 155 MT8195_TOP_AXI_PROT_EN_2_CLR, 156 MT8195_TOP_AXI_PROT_EN_2_STA1), 157 BUS_PROT_WR(INFRA, 158 MT8195_TOP_AXI_PROT_EN_1_MFG1, 159 MT8195_TOP_AXI_PROT_EN_1_SET, 160 MT8195_TOP_AXI_PROT_EN_1_CLR, 161 MT8195_TOP_AXI_PROT_EN_1_STA1), 162 BUS_PROT_WR(INFRA, 163 MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, 164 MT8195_TOP_AXI_PROT_EN_2_SET, 165 MT8195_TOP_AXI_PROT_EN_2_CLR, 166 MT8195_TOP_AXI_PROT_EN_2_STA1), 167 BUS_PROT_WR(INFRA, 168 MT8195_TOP_AXI_PROT_EN_MFG1_2ND, 169 MT8195_TOP_AXI_PROT_EN_SET, 170 MT8195_TOP_AXI_PROT_EN_CLR, 171 MT8195_TOP_AXI_PROT_EN_STA1), 172 BUS_PROT_WR(INFRA, 173 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, 174 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 175 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 176 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 177 }, 178 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 179 }, 180 [MT8195_POWER_DOMAIN_MFG2] = { 181 .name = "mfg2", 182 .sta_mask = BIT(3), 183 .ctl_offs = 0x308, 184 .pwr_sta_offs = 0x174, 185 .pwr_sta2nd_offs = 0x178, 186 .sram_pdn_bits = GENMASK(8, 8), 187 .sram_pdn_ack_bits = GENMASK(12, 12), 188 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 189 }, 190 [MT8195_POWER_DOMAIN_MFG3] = { 191 .name = "mfg3", 192 .sta_mask = BIT(4), 193 .ctl_offs = 0x30C, 194 .pwr_sta_offs = 0x174, 195 .pwr_sta2nd_offs = 0x178, 196 .sram_pdn_bits = GENMASK(8, 8), 197 .sram_pdn_ack_bits = GENMASK(12, 12), 198 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 199 }, 200 [MT8195_POWER_DOMAIN_MFG4] = { 201 .name = "mfg4", 202 .sta_mask = BIT(5), 203 .ctl_offs = 0x310, 204 .pwr_sta_offs = 0x174, 205 .pwr_sta2nd_offs = 0x178, 206 .sram_pdn_bits = GENMASK(8, 8), 207 .sram_pdn_ack_bits = GENMASK(12, 12), 208 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 209 }, 210 [MT8195_POWER_DOMAIN_MFG5] = { 211 .name = "mfg5", 212 .sta_mask = BIT(6), 213 .ctl_offs = 0x314, 214 .pwr_sta_offs = 0x174, 215 .pwr_sta2nd_offs = 0x178, 216 .sram_pdn_bits = GENMASK(8, 8), 217 .sram_pdn_ack_bits = GENMASK(12, 12), 218 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 219 }, 220 [MT8195_POWER_DOMAIN_MFG6] = { 221 .name = "mfg6", 222 .sta_mask = BIT(7), 223 .ctl_offs = 0x318, 224 .pwr_sta_offs = 0x174, 225 .pwr_sta2nd_offs = 0x178, 226 .sram_pdn_bits = GENMASK(8, 8), 227 .sram_pdn_ack_bits = GENMASK(12, 12), 228 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 229 }, 230 [MT8195_POWER_DOMAIN_VPPSYS0] = { 231 .name = "vppsys0", 232 .sta_mask = BIT(11), 233 .ctl_offs = 0x364, 234 .pwr_sta_offs = 0x16c, 235 .pwr_sta2nd_offs = 0x170, 236 .sram_pdn_bits = GENMASK(8, 8), 237 .sram_pdn_ack_bits = GENMASK(12, 12), 238 .bp_cfg = { 239 BUS_PROT_WR(INFRA, 240 MT8195_TOP_AXI_PROT_EN_VPPSYS0, 241 MT8195_TOP_AXI_PROT_EN_SET, 242 MT8195_TOP_AXI_PROT_EN_CLR, 243 MT8195_TOP_AXI_PROT_EN_STA1), 244 BUS_PROT_WR(INFRA, 245 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, 246 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 247 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 248 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 249 BUS_PROT_WR(INFRA, 250 MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, 251 MT8195_TOP_AXI_PROT_EN_SET, 252 MT8195_TOP_AXI_PROT_EN_CLR, 253 MT8195_TOP_AXI_PROT_EN_STA1), 254 BUS_PROT_WR(INFRA, 255 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, 256 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 257 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 258 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 259 BUS_PROT_WR(INFRA, 260 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, 261 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 262 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 263 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 264 }, 265 }, 266 [MT8195_POWER_DOMAIN_VDOSYS0] = { 267 .name = "vdosys0", 268 .sta_mask = BIT(13), 269 .ctl_offs = 0x36C, 270 .pwr_sta_offs = 0x16c, 271 .pwr_sta2nd_offs = 0x170, 272 .sram_pdn_bits = GENMASK(8, 8), 273 .sram_pdn_ack_bits = GENMASK(12, 12), 274 .bp_cfg = { 275 BUS_PROT_WR(INFRA, 276 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, 277 MT8195_TOP_AXI_PROT_EN_MM_SET, 278 MT8195_TOP_AXI_PROT_EN_MM_CLR, 279 MT8195_TOP_AXI_PROT_EN_MM_STA1), 280 BUS_PROT_WR(INFRA, 281 MT8195_TOP_AXI_PROT_EN_VDOSYS0, 282 MT8195_TOP_AXI_PROT_EN_SET, 283 MT8195_TOP_AXI_PROT_EN_CLR, 284 MT8195_TOP_AXI_PROT_EN_STA1), 285 BUS_PROT_WR(INFRA, 286 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, 287 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 288 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 289 MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), 290 }, 291 }, 292 [MT8195_POWER_DOMAIN_VPPSYS1] = { 293 .name = "vppsys1", 294 .sta_mask = BIT(12), 295 .ctl_offs = 0x368, 296 .pwr_sta_offs = 0x16c, 297 .pwr_sta2nd_offs = 0x170, 298 .sram_pdn_bits = GENMASK(8, 8), 299 .sram_pdn_ack_bits = GENMASK(12, 12), 300 .bp_cfg = { 301 BUS_PROT_WR(INFRA, 302 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, 303 MT8195_TOP_AXI_PROT_EN_MM_SET, 304 MT8195_TOP_AXI_PROT_EN_MM_CLR, 305 MT8195_TOP_AXI_PROT_EN_MM_STA1), 306 BUS_PROT_WR(INFRA, 307 MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, 308 MT8195_TOP_AXI_PROT_EN_MM_SET, 309 MT8195_TOP_AXI_PROT_EN_MM_CLR, 310 MT8195_TOP_AXI_PROT_EN_MM_STA1), 311 BUS_PROT_WR(INFRA, 312 MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, 313 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 314 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 315 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 316 }, 317 }, 318 [MT8195_POWER_DOMAIN_VDOSYS1] = { 319 .name = "vdosys1", 320 .sta_mask = BIT(14), 321 .ctl_offs = 0x370, 322 .pwr_sta_offs = 0x16c, 323 .pwr_sta2nd_offs = 0x170, 324 .sram_pdn_bits = GENMASK(8, 8), 325 .sram_pdn_ack_bits = GENMASK(12, 12), 326 .bp_cfg = { 327 BUS_PROT_WR(INFRA, 328 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, 329 MT8195_TOP_AXI_PROT_EN_MM_SET, 330 MT8195_TOP_AXI_PROT_EN_MM_CLR, 331 MT8195_TOP_AXI_PROT_EN_MM_STA1), 332 BUS_PROT_WR(INFRA, 333 MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, 334 MT8195_TOP_AXI_PROT_EN_MM_SET, 335 MT8195_TOP_AXI_PROT_EN_MM_CLR, 336 MT8195_TOP_AXI_PROT_EN_MM_STA1), 337 BUS_PROT_WR(INFRA, 338 MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, 339 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 340 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 341 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 342 }, 343 }, 344 [MT8195_POWER_DOMAIN_DP_TX] = { 345 .name = "dp_tx", 346 .sta_mask = BIT(16), 347 .ctl_offs = 0x378, 348 .pwr_sta_offs = 0x16c, 349 .pwr_sta2nd_offs = 0x170, 350 .sram_pdn_bits = GENMASK(8, 8), 351 .sram_pdn_ack_bits = GENMASK(12, 12), 352 .bp_cfg = { 353 BUS_PROT_WR(INFRA, 354 MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, 355 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 356 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 357 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 358 }, 359 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 360 }, 361 [MT8195_POWER_DOMAIN_EPD_TX] = { 362 .name = "epd_tx", 363 .sta_mask = BIT(17), 364 .ctl_offs = 0x37C, 365 .pwr_sta_offs = 0x16c, 366 .pwr_sta2nd_offs = 0x170, 367 .sram_pdn_bits = GENMASK(8, 8), 368 .sram_pdn_ack_bits = GENMASK(12, 12), 369 .bp_cfg = { 370 BUS_PROT_WR(INFRA, 371 MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, 372 MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, 373 MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, 374 MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), 375 }, 376 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 377 }, 378 [MT8195_POWER_DOMAIN_HDMI_TX] = { 379 .name = "hdmi_tx", 380 .sta_mask = BIT(18), 381 .ctl_offs = 0x380, 382 .pwr_sta_offs = 0x16c, 383 .pwr_sta2nd_offs = 0x170, 384 .sram_pdn_bits = GENMASK(8, 8), 385 .sram_pdn_ack_bits = GENMASK(12, 12), 386 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 387 }, 388 [MT8195_POWER_DOMAIN_WPESYS] = { 389 .name = "wpesys", 390 .sta_mask = BIT(15), 391 .ctl_offs = 0x374, 392 .pwr_sta_offs = 0x16c, 393 .pwr_sta2nd_offs = 0x170, 394 .sram_pdn_bits = GENMASK(8, 8), 395 .sram_pdn_ack_bits = GENMASK(12, 12), 396 .bp_cfg = { 397 BUS_PROT_WR(INFRA, 398 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, 399 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 400 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 401 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 402 BUS_PROT_WR(INFRA, 403 MT8195_TOP_AXI_PROT_EN_MM_WPESYS, 404 MT8195_TOP_AXI_PROT_EN_MM_SET, 405 MT8195_TOP_AXI_PROT_EN_MM_CLR, 406 MT8195_TOP_AXI_PROT_EN_MM_STA1), 407 BUS_PROT_WR(INFRA, 408 MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, 409 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 410 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 411 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 412 }, 413 }, 414 [MT8195_POWER_DOMAIN_VDEC0] = { 415 .name = "vdec0", 416 .sta_mask = BIT(20), 417 .ctl_offs = 0x388, 418 .pwr_sta_offs = 0x16c, 419 .pwr_sta2nd_offs = 0x170, 420 .sram_pdn_bits = GENMASK(8, 8), 421 .sram_pdn_ack_bits = GENMASK(12, 12), 422 .bp_cfg = { 423 BUS_PROT_WR(INFRA, 424 MT8195_TOP_AXI_PROT_EN_MM_VDEC0, 425 MT8195_TOP_AXI_PROT_EN_MM_SET, 426 MT8195_TOP_AXI_PROT_EN_MM_CLR, 427 MT8195_TOP_AXI_PROT_EN_MM_STA1), 428 BUS_PROT_WR(INFRA, 429 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, 430 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 431 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 432 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 433 BUS_PROT_WR(INFRA, 434 MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, 435 MT8195_TOP_AXI_PROT_EN_MM_SET, 436 MT8195_TOP_AXI_PROT_EN_MM_CLR, 437 MT8195_TOP_AXI_PROT_EN_MM_STA1), 438 BUS_PROT_WR(INFRA, 439 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, 440 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 441 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 442 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 443 }, 444 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 445 }, 446 [MT8195_POWER_DOMAIN_VDEC1] = { 447 .name = "vdec1", 448 .sta_mask = BIT(21), 449 .ctl_offs = 0x38C, 450 .pwr_sta_offs = 0x16c, 451 .pwr_sta2nd_offs = 0x170, 452 .sram_pdn_bits = GENMASK(8, 8), 453 .sram_pdn_ack_bits = GENMASK(12, 12), 454 .bp_cfg = { 455 BUS_PROT_WR(INFRA, 456 MT8195_TOP_AXI_PROT_EN_MM_VDEC1, 457 MT8195_TOP_AXI_PROT_EN_MM_SET, 458 MT8195_TOP_AXI_PROT_EN_MM_CLR, 459 MT8195_TOP_AXI_PROT_EN_MM_STA1), 460 BUS_PROT_WR(INFRA, 461 MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, 462 MT8195_TOP_AXI_PROT_EN_MM_SET, 463 MT8195_TOP_AXI_PROT_EN_MM_CLR, 464 MT8195_TOP_AXI_PROT_EN_MM_STA1), 465 }, 466 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 467 }, 468 [MT8195_POWER_DOMAIN_VDEC2] = { 469 .name = "vdec2", 470 .sta_mask = BIT(22), 471 .ctl_offs = 0x390, 472 .pwr_sta_offs = 0x16c, 473 .pwr_sta2nd_offs = 0x170, 474 .sram_pdn_bits = GENMASK(8, 8), 475 .sram_pdn_ack_bits = GENMASK(12, 12), 476 .bp_cfg = { 477 BUS_PROT_WR(INFRA, 478 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, 479 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 480 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 481 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 482 BUS_PROT_WR(INFRA, 483 MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, 484 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 485 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 486 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 487 }, 488 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 489 }, 490 [MT8195_POWER_DOMAIN_VENC] = { 491 .name = "venc", 492 .sta_mask = BIT(23), 493 .ctl_offs = 0x394, 494 .pwr_sta_offs = 0x16c, 495 .pwr_sta2nd_offs = 0x170, 496 .sram_pdn_bits = GENMASK(8, 8), 497 .sram_pdn_ack_bits = GENMASK(12, 12), 498 .bp_cfg = { 499 BUS_PROT_WR(INFRA, 500 MT8195_TOP_AXI_PROT_EN_MM_VENC, 501 MT8195_TOP_AXI_PROT_EN_MM_SET, 502 MT8195_TOP_AXI_PROT_EN_MM_CLR, 503 MT8195_TOP_AXI_PROT_EN_MM_STA1), 504 BUS_PROT_WR(INFRA, 505 MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, 506 MT8195_TOP_AXI_PROT_EN_MM_SET, 507 MT8195_TOP_AXI_PROT_EN_MM_CLR, 508 MT8195_TOP_AXI_PROT_EN_MM_STA1), 509 BUS_PROT_WR(INFRA, 510 MT8195_TOP_AXI_PROT_EN_MM_2_VENC, 511 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 512 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 513 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 514 }, 515 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 516 }, 517 [MT8195_POWER_DOMAIN_VENC_CORE1] = { 518 .name = "venc_core1", 519 .sta_mask = BIT(24), 520 .ctl_offs = 0x398, 521 .pwr_sta_offs = 0x16c, 522 .pwr_sta2nd_offs = 0x170, 523 .sram_pdn_bits = GENMASK(8, 8), 524 .sram_pdn_ack_bits = GENMASK(12, 12), 525 .bp_cfg = { 526 BUS_PROT_WR(INFRA, 527 MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, 528 MT8195_TOP_AXI_PROT_EN_MM_SET, 529 MT8195_TOP_AXI_PROT_EN_MM_CLR, 530 MT8195_TOP_AXI_PROT_EN_MM_STA1), 531 BUS_PROT_WR(INFRA, 532 MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, 533 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 534 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 535 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 536 }, 537 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 538 }, 539 [MT8195_POWER_DOMAIN_IMG] = { 540 .name = "img", 541 .sta_mask = BIT(29), 542 .ctl_offs = 0x3AC, 543 .pwr_sta_offs = 0x16c, 544 .pwr_sta2nd_offs = 0x170, 545 .sram_pdn_bits = GENMASK(8, 8), 546 .sram_pdn_ack_bits = GENMASK(12, 12), 547 .bp_cfg = { 548 BUS_PROT_WR(INFRA, 549 MT8195_TOP_AXI_PROT_EN_MM_IMG, 550 MT8195_TOP_AXI_PROT_EN_MM_SET, 551 MT8195_TOP_AXI_PROT_EN_MM_CLR, 552 MT8195_TOP_AXI_PROT_EN_MM_STA1), 553 BUS_PROT_WR(INFRA, 554 MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, 555 MT8195_TOP_AXI_PROT_EN_MM_SET, 556 MT8195_TOP_AXI_PROT_EN_MM_CLR, 557 MT8195_TOP_AXI_PROT_EN_MM_STA1), 558 }, 559 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 560 }, 561 [MT8195_POWER_DOMAIN_DIP] = { 562 .name = "dip", 563 .sta_mask = BIT(30), 564 .ctl_offs = 0x3B0, 565 .pwr_sta_offs = 0x16c, 566 .pwr_sta2nd_offs = 0x170, 567 .sram_pdn_bits = GENMASK(8, 8), 568 .sram_pdn_ack_bits = GENMASK(12, 12), 569 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 570 }, 571 [MT8195_POWER_DOMAIN_IPE] = { 572 .name = "ipe", 573 .sta_mask = BIT(31), 574 .ctl_offs = 0x3B4, 575 .pwr_sta_offs = 0x16c, 576 .pwr_sta2nd_offs = 0x170, 577 .sram_pdn_bits = GENMASK(8, 8), 578 .sram_pdn_ack_bits = GENMASK(12, 12), 579 .bp_cfg = { 580 BUS_PROT_WR(INFRA, 581 MT8195_TOP_AXI_PROT_EN_MM_IPE, 582 MT8195_TOP_AXI_PROT_EN_MM_SET, 583 MT8195_TOP_AXI_PROT_EN_MM_CLR, 584 MT8195_TOP_AXI_PROT_EN_MM_STA1), 585 BUS_PROT_WR(INFRA, 586 MT8195_TOP_AXI_PROT_EN_MM_2_IPE, 587 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 588 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 589 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 590 }, 591 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 592 }, 593 [MT8195_POWER_DOMAIN_CAM] = { 594 .name = "cam", 595 .sta_mask = BIT(25), 596 .ctl_offs = 0x39C, 597 .pwr_sta_offs = 0x16c, 598 .pwr_sta2nd_offs = 0x170, 599 .sram_pdn_bits = GENMASK(8, 8), 600 .sram_pdn_ack_bits = GENMASK(12, 12), 601 .bp_cfg = { 602 BUS_PROT_WR(INFRA, 603 MT8195_TOP_AXI_PROT_EN_2_CAM, 604 MT8195_TOP_AXI_PROT_EN_2_SET, 605 MT8195_TOP_AXI_PROT_EN_2_CLR, 606 MT8195_TOP_AXI_PROT_EN_2_STA1), 607 BUS_PROT_WR(INFRA, 608 MT8195_TOP_AXI_PROT_EN_MM_CAM, 609 MT8195_TOP_AXI_PROT_EN_MM_SET, 610 MT8195_TOP_AXI_PROT_EN_MM_CLR, 611 MT8195_TOP_AXI_PROT_EN_MM_STA1), 612 BUS_PROT_WR(INFRA, 613 MT8195_TOP_AXI_PROT_EN_1_CAM, 614 MT8195_TOP_AXI_PROT_EN_1_SET, 615 MT8195_TOP_AXI_PROT_EN_1_CLR, 616 MT8195_TOP_AXI_PROT_EN_1_STA1), 617 BUS_PROT_WR(INFRA, 618 MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, 619 MT8195_TOP_AXI_PROT_EN_MM_SET, 620 MT8195_TOP_AXI_PROT_EN_MM_CLR, 621 MT8195_TOP_AXI_PROT_EN_MM_STA1), 622 BUS_PROT_WR(INFRA, 623 MT8195_TOP_AXI_PROT_EN_MM_2_CAM, 624 MT8195_TOP_AXI_PROT_EN_MM_2_SET, 625 MT8195_TOP_AXI_PROT_EN_MM_2_CLR, 626 MT8195_TOP_AXI_PROT_EN_MM_2_STA1), 627 }, 628 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 629 }, 630 [MT8195_POWER_DOMAIN_CAM_RAWA] = { 631 .name = "cam_rawa", 632 .sta_mask = BIT(26), 633 .ctl_offs = 0x3A0, 634 .pwr_sta_offs = 0x16c, 635 .pwr_sta2nd_offs = 0x170, 636 .sram_pdn_bits = GENMASK(8, 8), 637 .sram_pdn_ack_bits = GENMASK(12, 12), 638 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 639 }, 640 [MT8195_POWER_DOMAIN_CAM_RAWB] = { 641 .name = "cam_rawb", 642 .sta_mask = BIT(27), 643 .ctl_offs = 0x3A4, 644 .pwr_sta_offs = 0x16c, 645 .pwr_sta2nd_offs = 0x170, 646 .sram_pdn_bits = GENMASK(8, 8), 647 .sram_pdn_ack_bits = GENMASK(12, 12), 648 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 649 }, 650 [MT8195_POWER_DOMAIN_CAM_MRAW] = { 651 .name = "cam_mraw", 652 .sta_mask = BIT(28), 653 .ctl_offs = 0x3A8, 654 .pwr_sta_offs = 0x16c, 655 .pwr_sta2nd_offs = 0x170, 656 .sram_pdn_bits = GENMASK(8, 8), 657 .sram_pdn_ack_bits = GENMASK(12, 12), 658 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 659 }, 660 }; 661 662 static const struct scpsys_soc_data mt8195_scpsys_data = { 663 .domains_data = scpsys_domain_data_mt8195, 664 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), 665 }; 666 667 #endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ 668