1*e2ad626fSUlf Hansson /* SPDX-License-Identifier: GPL-2.0-only */ 2*e2ad626fSUlf Hansson 3*e2ad626fSUlf Hansson #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H 4*e2ad626fSUlf Hansson #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H 5*e2ad626fSUlf Hansson 6*e2ad626fSUlf Hansson #include "mtk-pm-domains.h" 7*e2ad626fSUlf Hansson #include <dt-bindings/power/mt8192-power.h> 8*e2ad626fSUlf Hansson 9*e2ad626fSUlf Hansson /* 10*e2ad626fSUlf Hansson * MT8192 power domain support 11*e2ad626fSUlf Hansson */ 12*e2ad626fSUlf Hansson 13*e2ad626fSUlf Hansson static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { 14*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_AUDIO] = { 15*e2ad626fSUlf Hansson .name = "audio", 16*e2ad626fSUlf Hansson .sta_mask = BIT(21), 17*e2ad626fSUlf Hansson .ctl_offs = 0x0354, 18*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 19*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 20*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 21*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 22*e2ad626fSUlf Hansson .bp_infracfg = { 23*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, 24*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_SET, 25*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_CLR, 26*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_STA1), 27*e2ad626fSUlf Hansson }, 28*e2ad626fSUlf Hansson }, 29*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_CONN] = { 30*e2ad626fSUlf Hansson .name = "conn", 31*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_CONN, 32*e2ad626fSUlf Hansson .ctl_offs = 0x0304, 33*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 34*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 35*e2ad626fSUlf Hansson .sram_pdn_bits = 0, 36*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 37*e2ad626fSUlf Hansson .bp_infracfg = { 38*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, 39*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_SET, 40*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_CLR, 41*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_STA1), 42*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, 43*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_SET, 44*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_CLR, 45*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_STA1), 46*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, 47*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_SET, 48*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_CLR, 49*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_STA1), 50*e2ad626fSUlf Hansson }, 51*e2ad626fSUlf Hansson .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 52*e2ad626fSUlf Hansson }, 53*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG0] = { 54*e2ad626fSUlf Hansson .name = "mfg0", 55*e2ad626fSUlf Hansson .sta_mask = BIT(2), 56*e2ad626fSUlf Hansson .ctl_offs = 0x0308, 57*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 58*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 59*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 60*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 61*e2ad626fSUlf Hansson .caps = MTK_SCPD_DOMAIN_SUPPLY, 62*e2ad626fSUlf Hansson }, 63*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG1] = { 64*e2ad626fSUlf Hansson .name = "mfg1", 65*e2ad626fSUlf Hansson .sta_mask = BIT(3), 66*e2ad626fSUlf Hansson .ctl_offs = 0x030c, 67*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 68*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 69*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 70*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 71*e2ad626fSUlf Hansson .bp_infracfg = { 72*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, 73*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_SET, 74*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_CLR, 75*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_STA1), 76*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, 77*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_SET, 78*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_CLR, 79*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_STA1), 80*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, 81*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_SET, 82*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_CLR, 83*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_STA1), 84*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, 85*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_SET, 86*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_CLR, 87*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_STA1), 88*e2ad626fSUlf Hansson }, 89*e2ad626fSUlf Hansson .caps = MTK_SCPD_DOMAIN_SUPPLY, 90*e2ad626fSUlf Hansson }, 91*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG2] = { 92*e2ad626fSUlf Hansson .name = "mfg2", 93*e2ad626fSUlf Hansson .sta_mask = BIT(4), 94*e2ad626fSUlf Hansson .ctl_offs = 0x0310, 95*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 96*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 97*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 98*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 99*e2ad626fSUlf Hansson }, 100*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG3] = { 101*e2ad626fSUlf Hansson .name = "mfg3", 102*e2ad626fSUlf Hansson .sta_mask = BIT(5), 103*e2ad626fSUlf Hansson .ctl_offs = 0x0314, 104*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 105*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 106*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 107*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 108*e2ad626fSUlf Hansson }, 109*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG4] = { 110*e2ad626fSUlf Hansson .name = "mfg4", 111*e2ad626fSUlf Hansson .sta_mask = BIT(6), 112*e2ad626fSUlf Hansson .ctl_offs = 0x0318, 113*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 114*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 115*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 116*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 117*e2ad626fSUlf Hansson }, 118*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG5] = { 119*e2ad626fSUlf Hansson .name = "mfg5", 120*e2ad626fSUlf Hansson .sta_mask = BIT(7), 121*e2ad626fSUlf Hansson .ctl_offs = 0x031c, 122*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 123*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 124*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 125*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 126*e2ad626fSUlf Hansson }, 127*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MFG6] = { 128*e2ad626fSUlf Hansson .name = "mfg6", 129*e2ad626fSUlf Hansson .sta_mask = BIT(8), 130*e2ad626fSUlf Hansson .ctl_offs = 0x0320, 131*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 132*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 133*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 134*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 135*e2ad626fSUlf Hansson }, 136*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_DISP] = { 137*e2ad626fSUlf Hansson .name = "disp", 138*e2ad626fSUlf Hansson .sta_mask = BIT(20), 139*e2ad626fSUlf Hansson .ctl_offs = 0x0350, 140*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 141*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 142*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 143*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 144*e2ad626fSUlf Hansson .bp_infracfg = { 145*e2ad626fSUlf Hansson BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, 146*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 147*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 148*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 149*e2ad626fSUlf Hansson BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, 150*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 151*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 152*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 153*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, 154*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_SET, 155*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_CLR, 156*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_STA1), 157*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, 158*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 159*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 160*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 161*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, 162*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 163*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 164*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 165*e2ad626fSUlf Hansson }, 166*e2ad626fSUlf Hansson }, 167*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_IPE] = { 168*e2ad626fSUlf Hansson .name = "ipe", 169*e2ad626fSUlf Hansson .sta_mask = BIT(14), 170*e2ad626fSUlf Hansson .ctl_offs = 0x0338, 171*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 172*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 173*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 174*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 175*e2ad626fSUlf Hansson .bp_infracfg = { 176*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, 177*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 178*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 179*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 180*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, 181*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 182*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 183*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 184*e2ad626fSUlf Hansson }, 185*e2ad626fSUlf Hansson }, 186*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_ISP] = { 187*e2ad626fSUlf Hansson .name = "isp", 188*e2ad626fSUlf Hansson .sta_mask = BIT(12), 189*e2ad626fSUlf Hansson .ctl_offs = 0x0330, 190*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 191*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 192*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 193*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 194*e2ad626fSUlf Hansson .bp_infracfg = { 195*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, 196*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 197*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 198*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 199*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, 200*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 201*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 202*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 203*e2ad626fSUlf Hansson }, 204*e2ad626fSUlf Hansson }, 205*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_ISP2] = { 206*e2ad626fSUlf Hansson .name = "isp2", 207*e2ad626fSUlf Hansson .sta_mask = BIT(13), 208*e2ad626fSUlf Hansson .ctl_offs = 0x0334, 209*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 210*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 211*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 212*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 213*e2ad626fSUlf Hansson .bp_infracfg = { 214*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, 215*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 216*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 217*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 218*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, 219*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 220*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 221*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 222*e2ad626fSUlf Hansson }, 223*e2ad626fSUlf Hansson }, 224*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_MDP] = { 225*e2ad626fSUlf Hansson .name = "mdp", 226*e2ad626fSUlf Hansson .sta_mask = BIT(19), 227*e2ad626fSUlf Hansson .ctl_offs = 0x034c, 228*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 229*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 230*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 231*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 232*e2ad626fSUlf Hansson .bp_infracfg = { 233*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, 234*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 235*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 236*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 237*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, 238*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_SET, 239*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_CLR, 240*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_2_STA1), 241*e2ad626fSUlf Hansson }, 242*e2ad626fSUlf Hansson }, 243*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_VENC] = { 244*e2ad626fSUlf Hansson .name = "venc", 245*e2ad626fSUlf Hansson .sta_mask = BIT(17), 246*e2ad626fSUlf Hansson .ctl_offs = 0x0344, 247*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 248*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 249*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 250*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 251*e2ad626fSUlf Hansson .bp_infracfg = { 252*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, 253*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 254*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 255*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 256*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, 257*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 258*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 259*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 260*e2ad626fSUlf Hansson }, 261*e2ad626fSUlf Hansson }, 262*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_VDEC] = { 263*e2ad626fSUlf Hansson .name = "vdec", 264*e2ad626fSUlf Hansson .sta_mask = BIT(15), 265*e2ad626fSUlf Hansson .ctl_offs = 0x033c, 266*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 267*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 268*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 269*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 270*e2ad626fSUlf Hansson .bp_infracfg = { 271*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, 272*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 273*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 274*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 275*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, 276*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 277*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 278*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 279*e2ad626fSUlf Hansson }, 280*e2ad626fSUlf Hansson }, 281*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_VDEC2] = { 282*e2ad626fSUlf Hansson .name = "vdec2", 283*e2ad626fSUlf Hansson .sta_mask = BIT(16), 284*e2ad626fSUlf Hansson .ctl_offs = 0x0340, 285*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 286*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 287*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 288*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 289*e2ad626fSUlf Hansson }, 290*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_CAM] = { 291*e2ad626fSUlf Hansson .name = "cam", 292*e2ad626fSUlf Hansson .sta_mask = BIT(23), 293*e2ad626fSUlf Hansson .ctl_offs = 0x035c, 294*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 295*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 296*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 297*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 298*e2ad626fSUlf Hansson .bp_infracfg = { 299*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, 300*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_SET, 301*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_CLR, 302*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_2_STA1), 303*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, 304*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 305*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 306*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 307*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, 308*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_SET, 309*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_CLR, 310*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_1_STA1), 311*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, 312*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_SET, 313*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_CLR, 314*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_MM_STA1), 315*e2ad626fSUlf Hansson BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, 316*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_VDNR_SET, 317*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_VDNR_CLR, 318*e2ad626fSUlf Hansson MT8192_TOP_AXI_PROT_EN_VDNR_STA1), 319*e2ad626fSUlf Hansson }, 320*e2ad626fSUlf Hansson }, 321*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_CAM_RAWA] = { 322*e2ad626fSUlf Hansson .name = "cam_rawa", 323*e2ad626fSUlf Hansson .sta_mask = BIT(24), 324*e2ad626fSUlf Hansson .ctl_offs = 0x0360, 325*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 326*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 327*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 328*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 329*e2ad626fSUlf Hansson }, 330*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_CAM_RAWB] = { 331*e2ad626fSUlf Hansson .name = "cam_rawb", 332*e2ad626fSUlf Hansson .sta_mask = BIT(25), 333*e2ad626fSUlf Hansson .ctl_offs = 0x0364, 334*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 335*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 336*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 337*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 338*e2ad626fSUlf Hansson }, 339*e2ad626fSUlf Hansson [MT8192_POWER_DOMAIN_CAM_RAWC] = { 340*e2ad626fSUlf Hansson .name = "cam_rawc", 341*e2ad626fSUlf Hansson .sta_mask = BIT(26), 342*e2ad626fSUlf Hansson .ctl_offs = 0x0368, 343*e2ad626fSUlf Hansson .pwr_sta_offs = 0x016c, 344*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0170, 345*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 346*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 347*e2ad626fSUlf Hansson }, 348*e2ad626fSUlf Hansson }; 349*e2ad626fSUlf Hansson 350*e2ad626fSUlf Hansson static const struct scpsys_soc_data mt8192_scpsys_data = { 351*e2ad626fSUlf Hansson .domains_data = scpsys_domain_data_mt8192, 352*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), 353*e2ad626fSUlf Hansson }; 354*e2ad626fSUlf Hansson 355*e2ad626fSUlf Hansson #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ 356