1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 8 #define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 9 10 #include "mtk-pm-domains.h" 11 #include <dt-bindings/power/mediatek,mt8188-power.h> 12 13 /* 14 * MT8188 power domain support 15 */ 16 17 static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { 18 [MT8188_POWER_DOMAIN_MFG0] = { 19 .name = "mfg0", 20 .sta_mask = BIT(1), 21 .ctl_offs = 0x300, 22 .pwr_sta_offs = 0x174, 23 .pwr_sta2nd_offs = 0x178, 24 .sram_pdn_bits = BIT(8), 25 .sram_pdn_ack_bits = BIT(12), 26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 27 }, 28 [MT8188_POWER_DOMAIN_MFG1] = { 29 .name = "mfg1", 30 .sta_mask = BIT(2), 31 .ctl_offs = 0x304, 32 .pwr_sta_offs = 0x174, 33 .pwr_sta2nd_offs = 0x178, 34 .sram_pdn_bits = BIT(8), 35 .sram_pdn_ack_bits = BIT(12), 36 .bp_cfg = { 37 BUS_PROT_WR(INFRA, 38 MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, 39 MT8188_TOP_AXI_PROT_EN_SET, 40 MT8188_TOP_AXI_PROT_EN_CLR, 41 MT8188_TOP_AXI_PROT_EN_STA), 42 BUS_PROT_WR(INFRA, 43 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, 44 MT8188_TOP_AXI_PROT_EN_2_SET, 45 MT8188_TOP_AXI_PROT_EN_2_CLR, 46 MT8188_TOP_AXI_PROT_EN_2_STA), 47 BUS_PROT_WR(INFRA, 48 MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, 49 MT8188_TOP_AXI_PROT_EN_1_SET, 50 MT8188_TOP_AXI_PROT_EN_1_CLR, 51 MT8188_TOP_AXI_PROT_EN_1_STA), 52 BUS_PROT_WR(INFRA, 53 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, 54 MT8188_TOP_AXI_PROT_EN_2_SET, 55 MT8188_TOP_AXI_PROT_EN_2_CLR, 56 MT8188_TOP_AXI_PROT_EN_2_STA), 57 BUS_PROT_WR(INFRA, 58 MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, 59 MT8188_TOP_AXI_PROT_EN_SET, 60 MT8188_TOP_AXI_PROT_EN_CLR, 61 MT8188_TOP_AXI_PROT_EN_STA), 62 BUS_PROT_WR(INFRA, 63 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, 64 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 65 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 66 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 67 }, 68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 69 }, 70 [MT8188_POWER_DOMAIN_MFG2] = { 71 .name = "mfg2", 72 .sta_mask = BIT(3), 73 .ctl_offs = 0x308, 74 .pwr_sta_offs = 0x174, 75 .pwr_sta2nd_offs = 0x178, 76 .sram_pdn_bits = BIT(8), 77 .sram_pdn_ack_bits = BIT(12), 78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 79 }, 80 [MT8188_POWER_DOMAIN_MFG3] = { 81 .name = "mfg3", 82 .sta_mask = BIT(4), 83 .ctl_offs = 0x30C, 84 .pwr_sta_offs = 0x174, 85 .pwr_sta2nd_offs = 0x178, 86 .sram_pdn_bits = BIT(8), 87 .sram_pdn_ack_bits = BIT(12), 88 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 89 }, 90 [MT8188_POWER_DOMAIN_MFG4] = { 91 .name = "mfg4", 92 .sta_mask = BIT(5), 93 .ctl_offs = 0x310, 94 .pwr_sta_offs = 0x174, 95 .pwr_sta2nd_offs = 0x178, 96 .sram_pdn_bits = BIT(8), 97 .sram_pdn_ack_bits = BIT(12), 98 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 99 }, 100 [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = { 101 .name = "pextp_mac_p0", 102 .sta_mask = BIT(10), 103 .ctl_offs = 0x324, 104 .pwr_sta_offs = 0x174, 105 .pwr_sta2nd_offs = 0x178, 106 .sram_pdn_bits = BIT(8), 107 .sram_pdn_ack_bits = BIT(12), 108 .bp_cfg = { 109 BUS_PROT_WR(INFRA, 110 MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, 111 MT8188_TOP_AXI_PROT_EN_SET, 112 MT8188_TOP_AXI_PROT_EN_CLR, 113 MT8188_TOP_AXI_PROT_EN_STA), 114 BUS_PROT_WR(INFRA, 115 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, 116 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 117 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 118 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 119 }, 120 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 121 }, 122 [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = { 123 .name = "pextp_phy_top", 124 .sta_mask = BIT(12), 125 .ctl_offs = 0x328, 126 .pwr_sta_offs = 0x174, 127 .pwr_sta2nd_offs = 0x178, 128 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 129 }, 130 [MT8188_POWER_DOMAIN_CSIRX_TOP] = { 131 .name = "pextp_csirx_top", 132 .sta_mask = BIT(17), 133 .ctl_offs = 0x3C4, 134 .pwr_sta_offs = 0x174, 135 .pwr_sta2nd_offs = 0x178, 136 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 137 }, 138 [MT8188_POWER_DOMAIN_ETHER] = { 139 .name = "ether", 140 .sta_mask = BIT(1), 141 .ctl_offs = 0x338, 142 .pwr_sta_offs = 0x16C, 143 .pwr_sta2nd_offs = 0x170, 144 .sram_pdn_bits = BIT(8), 145 .sram_pdn_ack_bits = BIT(12), 146 .bp_cfg = { 147 BUS_PROT_WR(INFRA, 148 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, 149 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 150 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 151 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 152 }, 153 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 154 }, 155 [MT8188_POWER_DOMAIN_HDMI_TX] = { 156 .name = "hdmi_tx", 157 .sta_mask = BIT(18), 158 .ctl_offs = 0x37C, 159 .pwr_sta_offs = 0x16C, 160 .pwr_sta2nd_offs = 0x170, 161 .sram_pdn_bits = BIT(8), 162 .sram_pdn_ack_bits = BIT(12), 163 .bp_cfg = { 164 BUS_PROT_WR(INFRA, 165 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, 166 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 167 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 168 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 169 }, 170 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 171 }, 172 [MT8188_POWER_DOMAIN_ADSP_AO] = { 173 .name = "adsp_ao", 174 .sta_mask = BIT(10), 175 .ctl_offs = 0x35C, 176 .pwr_sta_offs = 0x16C, 177 .pwr_sta2nd_offs = 0x170, 178 .ext_buck_iso_offs = 0x3EC, 179 .ext_buck_iso_mask = BIT(10), 180 .bp_cfg = { 181 BUS_PROT_WR(INFRA, 182 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, 183 MT8188_TOP_AXI_PROT_EN_2_SET, 184 MT8188_TOP_AXI_PROT_EN_2_CLR, 185 MT8188_TOP_AXI_PROT_EN_2_STA), 186 BUS_PROT_WR(INFRA, 187 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, 188 MT8188_TOP_AXI_PROT_EN_2_SET, 189 MT8188_TOP_AXI_PROT_EN_2_CLR, 190 MT8188_TOP_AXI_PROT_EN_2_STA), 191 }, 192 .caps = MTK_SCPD_ALWAYS_ON | MTK_SCPD_EXT_BUCK_ISO, 193 }, 194 [MT8188_POWER_DOMAIN_ADSP_INFRA] = { 195 .name = "adsp_infra", 196 .sta_mask = BIT(9), 197 .ctl_offs = 0x358, 198 .pwr_sta_offs = 0x16C, 199 .pwr_sta2nd_offs = 0x170, 200 .sram_pdn_bits = BIT(8), 201 .sram_pdn_ack_bits = BIT(12), 202 .bp_cfg = { 203 BUS_PROT_WR(INFRA, 204 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, 205 MT8188_TOP_AXI_PROT_EN_2_SET, 206 MT8188_TOP_AXI_PROT_EN_2_CLR, 207 MT8188_TOP_AXI_PROT_EN_2_STA), 208 BUS_PROT_WR(INFRA, 209 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, 210 MT8188_TOP_AXI_PROT_EN_2_SET, 211 MT8188_TOP_AXI_PROT_EN_2_CLR, 212 MT8188_TOP_AXI_PROT_EN_2_STA), 213 }, 214 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON, 215 }, 216 [MT8188_POWER_DOMAIN_ADSP] = { 217 .name = "adsp", 218 .sta_mask = BIT(8), 219 .ctl_offs = 0x354, 220 .pwr_sta_offs = 0x16C, 221 .pwr_sta2nd_offs = 0x170, 222 .sram_pdn_bits = BIT(8), 223 .sram_pdn_ack_bits = BIT(12), 224 .bp_cfg = { 225 BUS_PROT_WR(INFRA, 226 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, 227 MT8188_TOP_AXI_PROT_EN_2_SET, 228 MT8188_TOP_AXI_PROT_EN_2_CLR, 229 MT8188_TOP_AXI_PROT_EN_2_STA), 230 BUS_PROT_WR(INFRA, 231 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, 232 MT8188_TOP_AXI_PROT_EN_2_SET, 233 MT8188_TOP_AXI_PROT_EN_2_CLR, 234 MT8188_TOP_AXI_PROT_EN_2_STA), 235 }, 236 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 237 }, 238 [MT8188_POWER_DOMAIN_AUDIO] = { 239 .name = "audio", 240 .sta_mask = BIT(6), 241 .ctl_offs = 0x34C, 242 .pwr_sta_offs = 0x16C, 243 .pwr_sta2nd_offs = 0x170, 244 .sram_pdn_bits = BIT(8), 245 .sram_pdn_ack_bits = BIT(12), 246 .bp_cfg = { 247 BUS_PROT_WR(INFRA, 248 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, 249 MT8188_TOP_AXI_PROT_EN_2_SET, 250 MT8188_TOP_AXI_PROT_EN_2_CLR, 251 MT8188_TOP_AXI_PROT_EN_2_STA), 252 BUS_PROT_WR(INFRA, 253 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, 254 MT8188_TOP_AXI_PROT_EN_2_SET, 255 MT8188_TOP_AXI_PROT_EN_2_CLR, 256 MT8188_TOP_AXI_PROT_EN_2_STA), 257 }, 258 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 259 }, 260 [MT8188_POWER_DOMAIN_AUDIO_ASRC] = { 261 .name = "audio_asrc", 262 .sta_mask = BIT(7), 263 .ctl_offs = 0x350, 264 .pwr_sta_offs = 0x16C, 265 .pwr_sta2nd_offs = 0x170, 266 .sram_pdn_bits = BIT(8), 267 .sram_pdn_ack_bits = BIT(12), 268 .bp_cfg = { 269 BUS_PROT_WR(INFRA, 270 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, 271 MT8188_TOP_AXI_PROT_EN_2_SET, 272 MT8188_TOP_AXI_PROT_EN_2_CLR, 273 MT8188_TOP_AXI_PROT_EN_2_STA), 274 BUS_PROT_WR(INFRA, 275 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, 276 MT8188_TOP_AXI_PROT_EN_2_SET, 277 MT8188_TOP_AXI_PROT_EN_2_CLR, 278 MT8188_TOP_AXI_PROT_EN_2_STA), 279 }, 280 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 281 }, 282 [MT8188_POWER_DOMAIN_VPPSYS0] = { 283 .name = "vppsys0", 284 .sta_mask = BIT(11), 285 .ctl_offs = 0x360, 286 .pwr_sta_offs = 0x16C, 287 .pwr_sta2nd_offs = 0x170, 288 .sram_pdn_bits = BIT(8), 289 .sram_pdn_ack_bits = BIT(12), 290 .bp_cfg = { 291 BUS_PROT_WR(INFRA, 292 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, 293 MT8188_TOP_AXI_PROT_EN_SET, 294 MT8188_TOP_AXI_PROT_EN_CLR, 295 MT8188_TOP_AXI_PROT_EN_STA), 296 BUS_PROT_WR(INFRA, 297 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, 298 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 299 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 300 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 301 BUS_PROT_WR(INFRA, 302 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, 303 MT8188_TOP_AXI_PROT_EN_SET, 304 MT8188_TOP_AXI_PROT_EN_CLR, 305 MT8188_TOP_AXI_PROT_EN_STA), 306 BUS_PROT_WR(INFRA, 307 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, 308 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 309 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 310 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 311 BUS_PROT_WR(INFRA, 312 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, 313 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 314 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 315 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 316 }, 317 }, 318 [MT8188_POWER_DOMAIN_VDOSYS0] = { 319 .name = "vdosys0", 320 .sta_mask = BIT(13), 321 .ctl_offs = 0x368, 322 .pwr_sta_offs = 0x16C, 323 .pwr_sta2nd_offs = 0x170, 324 .sram_pdn_bits = BIT(8), 325 .sram_pdn_ack_bits = BIT(12), 326 .bp_cfg = { 327 BUS_PROT_WR(INFRA, 328 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, 329 MT8188_TOP_AXI_PROT_EN_MM_SET, 330 MT8188_TOP_AXI_PROT_EN_MM_CLR, 331 MT8188_TOP_AXI_PROT_EN_MM_STA), 332 BUS_PROT_WR(INFRA, 333 MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, 334 MT8188_TOP_AXI_PROT_EN_SET, 335 MT8188_TOP_AXI_PROT_EN_CLR, 336 MT8188_TOP_AXI_PROT_EN_STA), 337 BUS_PROT_WR(INFRA, 338 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, 339 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 340 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 341 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 342 }, 343 }, 344 [MT8188_POWER_DOMAIN_VDOSYS1] = { 345 .name = "vdosys1", 346 .sta_mask = BIT(14), 347 .ctl_offs = 0x36C, 348 .pwr_sta_offs = 0x16C, 349 .pwr_sta2nd_offs = 0x170, 350 .sram_pdn_bits = BIT(8), 351 .sram_pdn_ack_bits = BIT(12), 352 .bp_cfg = { 353 BUS_PROT_WR(INFRA, 354 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, 355 MT8188_TOP_AXI_PROT_EN_MM_SET, 356 MT8188_TOP_AXI_PROT_EN_MM_CLR, 357 MT8188_TOP_AXI_PROT_EN_MM_STA), 358 BUS_PROT_WR(INFRA, 359 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, 360 MT8188_TOP_AXI_PROT_EN_MM_SET, 361 MT8188_TOP_AXI_PROT_EN_MM_CLR, 362 MT8188_TOP_AXI_PROT_EN_MM_STA), 363 BUS_PROT_WR(INFRA, 364 MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, 365 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 366 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 367 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 368 }, 369 }, 370 [MT8188_POWER_DOMAIN_DP_TX] = { 371 .name = "dp_tx", 372 .sta_mask = BIT(16), 373 .ctl_offs = 0x374, 374 .pwr_sta_offs = 0x16C, 375 .pwr_sta2nd_offs = 0x170, 376 .sram_pdn_bits = BIT(8), 377 .sram_pdn_ack_bits = BIT(12), 378 .bp_cfg = { 379 BUS_PROT_WR(INFRA, 380 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, 381 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 382 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 383 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 384 }, 385 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 386 }, 387 [MT8188_POWER_DOMAIN_EDP_TX] = { 388 .name = "edp_tx", 389 .sta_mask = BIT(17), 390 .ctl_offs = 0x378, 391 .pwr_sta_offs = 0x16C, 392 .pwr_sta2nd_offs = 0x170, 393 .sram_pdn_bits = BIT(8), 394 .sram_pdn_ack_bits = BIT(12), 395 .bp_cfg = { 396 BUS_PROT_WR(INFRA, 397 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, 398 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 399 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 400 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 401 }, 402 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 403 }, 404 [MT8188_POWER_DOMAIN_VPPSYS1] = { 405 .name = "vppsys1", 406 .sta_mask = BIT(12), 407 .ctl_offs = 0x364, 408 .pwr_sta_offs = 0x16C, 409 .pwr_sta2nd_offs = 0x170, 410 .sram_pdn_bits = BIT(8), 411 .sram_pdn_ack_bits = BIT(12), 412 .bp_cfg = { 413 BUS_PROT_WR(INFRA, 414 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, 415 MT8188_TOP_AXI_PROT_EN_MM_SET, 416 MT8188_TOP_AXI_PROT_EN_MM_CLR, 417 MT8188_TOP_AXI_PROT_EN_MM_STA), 418 BUS_PROT_WR(INFRA, 419 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, 420 MT8188_TOP_AXI_PROT_EN_MM_SET, 421 MT8188_TOP_AXI_PROT_EN_MM_CLR, 422 MT8188_TOP_AXI_PROT_EN_MM_STA), 423 BUS_PROT_WR(INFRA, 424 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, 425 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 426 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 427 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 428 }, 429 }, 430 [MT8188_POWER_DOMAIN_WPE] = { 431 .name = "wpe", 432 .sta_mask = BIT(15), 433 .ctl_offs = 0x370, 434 .pwr_sta_offs = 0x16C, 435 .pwr_sta2nd_offs = 0x170, 436 .sram_pdn_bits = BIT(8), 437 .sram_pdn_ack_bits = BIT(12), 438 .bp_cfg = { 439 BUS_PROT_WR(INFRA, 440 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, 441 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 442 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 443 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 444 BUS_PROT_WR(INFRA, 445 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, 446 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 447 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 448 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 449 }, 450 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 451 }, 452 [MT8188_POWER_DOMAIN_VDEC0] = { 453 .name = "vdec0", 454 .sta_mask = BIT(19), 455 .ctl_offs = 0x380, 456 .pwr_sta_offs = 0x16C, 457 .pwr_sta2nd_offs = 0x170, 458 .sram_pdn_bits = BIT(8), 459 .sram_pdn_ack_bits = BIT(12), 460 .bp_cfg = { 461 BUS_PROT_WR(INFRA, 462 MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, 463 MT8188_TOP_AXI_PROT_EN_MM_SET, 464 MT8188_TOP_AXI_PROT_EN_MM_CLR, 465 MT8188_TOP_AXI_PROT_EN_MM_STA), 466 BUS_PROT_WR(INFRA, 467 MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, 468 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 469 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 470 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 471 }, 472 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 473 }, 474 [MT8188_POWER_DOMAIN_VDEC1] = { 475 .name = "vdec1", 476 .sta_mask = BIT(20), 477 .ctl_offs = 0x384, 478 .pwr_sta_offs = 0x16C, 479 .pwr_sta2nd_offs = 0x170, 480 .sram_pdn_bits = BIT(8), 481 .sram_pdn_ack_bits = BIT(12), 482 .bp_cfg = { 483 BUS_PROT_WR(INFRA, 484 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, 485 MT8188_TOP_AXI_PROT_EN_MM_SET, 486 MT8188_TOP_AXI_PROT_EN_MM_CLR, 487 MT8188_TOP_AXI_PROT_EN_MM_STA), 488 BUS_PROT_WR(INFRA, 489 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, 490 MT8188_TOP_AXI_PROT_EN_MM_SET, 491 MT8188_TOP_AXI_PROT_EN_MM_CLR, 492 MT8188_TOP_AXI_PROT_EN_MM_STA), 493 }, 494 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 495 }, 496 [MT8188_POWER_DOMAIN_VENC] = { 497 .name = "venc", 498 .sta_mask = BIT(22), 499 .ctl_offs = 0x38C, 500 .pwr_sta_offs = 0x16C, 501 .pwr_sta2nd_offs = 0x170, 502 .sram_pdn_bits = BIT(8), 503 .sram_pdn_ack_bits = BIT(12), 504 .bp_cfg = { 505 BUS_PROT_WR(INFRA, 506 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, 507 MT8188_TOP_AXI_PROT_EN_MM_SET, 508 MT8188_TOP_AXI_PROT_EN_MM_CLR, 509 MT8188_TOP_AXI_PROT_EN_MM_STA), 510 BUS_PROT_WR(INFRA, 511 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, 512 MT8188_TOP_AXI_PROT_EN_MM_SET, 513 MT8188_TOP_AXI_PROT_EN_MM_CLR, 514 MT8188_TOP_AXI_PROT_EN_MM_STA), 515 BUS_PROT_WR(INFRA, 516 MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, 517 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 518 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 519 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 520 }, 521 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 522 }, 523 [MT8188_POWER_DOMAIN_IMG_VCORE] = { 524 .name = "vcore", 525 .sta_mask = BIT(28), 526 .ctl_offs = 0x3A4, 527 .pwr_sta_offs = 0x16C, 528 .pwr_sta2nd_offs = 0x170, 529 .ext_buck_iso_offs = 0x3EC, 530 .ext_buck_iso_mask = BIT(12), 531 .bp_cfg = { 532 BUS_PROT_WR(INFRA, 533 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, 534 MT8188_TOP_AXI_PROT_EN_MM_SET, 535 MT8188_TOP_AXI_PROT_EN_MM_CLR, 536 MT8188_TOP_AXI_PROT_EN_MM_STA), 537 BUS_PROT_WR(INFRA, 538 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, 539 MT8188_TOP_AXI_PROT_EN_MM_SET, 540 MT8188_TOP_AXI_PROT_EN_MM_CLR, 541 MT8188_TOP_AXI_PROT_EN_MM_STA), 542 BUS_PROT_WR(INFRA, 543 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, 544 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 545 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 546 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 547 }, 548 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY | 549 MTK_SCPD_EXT_BUCK_ISO, 550 }, 551 [MT8188_POWER_DOMAIN_IMG_MAIN] = { 552 .name = "img_main", 553 .sta_mask = BIT(29), 554 .ctl_offs = 0x3A8, 555 .pwr_sta_offs = 0x16C, 556 .pwr_sta2nd_offs = 0x170, 557 .sram_pdn_bits = BIT(8), 558 .sram_pdn_ack_bits = BIT(12), 559 .bp_cfg = { 560 BUS_PROT_WR(INFRA, 561 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, 562 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 563 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 564 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 565 BUS_PROT_WR(INFRA, 566 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, 567 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 568 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 569 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 570 }, 571 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 572 }, 573 [MT8188_POWER_DOMAIN_DIP] = { 574 .name = "dip", 575 .sta_mask = BIT(30), 576 .ctl_offs = 0x3AC, 577 .pwr_sta_offs = 0x16C, 578 .pwr_sta2nd_offs = 0x170, 579 .sram_pdn_bits = BIT(8), 580 .sram_pdn_ack_bits = BIT(12), 581 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 582 }, 583 [MT8188_POWER_DOMAIN_IPE] = { 584 .name = "ipe", 585 .sta_mask = BIT(31), 586 .ctl_offs = 0x3B0, 587 .pwr_sta_offs = 0x16C, 588 .pwr_sta2nd_offs = 0x170, 589 .sram_pdn_bits = BIT(8), 590 .sram_pdn_ack_bits = BIT(12), 591 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 592 }, 593 [MT8188_POWER_DOMAIN_CAM_VCORE] = { 594 .name = "cam_vcore", 595 .sta_mask = BIT(27), 596 .ctl_offs = 0x3A0, 597 .pwr_sta_offs = 0x16C, 598 .pwr_sta2nd_offs = 0x170, 599 .ext_buck_iso_offs = 0x3EC, 600 .ext_buck_iso_mask = BIT(11), 601 .bp_cfg = { 602 BUS_PROT_WR(INFRA, 603 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, 604 MT8188_TOP_AXI_PROT_EN_MM_SET, 605 MT8188_TOP_AXI_PROT_EN_MM_CLR, 606 MT8188_TOP_AXI_PROT_EN_MM_STA), 607 BUS_PROT_WR(INFRA, 608 MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, 609 MT8188_TOP_AXI_PROT_EN_2_SET, 610 MT8188_TOP_AXI_PROT_EN_2_CLR, 611 MT8188_TOP_AXI_PROT_EN_2_STA), 612 BUS_PROT_WR(INFRA, 613 MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, 614 MT8188_TOP_AXI_PROT_EN_1_SET, 615 MT8188_TOP_AXI_PROT_EN_1_CLR, 616 MT8188_TOP_AXI_PROT_EN_1_STA), 617 BUS_PROT_WR(INFRA, 618 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, 619 MT8188_TOP_AXI_PROT_EN_MM_SET, 620 MT8188_TOP_AXI_PROT_EN_MM_CLR, 621 MT8188_TOP_AXI_PROT_EN_MM_STA), 622 BUS_PROT_WR(INFRA, 623 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, 624 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 625 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 626 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 627 }, 628 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY | 629 MTK_SCPD_EXT_BUCK_ISO, 630 }, 631 [MT8188_POWER_DOMAIN_CAM_MAIN] = { 632 .name = "cam_main", 633 .sta_mask = BIT(24), 634 .ctl_offs = 0x394, 635 .pwr_sta_offs = 0x16C, 636 .pwr_sta2nd_offs = 0x170, 637 .sram_pdn_bits = BIT(8), 638 .sram_pdn_ack_bits = BIT(12), 639 .bp_cfg = { 640 BUS_PROT_WR(INFRA, 641 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, 642 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 643 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 644 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 645 BUS_PROT_WR(INFRA, 646 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, 647 MT8188_TOP_AXI_PROT_EN_2_SET, 648 MT8188_TOP_AXI_PROT_EN_2_CLR, 649 MT8188_TOP_AXI_PROT_EN_2_STA), 650 BUS_PROT_WR(INFRA, 651 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, 652 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 653 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 654 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 655 BUS_PROT_WR(INFRA, 656 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, 657 MT8188_TOP_AXI_PROT_EN_2_SET, 658 MT8188_TOP_AXI_PROT_EN_2_CLR, 659 MT8188_TOP_AXI_PROT_EN_2_STA), 660 }, 661 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 662 }, 663 [MT8188_POWER_DOMAIN_CAM_SUBA] = { 664 .name = "cam_suba", 665 .sta_mask = BIT(25), 666 .ctl_offs = 0x398, 667 .pwr_sta_offs = 0x16C, 668 .pwr_sta2nd_offs = 0x170, 669 .sram_pdn_bits = BIT(8), 670 .sram_pdn_ack_bits = BIT(12), 671 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 672 }, 673 [MT8188_POWER_DOMAIN_CAM_SUBB] = { 674 .name = "cam_subb", 675 .sta_mask = BIT(26), 676 .ctl_offs = 0x39C, 677 .pwr_sta_offs = 0x16C, 678 .pwr_sta2nd_offs = 0x170, 679 .sram_pdn_bits = BIT(8), 680 .sram_pdn_ack_bits = BIT(12), 681 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 682 }, 683 }; 684 685 static const struct scpsys_soc_data mt8188_scpsys_data = { 686 .domains_data = scpsys_domain_data_mt8188, 687 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188), 688 }; 689 690 #endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */ 691