1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Garmin Chang <garmin.chang@mediatek.com> 5 */ 6 7 #ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 8 #define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H 9 10 #include "mtk-pm-domains.h" 11 #include <dt-bindings/power/mediatek,mt8188-power.h> 12 13 /* 14 * MT8188 power domain support 15 */ 16 17 static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = { 18 [MT8188_POWER_DOMAIN_MFG0] = { 19 .name = "mfg0", 20 .sta_mask = BIT(1), 21 .ctl_offs = 0x300, 22 .pwr_sta_offs = 0x174, 23 .pwr_sta2nd_offs = 0x178, 24 .sram_pdn_bits = BIT(8), 25 .sram_pdn_ack_bits = BIT(12), 26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 27 }, 28 [MT8188_POWER_DOMAIN_MFG1] = { 29 .name = "mfg1", 30 .sta_mask = BIT(2), 31 .ctl_offs = 0x304, 32 .pwr_sta_offs = 0x174, 33 .pwr_sta2nd_offs = 0x178, 34 .sram_pdn_bits = BIT(8), 35 .sram_pdn_ack_bits = BIT(12), 36 .bp_cfg = { 37 BUS_PROT_WR(INFRA, 38 MT8188_TOP_AXI_PROT_EN_MFG1_STEP1, 39 MT8188_TOP_AXI_PROT_EN_SET, 40 MT8188_TOP_AXI_PROT_EN_CLR, 41 MT8188_TOP_AXI_PROT_EN_STA), 42 BUS_PROT_WR(INFRA, 43 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2, 44 MT8188_TOP_AXI_PROT_EN_2_SET, 45 MT8188_TOP_AXI_PROT_EN_2_CLR, 46 MT8188_TOP_AXI_PROT_EN_2_STA), 47 BUS_PROT_WR(INFRA, 48 MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3, 49 MT8188_TOP_AXI_PROT_EN_1_SET, 50 MT8188_TOP_AXI_PROT_EN_1_CLR, 51 MT8188_TOP_AXI_PROT_EN_1_STA), 52 BUS_PROT_WR(INFRA, 53 MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4, 54 MT8188_TOP_AXI_PROT_EN_2_SET, 55 MT8188_TOP_AXI_PROT_EN_2_CLR, 56 MT8188_TOP_AXI_PROT_EN_2_STA), 57 BUS_PROT_WR(INFRA, 58 MT8188_TOP_AXI_PROT_EN_MFG1_STEP5, 59 MT8188_TOP_AXI_PROT_EN_SET, 60 MT8188_TOP_AXI_PROT_EN_CLR, 61 MT8188_TOP_AXI_PROT_EN_STA), 62 BUS_PROT_WR(INFRA, 63 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6, 64 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 65 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 66 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 67 }, 68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 69 }, 70 [MT8188_POWER_DOMAIN_MFG2] = { 71 .name = "mfg2", 72 .sta_mask = BIT(3), 73 .ctl_offs = 0x308, 74 .pwr_sta_offs = 0x174, 75 .pwr_sta2nd_offs = 0x178, 76 .sram_pdn_bits = BIT(8), 77 .sram_pdn_ack_bits = BIT(12), 78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 79 }, 80 [MT8188_POWER_DOMAIN_MFG3] = { 81 .name = "mfg3", 82 .sta_mask = BIT(4), 83 .ctl_offs = 0x30C, 84 .pwr_sta_offs = 0x174, 85 .pwr_sta2nd_offs = 0x178, 86 .sram_pdn_bits = BIT(8), 87 .sram_pdn_ack_bits = BIT(12), 88 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 89 }, 90 [MT8188_POWER_DOMAIN_MFG4] = { 91 .name = "mfg4", 92 .sta_mask = BIT(5), 93 .ctl_offs = 0x310, 94 .pwr_sta_offs = 0x174, 95 .pwr_sta2nd_offs = 0x178, 96 .sram_pdn_bits = BIT(8), 97 .sram_pdn_ack_bits = BIT(12), 98 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 99 }, 100 [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = { 101 .name = "pextp_mac_p0", 102 .sta_mask = BIT(10), 103 .ctl_offs = 0x324, 104 .pwr_sta_offs = 0x174, 105 .pwr_sta2nd_offs = 0x178, 106 .sram_pdn_bits = BIT(8), 107 .sram_pdn_ack_bits = BIT(12), 108 .bp_cfg = { 109 BUS_PROT_WR(INFRA, 110 MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1, 111 MT8188_TOP_AXI_PROT_EN_SET, 112 MT8188_TOP_AXI_PROT_EN_CLR, 113 MT8188_TOP_AXI_PROT_EN_STA), 114 BUS_PROT_WR(INFRA, 115 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2, 116 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 117 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 118 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 119 }, 120 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 121 }, 122 [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = { 123 .name = "pextp_phy_top", 124 .sta_mask = BIT(12), 125 .ctl_offs = 0x328, 126 .pwr_sta_offs = 0x174, 127 .pwr_sta2nd_offs = 0x178, 128 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 129 }, 130 [MT8188_POWER_DOMAIN_CSIRX_TOP] = { 131 .name = "pextp_csirx_top", 132 .sta_mask = BIT(17), 133 .ctl_offs = 0x3C4, 134 .pwr_sta_offs = 0x174, 135 .pwr_sta2nd_offs = 0x178, 136 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 137 }, 138 [MT8188_POWER_DOMAIN_ETHER] = { 139 .name = "ether", 140 .sta_mask = BIT(1), 141 .ctl_offs = 0x338, 142 .pwr_sta_offs = 0x16C, 143 .pwr_sta2nd_offs = 0x170, 144 .sram_pdn_bits = BIT(8), 145 .sram_pdn_ack_bits = BIT(12), 146 .bp_cfg = { 147 BUS_PROT_WR(INFRA, 148 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1, 149 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 150 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 151 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 152 }, 153 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 154 }, 155 [MT8188_POWER_DOMAIN_HDMI_TX] = { 156 .name = "hdmi_tx", 157 .sta_mask = BIT(18), 158 .ctl_offs = 0x37C, 159 .pwr_sta_offs = 0x16C, 160 .pwr_sta2nd_offs = 0x170, 161 .sram_pdn_bits = BIT(8), 162 .sram_pdn_ack_bits = BIT(12), 163 .bp_cfg = { 164 BUS_PROT_WR(INFRA, 165 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1, 166 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 167 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 168 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 169 }, 170 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 171 }, 172 [MT8188_POWER_DOMAIN_ADSP_AO] = { 173 .name = "adsp_ao", 174 .sta_mask = BIT(10), 175 .ctl_offs = 0x35C, 176 .pwr_sta_offs = 0x16C, 177 .pwr_sta2nd_offs = 0x170, 178 .bp_cfg = { 179 BUS_PROT_WR(INFRA, 180 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1, 181 MT8188_TOP_AXI_PROT_EN_2_SET, 182 MT8188_TOP_AXI_PROT_EN_2_CLR, 183 MT8188_TOP_AXI_PROT_EN_2_STA), 184 BUS_PROT_WR(INFRA, 185 MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2, 186 MT8188_TOP_AXI_PROT_EN_2_SET, 187 MT8188_TOP_AXI_PROT_EN_2_CLR, 188 MT8188_TOP_AXI_PROT_EN_2_STA), 189 }, 190 .caps = MTK_SCPD_ALWAYS_ON, 191 }, 192 [MT8188_POWER_DOMAIN_ADSP_INFRA] = { 193 .name = "adsp_infra", 194 .sta_mask = BIT(9), 195 .ctl_offs = 0x358, 196 .pwr_sta_offs = 0x16C, 197 .pwr_sta2nd_offs = 0x170, 198 .sram_pdn_bits = BIT(8), 199 .sram_pdn_ack_bits = BIT(12), 200 .bp_cfg = { 201 BUS_PROT_WR(INFRA, 202 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1, 203 MT8188_TOP_AXI_PROT_EN_2_SET, 204 MT8188_TOP_AXI_PROT_EN_2_CLR, 205 MT8188_TOP_AXI_PROT_EN_2_STA), 206 BUS_PROT_WR(INFRA, 207 MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2, 208 MT8188_TOP_AXI_PROT_EN_2_SET, 209 MT8188_TOP_AXI_PROT_EN_2_CLR, 210 MT8188_TOP_AXI_PROT_EN_2_STA), 211 }, 212 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ALWAYS_ON, 213 }, 214 [MT8188_POWER_DOMAIN_ADSP] = { 215 .name = "adsp", 216 .sta_mask = BIT(8), 217 .ctl_offs = 0x354, 218 .pwr_sta_offs = 0x16C, 219 .pwr_sta2nd_offs = 0x170, 220 .sram_pdn_bits = BIT(8), 221 .sram_pdn_ack_bits = BIT(12), 222 .bp_cfg = { 223 BUS_PROT_WR(INFRA, 224 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1, 225 MT8188_TOP_AXI_PROT_EN_2_SET, 226 MT8188_TOP_AXI_PROT_EN_2_CLR, 227 MT8188_TOP_AXI_PROT_EN_2_STA), 228 BUS_PROT_WR(INFRA, 229 MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2, 230 MT8188_TOP_AXI_PROT_EN_2_SET, 231 MT8188_TOP_AXI_PROT_EN_2_CLR, 232 MT8188_TOP_AXI_PROT_EN_2_STA), 233 }, 234 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 235 }, 236 [MT8188_POWER_DOMAIN_AUDIO] = { 237 .name = "audio", 238 .sta_mask = BIT(6), 239 .ctl_offs = 0x34C, 240 .pwr_sta_offs = 0x16C, 241 .pwr_sta2nd_offs = 0x170, 242 .sram_pdn_bits = BIT(8), 243 .sram_pdn_ack_bits = BIT(12), 244 .bp_cfg = { 245 BUS_PROT_WR(INFRA, 246 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1, 247 MT8188_TOP_AXI_PROT_EN_2_SET, 248 MT8188_TOP_AXI_PROT_EN_2_CLR, 249 MT8188_TOP_AXI_PROT_EN_2_STA), 250 BUS_PROT_WR(INFRA, 251 MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2, 252 MT8188_TOP_AXI_PROT_EN_2_SET, 253 MT8188_TOP_AXI_PROT_EN_2_CLR, 254 MT8188_TOP_AXI_PROT_EN_2_STA), 255 }, 256 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 257 }, 258 [MT8188_POWER_DOMAIN_AUDIO_ASRC] = { 259 .name = "audio_asrc", 260 .sta_mask = BIT(7), 261 .ctl_offs = 0x350, 262 .pwr_sta_offs = 0x16C, 263 .pwr_sta2nd_offs = 0x170, 264 .sram_pdn_bits = BIT(8), 265 .sram_pdn_ack_bits = BIT(12), 266 .bp_cfg = { 267 BUS_PROT_WR(INFRA, 268 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1, 269 MT8188_TOP_AXI_PROT_EN_2_SET, 270 MT8188_TOP_AXI_PROT_EN_2_CLR, 271 MT8188_TOP_AXI_PROT_EN_2_STA), 272 BUS_PROT_WR(INFRA, 273 MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2, 274 MT8188_TOP_AXI_PROT_EN_2_SET, 275 MT8188_TOP_AXI_PROT_EN_2_CLR, 276 MT8188_TOP_AXI_PROT_EN_2_STA), 277 }, 278 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 279 }, 280 [MT8188_POWER_DOMAIN_VPPSYS0] = { 281 .name = "vppsys0", 282 .sta_mask = BIT(11), 283 .ctl_offs = 0x360, 284 .pwr_sta_offs = 0x16C, 285 .pwr_sta2nd_offs = 0x170, 286 .sram_pdn_bits = BIT(8), 287 .sram_pdn_ack_bits = BIT(12), 288 .bp_cfg = { 289 BUS_PROT_WR(INFRA, 290 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1, 291 MT8188_TOP_AXI_PROT_EN_SET, 292 MT8188_TOP_AXI_PROT_EN_CLR, 293 MT8188_TOP_AXI_PROT_EN_STA), 294 BUS_PROT_WR(INFRA, 295 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2, 296 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 297 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 298 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 299 BUS_PROT_WR(INFRA, 300 MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3, 301 MT8188_TOP_AXI_PROT_EN_SET, 302 MT8188_TOP_AXI_PROT_EN_CLR, 303 MT8188_TOP_AXI_PROT_EN_STA), 304 BUS_PROT_WR(INFRA, 305 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4, 306 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 307 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 308 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 309 BUS_PROT_WR(INFRA, 310 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5, 311 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 312 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 313 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 314 }, 315 }, 316 [MT8188_POWER_DOMAIN_VDOSYS0] = { 317 .name = "vdosys0", 318 .sta_mask = BIT(13), 319 .ctl_offs = 0x368, 320 .pwr_sta_offs = 0x16C, 321 .pwr_sta2nd_offs = 0x170, 322 .sram_pdn_bits = BIT(8), 323 .sram_pdn_ack_bits = BIT(12), 324 .bp_cfg = { 325 BUS_PROT_WR(INFRA, 326 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1, 327 MT8188_TOP_AXI_PROT_EN_MM_SET, 328 MT8188_TOP_AXI_PROT_EN_MM_CLR, 329 MT8188_TOP_AXI_PROT_EN_MM_STA), 330 BUS_PROT_WR(INFRA, 331 MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2, 332 MT8188_TOP_AXI_PROT_EN_SET, 333 MT8188_TOP_AXI_PROT_EN_CLR, 334 MT8188_TOP_AXI_PROT_EN_STA), 335 BUS_PROT_WR(INFRA, 336 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3, 337 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, 338 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, 339 MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA), 340 }, 341 }, 342 [MT8188_POWER_DOMAIN_VDOSYS1] = { 343 .name = "vdosys1", 344 .sta_mask = BIT(14), 345 .ctl_offs = 0x36C, 346 .pwr_sta_offs = 0x16C, 347 .pwr_sta2nd_offs = 0x170, 348 .sram_pdn_bits = BIT(8), 349 .sram_pdn_ack_bits = BIT(12), 350 .bp_cfg = { 351 BUS_PROT_WR(INFRA, 352 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1, 353 MT8188_TOP_AXI_PROT_EN_MM_SET, 354 MT8188_TOP_AXI_PROT_EN_MM_CLR, 355 MT8188_TOP_AXI_PROT_EN_MM_STA), 356 BUS_PROT_WR(INFRA, 357 MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2, 358 MT8188_TOP_AXI_PROT_EN_MM_SET, 359 MT8188_TOP_AXI_PROT_EN_MM_CLR, 360 MT8188_TOP_AXI_PROT_EN_MM_STA), 361 BUS_PROT_WR(INFRA, 362 MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3, 363 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 364 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 365 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 366 }, 367 }, 368 [MT8188_POWER_DOMAIN_DP_TX] = { 369 .name = "dp_tx", 370 .sta_mask = BIT(16), 371 .ctl_offs = 0x374, 372 .pwr_sta_offs = 0x16C, 373 .pwr_sta2nd_offs = 0x170, 374 .sram_pdn_bits = BIT(8), 375 .sram_pdn_ack_bits = BIT(12), 376 .bp_cfg = { 377 BUS_PROT_WR(INFRA, 378 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1, 379 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 380 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 381 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 382 }, 383 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 384 }, 385 [MT8188_POWER_DOMAIN_EDP_TX] = { 386 .name = "edp_tx", 387 .sta_mask = BIT(17), 388 .ctl_offs = 0x378, 389 .pwr_sta_offs = 0x16C, 390 .pwr_sta2nd_offs = 0x170, 391 .sram_pdn_bits = BIT(8), 392 .sram_pdn_ack_bits = BIT(12), 393 .bp_cfg = { 394 BUS_PROT_WR(INFRA, 395 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1, 396 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET, 397 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR, 398 MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA), 399 }, 400 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 401 }, 402 [MT8188_POWER_DOMAIN_VPPSYS1] = { 403 .name = "vppsys1", 404 .sta_mask = BIT(12), 405 .ctl_offs = 0x364, 406 .pwr_sta_offs = 0x16C, 407 .pwr_sta2nd_offs = 0x170, 408 .sram_pdn_bits = BIT(8), 409 .sram_pdn_ack_bits = BIT(12), 410 .bp_cfg = { 411 BUS_PROT_WR(INFRA, 412 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1, 413 MT8188_TOP_AXI_PROT_EN_MM_SET, 414 MT8188_TOP_AXI_PROT_EN_MM_CLR, 415 MT8188_TOP_AXI_PROT_EN_MM_STA), 416 BUS_PROT_WR(INFRA, 417 MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2, 418 MT8188_TOP_AXI_PROT_EN_MM_SET, 419 MT8188_TOP_AXI_PROT_EN_MM_CLR, 420 MT8188_TOP_AXI_PROT_EN_MM_STA), 421 BUS_PROT_WR(INFRA, 422 MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3, 423 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 424 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 425 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 426 }, 427 }, 428 [MT8188_POWER_DOMAIN_WPE] = { 429 .name = "wpe", 430 .sta_mask = BIT(15), 431 .ctl_offs = 0x370, 432 .pwr_sta_offs = 0x16C, 433 .pwr_sta2nd_offs = 0x170, 434 .sram_pdn_bits = BIT(8), 435 .sram_pdn_ack_bits = BIT(12), 436 .bp_cfg = { 437 BUS_PROT_WR(INFRA, 438 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1, 439 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 440 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 441 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 442 BUS_PROT_WR(INFRA, 443 MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2, 444 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 445 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 446 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 447 }, 448 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 449 }, 450 [MT8188_POWER_DOMAIN_VDEC0] = { 451 .name = "vdec0", 452 .sta_mask = BIT(19), 453 .ctl_offs = 0x380, 454 .pwr_sta_offs = 0x16C, 455 .pwr_sta2nd_offs = 0x170, 456 .sram_pdn_bits = BIT(8), 457 .sram_pdn_ack_bits = BIT(12), 458 .bp_cfg = { 459 BUS_PROT_WR(INFRA, 460 MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1, 461 MT8188_TOP_AXI_PROT_EN_MM_SET, 462 MT8188_TOP_AXI_PROT_EN_MM_CLR, 463 MT8188_TOP_AXI_PROT_EN_MM_STA), 464 BUS_PROT_WR(INFRA, 465 MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2, 466 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 467 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 468 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 469 }, 470 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 471 }, 472 [MT8188_POWER_DOMAIN_VDEC1] = { 473 .name = "vdec1", 474 .sta_mask = BIT(20), 475 .ctl_offs = 0x384, 476 .pwr_sta_offs = 0x16C, 477 .pwr_sta2nd_offs = 0x170, 478 .sram_pdn_bits = BIT(8), 479 .sram_pdn_ack_bits = BIT(12), 480 .bp_cfg = { 481 BUS_PROT_WR(INFRA, 482 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1, 483 MT8188_TOP_AXI_PROT_EN_MM_SET, 484 MT8188_TOP_AXI_PROT_EN_MM_CLR, 485 MT8188_TOP_AXI_PROT_EN_MM_STA), 486 BUS_PROT_WR(INFRA, 487 MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2, 488 MT8188_TOP_AXI_PROT_EN_MM_SET, 489 MT8188_TOP_AXI_PROT_EN_MM_CLR, 490 MT8188_TOP_AXI_PROT_EN_MM_STA), 491 }, 492 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 493 }, 494 [MT8188_POWER_DOMAIN_VENC] = { 495 .name = "venc", 496 .sta_mask = BIT(22), 497 .ctl_offs = 0x38C, 498 .pwr_sta_offs = 0x16C, 499 .pwr_sta2nd_offs = 0x170, 500 .sram_pdn_bits = BIT(8), 501 .sram_pdn_ack_bits = BIT(12), 502 .bp_cfg = { 503 BUS_PROT_WR(INFRA, 504 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1, 505 MT8188_TOP_AXI_PROT_EN_MM_SET, 506 MT8188_TOP_AXI_PROT_EN_MM_CLR, 507 MT8188_TOP_AXI_PROT_EN_MM_STA), 508 BUS_PROT_WR(INFRA, 509 MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2, 510 MT8188_TOP_AXI_PROT_EN_MM_SET, 511 MT8188_TOP_AXI_PROT_EN_MM_CLR, 512 MT8188_TOP_AXI_PROT_EN_MM_STA), 513 BUS_PROT_WR(INFRA, 514 MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3, 515 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 516 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 517 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 518 }, 519 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 520 }, 521 [MT8188_POWER_DOMAIN_IMG_VCORE] = { 522 .name = "vcore", 523 .sta_mask = BIT(28), 524 .ctl_offs = 0x3A4, 525 .pwr_sta_offs = 0x16C, 526 .pwr_sta2nd_offs = 0x170, 527 .bp_cfg = { 528 BUS_PROT_WR(INFRA, 529 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1, 530 MT8188_TOP_AXI_PROT_EN_MM_SET, 531 MT8188_TOP_AXI_PROT_EN_MM_CLR, 532 MT8188_TOP_AXI_PROT_EN_MM_STA), 533 BUS_PROT_WR(INFRA, 534 MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2, 535 MT8188_TOP_AXI_PROT_EN_MM_SET, 536 MT8188_TOP_AXI_PROT_EN_MM_CLR, 537 MT8188_TOP_AXI_PROT_EN_MM_STA), 538 BUS_PROT_WR(INFRA, 539 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3, 540 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 541 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 542 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 543 }, 544 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 545 }, 546 [MT8188_POWER_DOMAIN_IMG_MAIN] = { 547 .name = "img_main", 548 .sta_mask = BIT(29), 549 .ctl_offs = 0x3A8, 550 .pwr_sta_offs = 0x16C, 551 .pwr_sta2nd_offs = 0x170, 552 .sram_pdn_bits = BIT(8), 553 .sram_pdn_ack_bits = BIT(12), 554 .bp_cfg = { 555 BUS_PROT_WR(INFRA, 556 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1, 557 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 558 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 559 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 560 BUS_PROT_WR(INFRA, 561 MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2, 562 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 563 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 564 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 565 }, 566 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 567 }, 568 [MT8188_POWER_DOMAIN_DIP] = { 569 .name = "dip", 570 .sta_mask = BIT(30), 571 .ctl_offs = 0x3AC, 572 .pwr_sta_offs = 0x16C, 573 .pwr_sta2nd_offs = 0x170, 574 .sram_pdn_bits = BIT(8), 575 .sram_pdn_ack_bits = BIT(12), 576 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 577 }, 578 [MT8188_POWER_DOMAIN_IPE] = { 579 .name = "ipe", 580 .sta_mask = BIT(31), 581 .ctl_offs = 0x3B0, 582 .pwr_sta_offs = 0x16C, 583 .pwr_sta2nd_offs = 0x170, 584 .sram_pdn_bits = BIT(8), 585 .sram_pdn_ack_bits = BIT(12), 586 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 587 }, 588 [MT8188_POWER_DOMAIN_CAM_VCORE] = { 589 .name = "cam_vcore", 590 .sta_mask = BIT(27), 591 .ctl_offs = 0x3A0, 592 .pwr_sta_offs = 0x16C, 593 .pwr_sta2nd_offs = 0x170, 594 .bp_cfg = { 595 BUS_PROT_WR(INFRA, 596 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1, 597 MT8188_TOP_AXI_PROT_EN_MM_SET, 598 MT8188_TOP_AXI_PROT_EN_MM_CLR, 599 MT8188_TOP_AXI_PROT_EN_MM_STA), 600 BUS_PROT_WR(INFRA, 601 MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2, 602 MT8188_TOP_AXI_PROT_EN_2_SET, 603 MT8188_TOP_AXI_PROT_EN_2_CLR, 604 MT8188_TOP_AXI_PROT_EN_2_STA), 605 BUS_PROT_WR(INFRA, 606 MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3, 607 MT8188_TOP_AXI_PROT_EN_1_SET, 608 MT8188_TOP_AXI_PROT_EN_1_CLR, 609 MT8188_TOP_AXI_PROT_EN_1_STA), 610 BUS_PROT_WR(INFRA, 611 MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4, 612 MT8188_TOP_AXI_PROT_EN_MM_SET, 613 MT8188_TOP_AXI_PROT_EN_MM_CLR, 614 MT8188_TOP_AXI_PROT_EN_MM_STA), 615 BUS_PROT_WR(INFRA, 616 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5, 617 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 618 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 619 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 620 }, 621 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 622 }, 623 [MT8188_POWER_DOMAIN_CAM_MAIN] = { 624 .name = "cam_main", 625 .sta_mask = BIT(24), 626 .ctl_offs = 0x394, 627 .pwr_sta_offs = 0x16C, 628 .pwr_sta2nd_offs = 0x170, 629 .sram_pdn_bits = BIT(8), 630 .sram_pdn_ack_bits = BIT(12), 631 .bp_cfg = { 632 BUS_PROT_WR(INFRA, 633 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1, 634 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 635 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 636 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 637 BUS_PROT_WR(INFRA, 638 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2, 639 MT8188_TOP_AXI_PROT_EN_2_SET, 640 MT8188_TOP_AXI_PROT_EN_2_CLR, 641 MT8188_TOP_AXI_PROT_EN_2_STA), 642 BUS_PROT_WR(INFRA, 643 MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3, 644 MT8188_TOP_AXI_PROT_EN_MM_2_SET, 645 MT8188_TOP_AXI_PROT_EN_MM_2_CLR, 646 MT8188_TOP_AXI_PROT_EN_MM_2_STA), 647 BUS_PROT_WR(INFRA, 648 MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4, 649 MT8188_TOP_AXI_PROT_EN_2_SET, 650 MT8188_TOP_AXI_PROT_EN_2_CLR, 651 MT8188_TOP_AXI_PROT_EN_2_STA), 652 }, 653 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 654 }, 655 [MT8188_POWER_DOMAIN_CAM_SUBA] = { 656 .name = "cam_suba", 657 .sta_mask = BIT(25), 658 .ctl_offs = 0x398, 659 .pwr_sta_offs = 0x16C, 660 .pwr_sta2nd_offs = 0x170, 661 .sram_pdn_bits = BIT(8), 662 .sram_pdn_ack_bits = BIT(12), 663 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 664 }, 665 [MT8188_POWER_DOMAIN_CAM_SUBB] = { 666 .name = "cam_subb", 667 .sta_mask = BIT(26), 668 .ctl_offs = 0x39C, 669 .pwr_sta_offs = 0x16C, 670 .pwr_sta2nd_offs = 0x170, 671 .sram_pdn_bits = BIT(8), 672 .sram_pdn_ack_bits = BIT(12), 673 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 674 }, 675 }; 676 677 static const struct scpsys_soc_data mt8188_scpsys_data = { 678 .domains_data = scpsys_domain_data_mt8188, 679 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188), 680 }; 681 682 #endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */ 683