1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 MediaTek Inc. 4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5 */ 6 7 #ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H 8 #define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H 9 10 #include "mtk-pm-domains.h" 11 #include <dt-bindings/power/mt8186-power.h> 12 13 /* 14 * MT8186 power domain support 15 */ 16 static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8186[] = { 17 BUS_PROT_BLOCK_INFRA 18 }; 19 20 static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { 21 [MT8186_POWER_DOMAIN_MFG0] = { 22 .name = "mfg0", 23 .sta_mask = BIT(2), 24 .ctl_offs = 0x308, 25 .pwr_sta_offs = 0x16C, 26 .pwr_sta2nd_offs = 0x170, 27 .sram_pdn_bits = BIT(8), 28 .sram_pdn_ack_bits = BIT(12), 29 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 30 }, 31 [MT8186_POWER_DOMAIN_MFG1] = { 32 .name = "mfg1", 33 .sta_mask = BIT(3), 34 .ctl_offs = 0x30c, 35 .pwr_sta_offs = 0x16C, 36 .pwr_sta2nd_offs = 0x170, 37 .sram_pdn_bits = BIT(8), 38 .sram_pdn_ack_bits = BIT(12), 39 .bp_cfg = { 40 BUS_PROT_WR_IGN(INFRA, 41 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, 42 MT8186_TOP_AXI_PROT_EN_1_SET, 43 MT8186_TOP_AXI_PROT_EN_1_CLR, 44 MT8186_TOP_AXI_PROT_EN_1_STA), 45 BUS_PROT_WR_IGN(INFRA, 46 MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, 47 MT8186_TOP_AXI_PROT_EN_SET, 48 MT8186_TOP_AXI_PROT_EN_CLR, 49 MT8186_TOP_AXI_PROT_EN_STA), 50 BUS_PROT_WR_IGN(INFRA, 51 MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, 52 MT8186_TOP_AXI_PROT_EN_SET, 53 MT8186_TOP_AXI_PROT_EN_CLR, 54 MT8186_TOP_AXI_PROT_EN_STA), 55 BUS_PROT_WR_IGN(INFRA, 56 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, 57 MT8186_TOP_AXI_PROT_EN_1_SET, 58 MT8186_TOP_AXI_PROT_EN_1_CLR, 59 MT8186_TOP_AXI_PROT_EN_1_STA), 60 }, 61 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, 62 }, 63 [MT8186_POWER_DOMAIN_MFG2] = { 64 .name = "mfg2", 65 .sta_mask = BIT(4), 66 .ctl_offs = 0x310, 67 .pwr_sta_offs = 0x16C, 68 .pwr_sta2nd_offs = 0x170, 69 .sram_pdn_bits = BIT(8), 70 .sram_pdn_ack_bits = BIT(12), 71 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 72 }, 73 [MT8186_POWER_DOMAIN_MFG3] = { 74 .name = "mfg3", 75 .sta_mask = BIT(5), 76 .ctl_offs = 0x314, 77 .pwr_sta_offs = 0x16C, 78 .pwr_sta2nd_offs = 0x170, 79 .sram_pdn_bits = BIT(8), 80 .sram_pdn_ack_bits = BIT(12), 81 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 82 }, 83 [MT8186_POWER_DOMAIN_SSUSB] = { 84 .name = "ssusb", 85 .sta_mask = BIT(20), 86 .ctl_offs = 0x9F0, 87 .pwr_sta_offs = 0x16C, 88 .pwr_sta2nd_offs = 0x170, 89 .sram_pdn_bits = BIT(8), 90 .sram_pdn_ack_bits = BIT(12), 91 .caps = MTK_SCPD_ACTIVE_WAKEUP, 92 }, 93 [MT8186_POWER_DOMAIN_SSUSB_P1] = { 94 .name = "ssusb_p1", 95 .sta_mask = BIT(19), 96 .ctl_offs = 0x9F4, 97 .pwr_sta_offs = 0x16C, 98 .pwr_sta2nd_offs = 0x170, 99 .sram_pdn_bits = BIT(8), 100 .sram_pdn_ack_bits = BIT(12), 101 .caps = MTK_SCPD_ACTIVE_WAKEUP, 102 }, 103 [MT8186_POWER_DOMAIN_DIS] = { 104 .name = "dis", 105 .sta_mask = BIT(21), 106 .ctl_offs = 0x354, 107 .pwr_sta_offs = 0x16C, 108 .pwr_sta2nd_offs = 0x170, 109 .sram_pdn_bits = BIT(8), 110 .sram_pdn_ack_bits = BIT(12), 111 .bp_cfg = { 112 BUS_PROT_WR_IGN(INFRA, 113 MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, 114 MT8186_TOP_AXI_PROT_EN_1_SET, 115 MT8186_TOP_AXI_PROT_EN_1_CLR, 116 MT8186_TOP_AXI_PROT_EN_1_STA), 117 BUS_PROT_WR_IGN(INFRA, 118 MT8186_TOP_AXI_PROT_EN_DIS_STEP2, 119 MT8186_TOP_AXI_PROT_EN_SET, 120 MT8186_TOP_AXI_PROT_EN_CLR, 121 MT8186_TOP_AXI_PROT_EN_STA), 122 }, 123 }, 124 [MT8186_POWER_DOMAIN_IMG] = { 125 .name = "img", 126 .sta_mask = BIT(13), 127 .ctl_offs = 0x334, 128 .pwr_sta_offs = 0x16C, 129 .pwr_sta2nd_offs = 0x170, 130 .sram_pdn_bits = BIT(8), 131 .sram_pdn_ack_bits = BIT(12), 132 .bp_cfg = { 133 BUS_PROT_WR_IGN(INFRA, 134 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, 135 MT8186_TOP_AXI_PROT_EN_1_SET, 136 MT8186_TOP_AXI_PROT_EN_1_CLR, 137 MT8186_TOP_AXI_PROT_EN_1_STA), 138 BUS_PROT_WR_IGN(INFRA, 139 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, 140 MT8186_TOP_AXI_PROT_EN_1_SET, 141 MT8186_TOP_AXI_PROT_EN_1_CLR, 142 MT8186_TOP_AXI_PROT_EN_1_STA), 143 }, 144 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 145 }, 146 [MT8186_POWER_DOMAIN_IMG2] = { 147 .name = "img2", 148 .sta_mask = BIT(14), 149 .ctl_offs = 0x338, 150 .pwr_sta_offs = 0x16C, 151 .pwr_sta2nd_offs = 0x170, 152 .sram_pdn_bits = BIT(8), 153 .sram_pdn_ack_bits = BIT(12), 154 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 155 }, 156 [MT8186_POWER_DOMAIN_IPE] = { 157 .name = "ipe", 158 .sta_mask = BIT(15), 159 .ctl_offs = 0x33C, 160 .pwr_sta_offs = 0x16C, 161 .pwr_sta2nd_offs = 0x170, 162 .sram_pdn_bits = BIT(8), 163 .sram_pdn_ack_bits = BIT(12), 164 .bp_cfg = { 165 BUS_PROT_WR_IGN(INFRA, 166 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, 167 MT8186_TOP_AXI_PROT_EN_1_SET, 168 MT8186_TOP_AXI_PROT_EN_1_CLR, 169 MT8186_TOP_AXI_PROT_EN_1_STA), 170 BUS_PROT_WR_IGN(INFRA, 171 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, 172 MT8186_TOP_AXI_PROT_EN_1_SET, 173 MT8186_TOP_AXI_PROT_EN_1_CLR, 174 MT8186_TOP_AXI_PROT_EN_1_STA), 175 }, 176 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 177 }, 178 [MT8186_POWER_DOMAIN_CAM] = { 179 .name = "cam", 180 .sta_mask = BIT(23), 181 .ctl_offs = 0x35C, 182 .pwr_sta_offs = 0x16C, 183 .pwr_sta2nd_offs = 0x170, 184 .sram_pdn_bits = BIT(8), 185 .sram_pdn_ack_bits = BIT(12), 186 .bp_cfg = { 187 BUS_PROT_WR_IGN(INFRA, 188 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, 189 MT8186_TOP_AXI_PROT_EN_1_SET, 190 MT8186_TOP_AXI_PROT_EN_1_CLR, 191 MT8186_TOP_AXI_PROT_EN_1_STA), 192 BUS_PROT_WR_IGN(INFRA, 193 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, 194 MT8186_TOP_AXI_PROT_EN_1_SET, 195 MT8186_TOP_AXI_PROT_EN_1_CLR, 196 MT8186_TOP_AXI_PROT_EN_1_STA), 197 }, 198 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 199 }, 200 [MT8186_POWER_DOMAIN_CAM_RAWA] = { 201 .name = "cam_rawa", 202 .sta_mask = BIT(24), 203 .ctl_offs = 0x360, 204 .pwr_sta_offs = 0x16C, 205 .pwr_sta2nd_offs = 0x170, 206 .sram_pdn_bits = BIT(8), 207 .sram_pdn_ack_bits = BIT(12), 208 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 209 }, 210 [MT8186_POWER_DOMAIN_CAM_RAWB] = { 211 .name = "cam_rawb", 212 .sta_mask = BIT(25), 213 .ctl_offs = 0x364, 214 .pwr_sta_offs = 0x16C, 215 .pwr_sta2nd_offs = 0x170, 216 .sram_pdn_bits = BIT(8), 217 .sram_pdn_ack_bits = BIT(12), 218 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 219 }, 220 [MT8186_POWER_DOMAIN_VENC] = { 221 .name = "venc", 222 .sta_mask = BIT(18), 223 .ctl_offs = 0x348, 224 .pwr_sta_offs = 0x16C, 225 .pwr_sta2nd_offs = 0x170, 226 .sram_pdn_bits = BIT(8), 227 .sram_pdn_ack_bits = BIT(12), 228 .bp_cfg = { 229 BUS_PROT_WR_IGN(INFRA, 230 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, 231 MT8186_TOP_AXI_PROT_EN_1_SET, 232 MT8186_TOP_AXI_PROT_EN_1_CLR, 233 MT8186_TOP_AXI_PROT_EN_1_STA), 234 BUS_PROT_WR_IGN(INFRA, 235 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, 236 MT8186_TOP_AXI_PROT_EN_1_SET, 237 MT8186_TOP_AXI_PROT_EN_1_CLR, 238 MT8186_TOP_AXI_PROT_EN_1_STA), 239 }, 240 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 241 }, 242 [MT8186_POWER_DOMAIN_VDEC] = { 243 .name = "vdec", 244 .sta_mask = BIT(16), 245 .ctl_offs = 0x340, 246 .pwr_sta_offs = 0x16C, 247 .pwr_sta2nd_offs = 0x170, 248 .sram_pdn_bits = BIT(8), 249 .sram_pdn_ack_bits = BIT(12), 250 .bp_cfg = { 251 BUS_PROT_WR_IGN(INFRA, 252 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, 253 MT8186_TOP_AXI_PROT_EN_1_SET, 254 MT8186_TOP_AXI_PROT_EN_1_CLR, 255 MT8186_TOP_AXI_PROT_EN_1_STA), 256 BUS_PROT_WR_IGN(INFRA, 257 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, 258 MT8186_TOP_AXI_PROT_EN_1_SET, 259 MT8186_TOP_AXI_PROT_EN_1_CLR, 260 MT8186_TOP_AXI_PROT_EN_1_STA), 261 }, 262 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 263 }, 264 [MT8186_POWER_DOMAIN_WPE] = { 265 .name = "wpe", 266 .sta_mask = BIT(0), 267 .ctl_offs = 0x3F8, 268 .pwr_sta_offs = 0x16C, 269 .pwr_sta2nd_offs = 0x170, 270 .sram_pdn_bits = BIT(8), 271 .sram_pdn_ack_bits = BIT(12), 272 .bp_cfg = { 273 BUS_PROT_WR_IGN(INFRA, 274 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, 275 MT8186_TOP_AXI_PROT_EN_2_SET, 276 MT8186_TOP_AXI_PROT_EN_2_CLR, 277 MT8186_TOP_AXI_PROT_EN_2_STA), 278 BUS_PROT_WR_IGN(INFRA, 279 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, 280 MT8186_TOP_AXI_PROT_EN_2_SET, 281 MT8186_TOP_AXI_PROT_EN_2_CLR, 282 MT8186_TOP_AXI_PROT_EN_2_STA), 283 }, 284 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 285 }, 286 [MT8186_POWER_DOMAIN_CONN_ON] = { 287 .name = "conn_on", 288 .sta_mask = BIT(1), 289 .ctl_offs = 0x304, 290 .pwr_sta_offs = 0x16C, 291 .pwr_sta2nd_offs = 0x170, 292 .bp_cfg = { 293 BUS_PROT_WR_IGN(INFRA, 294 MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, 295 MT8186_TOP_AXI_PROT_EN_1_SET, 296 MT8186_TOP_AXI_PROT_EN_1_CLR, 297 MT8186_TOP_AXI_PROT_EN_1_STA), 298 BUS_PROT_WR_IGN(INFRA, 299 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, 300 MT8186_TOP_AXI_PROT_EN_SET, 301 MT8186_TOP_AXI_PROT_EN_CLR, 302 MT8186_TOP_AXI_PROT_EN_STA), 303 BUS_PROT_WR_IGN(INFRA, 304 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, 305 MT8186_TOP_AXI_PROT_EN_SET, 306 MT8186_TOP_AXI_PROT_EN_CLR, 307 MT8186_TOP_AXI_PROT_EN_STA), 308 BUS_PROT_WR_IGN(INFRA, 309 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, 310 MT8186_TOP_AXI_PROT_EN_SET, 311 MT8186_TOP_AXI_PROT_EN_CLR, 312 MT8186_TOP_AXI_PROT_EN_STA), 313 }, 314 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, 315 }, 316 [MT8186_POWER_DOMAIN_CSIRX_TOP] = { 317 .name = "csirx_top", 318 .sta_mask = BIT(6), 319 .ctl_offs = 0x318, 320 .pwr_sta_offs = 0x16C, 321 .pwr_sta2nd_offs = 0x170, 322 .sram_pdn_bits = BIT(8), 323 .sram_pdn_ack_bits = BIT(12), 324 .caps = MTK_SCPD_KEEP_DEFAULT_OFF, 325 }, 326 [MT8186_POWER_DOMAIN_ADSP_AO] = { 327 .name = "adsp_ao", 328 .sta_mask = BIT(17), 329 .ctl_offs = 0x9FC, 330 .pwr_sta_offs = 0x16C, 331 .pwr_sta2nd_offs = 0x170, 332 }, 333 [MT8186_POWER_DOMAIN_ADSP_INFRA] = { 334 .name = "adsp_infra", 335 .sta_mask = BIT(10), 336 .ctl_offs = 0x9F8, 337 .pwr_sta_offs = 0x16C, 338 .pwr_sta2nd_offs = 0x170, 339 }, 340 [MT8186_POWER_DOMAIN_ADSP_TOP] = { 341 .name = "adsp_top", 342 .sta_mask = BIT(31), 343 .ctl_offs = 0x3E4, 344 .pwr_sta_offs = 0x16C, 345 .pwr_sta2nd_offs = 0x170, 346 .sram_pdn_bits = BIT(8), 347 .sram_pdn_ack_bits = BIT(12), 348 .bp_cfg = { 349 BUS_PROT_WR_IGN(INFRA, 350 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, 351 MT8186_TOP_AXI_PROT_EN_3_SET, 352 MT8186_TOP_AXI_PROT_EN_3_CLR, 353 MT8186_TOP_AXI_PROT_EN_3_STA), 354 BUS_PROT_WR_IGN(INFRA, 355 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, 356 MT8186_TOP_AXI_PROT_EN_3_SET, 357 MT8186_TOP_AXI_PROT_EN_3_CLR, 358 MT8186_TOP_AXI_PROT_EN_3_STA), 359 }, 360 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, 361 }, 362 }; 363 364 static const struct scpsys_soc_data mt8186_scpsys_data = { 365 .domains_data = scpsys_domain_data_mt8186, 366 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186), 367 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8186, 368 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8186), 369 }; 370 371 #endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */ 372