1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 5 6 #include "mtk-pm-domains.h" 7 #include <dt-bindings/power/mt8183-power.h> 8 9 /* 10 * MT8183 power domain support 11 */ 12 13 static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 14 [MT8183_POWER_DOMAIN_AUDIO] = { 15 .name = "audio", 16 .sta_mask = PWR_STATUS_AUDIO, 17 .ctl_offs = 0x0314, 18 .pwr_sta_offs = 0x0180, 19 .pwr_sta2nd_offs = 0x0184, 20 .sram_pdn_bits = GENMASK(11, 8), 21 .sram_pdn_ack_bits = GENMASK(15, 12), 22 }, 23 [MT8183_POWER_DOMAIN_CONN] = { 24 .name = "conn", 25 .sta_mask = PWR_STATUS_CONN, 26 .ctl_offs = 0x032c, 27 .pwr_sta_offs = 0x0180, 28 .pwr_sta2nd_offs = 0x0184, 29 .sram_pdn_bits = 0, 30 .sram_pdn_ack_bits = 0, 31 .bp_cfg = { 32 BUS_PROT_WR(INFRA, 33 MT8183_TOP_AXI_PROT_EN_CONN, 34 MT8183_TOP_AXI_PROT_EN_SET, 35 MT8183_TOP_AXI_PROT_EN_CLR, 36 MT8183_TOP_AXI_PROT_EN_STA1), 37 }, 38 }, 39 [MT8183_POWER_DOMAIN_MFG_ASYNC] = { 40 .name = "mfg_async", 41 .sta_mask = PWR_STATUS_MFG_ASYNC, 42 .ctl_offs = 0x0334, 43 .pwr_sta_offs = 0x0180, 44 .pwr_sta2nd_offs = 0x0184, 45 .sram_pdn_bits = 0, 46 .sram_pdn_ack_bits = 0, 47 .caps = MTK_SCPD_DOMAIN_SUPPLY, 48 }, 49 [MT8183_POWER_DOMAIN_MFG] = { 50 .name = "mfg", 51 .sta_mask = PWR_STATUS_MFG, 52 .ctl_offs = 0x0338, 53 .pwr_sta_offs = 0x0180, 54 .pwr_sta2nd_offs = 0x0184, 55 .sram_pdn_bits = GENMASK(8, 8), 56 .sram_pdn_ack_bits = GENMASK(12, 12), 57 .caps = MTK_SCPD_DOMAIN_SUPPLY, 58 }, 59 [MT8183_POWER_DOMAIN_MFG_CORE0] = { 60 .name = "mfg_core0", 61 .sta_mask = BIT(7), 62 .ctl_offs = 0x034c, 63 .pwr_sta_offs = 0x0180, 64 .pwr_sta2nd_offs = 0x0184, 65 .sram_pdn_bits = GENMASK(8, 8), 66 .sram_pdn_ack_bits = GENMASK(12, 12), 67 }, 68 [MT8183_POWER_DOMAIN_MFG_CORE1] = { 69 .name = "mfg_core1", 70 .sta_mask = BIT(20), 71 .ctl_offs = 0x0310, 72 .pwr_sta_offs = 0x0180, 73 .pwr_sta2nd_offs = 0x0184, 74 .sram_pdn_bits = GENMASK(8, 8), 75 .sram_pdn_ack_bits = GENMASK(12, 12), 76 }, 77 [MT8183_POWER_DOMAIN_MFG_2D] = { 78 .name = "mfg_2d", 79 .sta_mask = PWR_STATUS_MFG_2D, 80 .ctl_offs = 0x0348, 81 .pwr_sta_offs = 0x0180, 82 .pwr_sta2nd_offs = 0x0184, 83 .sram_pdn_bits = GENMASK(8, 8), 84 .sram_pdn_ack_bits = GENMASK(12, 12), 85 .bp_cfg = { 86 BUS_PROT_WR(INFRA, 87 MT8183_TOP_AXI_PROT_EN_1_MFG, 88 MT8183_TOP_AXI_PROT_EN_1_SET, 89 MT8183_TOP_AXI_PROT_EN_1_CLR, 90 MT8183_TOP_AXI_PROT_EN_STA1_1), 91 BUS_PROT_WR(INFRA, 92 MT8183_TOP_AXI_PROT_EN_MFG, 93 MT8183_TOP_AXI_PROT_EN_SET, 94 MT8183_TOP_AXI_PROT_EN_CLR, 95 MT8183_TOP_AXI_PROT_EN_STA1), 96 }, 97 }, 98 [MT8183_POWER_DOMAIN_DISP] = { 99 .name = "disp", 100 .sta_mask = PWR_STATUS_DISP, 101 .ctl_offs = 0x030c, 102 .pwr_sta_offs = 0x0180, 103 .pwr_sta2nd_offs = 0x0184, 104 .sram_pdn_bits = GENMASK(8, 8), 105 .sram_pdn_ack_bits = GENMASK(12, 12), 106 .bp_cfg = { 107 BUS_PROT_WR(INFRA, 108 MT8183_TOP_AXI_PROT_EN_1_DISP, 109 MT8183_TOP_AXI_PROT_EN_1_SET, 110 MT8183_TOP_AXI_PROT_EN_1_CLR, 111 MT8183_TOP_AXI_PROT_EN_STA1_1), 112 BUS_PROT_WR(INFRA, 113 MT8183_TOP_AXI_PROT_EN_DISP, 114 MT8183_TOP_AXI_PROT_EN_SET, 115 MT8183_TOP_AXI_PROT_EN_CLR, 116 MT8183_TOP_AXI_PROT_EN_STA1), 117 BUS_PROT_WR(SMI, 118 MT8183_SMI_COMMON_SMI_CLAMP_DISP, 119 MT8183_SMI_COMMON_CLAMP_EN_SET, 120 MT8183_SMI_COMMON_CLAMP_EN_CLR, 121 MT8183_SMI_COMMON_CLAMP_EN), 122 }, 123 }, 124 [MT8183_POWER_DOMAIN_CAM] = { 125 .name = "cam", 126 .sta_mask = BIT(25), 127 .ctl_offs = 0x0344, 128 .pwr_sta_offs = 0x0180, 129 .pwr_sta2nd_offs = 0x0184, 130 .sram_pdn_bits = GENMASK(9, 8), 131 .sram_pdn_ack_bits = GENMASK(13, 12), 132 .bp_cfg = { 133 BUS_PROT_WR(INFRA, 134 MT8183_TOP_AXI_PROT_EN_MM_CAM, 135 MT8183_TOP_AXI_PROT_EN_MM_SET, 136 MT8183_TOP_AXI_PROT_EN_MM_CLR, 137 MT8183_TOP_AXI_PROT_EN_MM_STA1), 138 BUS_PROT_WR(INFRA, 139 MT8183_TOP_AXI_PROT_EN_CAM, 140 MT8183_TOP_AXI_PROT_EN_SET, 141 MT8183_TOP_AXI_PROT_EN_CLR, 142 MT8183_TOP_AXI_PROT_EN_STA1), 143 BUS_PROT_WR_IGN(INFRA, 144 MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, 145 MT8183_TOP_AXI_PROT_EN_MM_SET, 146 MT8183_TOP_AXI_PROT_EN_MM_CLR, 147 MT8183_TOP_AXI_PROT_EN_MM_STA1), 148 BUS_PROT_WR(SMI, 149 MT8183_SMI_COMMON_SMI_CLAMP_CAM, 150 MT8183_SMI_COMMON_CLAMP_EN_SET, 151 MT8183_SMI_COMMON_CLAMP_EN_CLR, 152 MT8183_SMI_COMMON_CLAMP_EN), 153 }, 154 }, 155 [MT8183_POWER_DOMAIN_ISP] = { 156 .name = "isp", 157 .sta_mask = PWR_STATUS_ISP, 158 .ctl_offs = 0x0308, 159 .pwr_sta_offs = 0x0180, 160 .pwr_sta2nd_offs = 0x0184, 161 .sram_pdn_bits = GENMASK(9, 8), 162 .sram_pdn_ack_bits = GENMASK(13, 12), 163 .bp_cfg = { 164 BUS_PROT_WR(INFRA, 165 MT8183_TOP_AXI_PROT_EN_MM_ISP, 166 MT8183_TOP_AXI_PROT_EN_MM_SET, 167 MT8183_TOP_AXI_PROT_EN_MM_CLR, 168 MT8183_TOP_AXI_PROT_EN_MM_STA1), 169 BUS_PROT_WR_IGN(INFRA, 170 MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, 171 MT8183_TOP_AXI_PROT_EN_MM_SET, 172 MT8183_TOP_AXI_PROT_EN_MM_CLR, 173 MT8183_TOP_AXI_PROT_EN_MM_STA1), 174 BUS_PROT_WR(SMI, 175 MT8183_SMI_COMMON_SMI_CLAMP_ISP, 176 MT8183_SMI_COMMON_CLAMP_EN_SET, 177 MT8183_SMI_COMMON_CLAMP_EN_CLR, 178 MT8183_SMI_COMMON_CLAMP_EN), 179 }, 180 }, 181 [MT8183_POWER_DOMAIN_VDEC] = { 182 .name = "vdec", 183 .sta_mask = BIT(31), 184 .ctl_offs = 0x0300, 185 .pwr_sta_offs = 0x0180, 186 .pwr_sta2nd_offs = 0x0184, 187 .sram_pdn_bits = GENMASK(8, 8), 188 .sram_pdn_ack_bits = GENMASK(12, 12), 189 .bp_cfg = { 190 BUS_PROT_WR(SMI, 191 MT8183_SMI_COMMON_SMI_CLAMP_VDEC, 192 MT8183_SMI_COMMON_CLAMP_EN_SET, 193 MT8183_SMI_COMMON_CLAMP_EN_CLR, 194 MT8183_SMI_COMMON_CLAMP_EN), 195 }, 196 }, 197 [MT8183_POWER_DOMAIN_VENC] = { 198 .name = "venc", 199 .sta_mask = PWR_STATUS_VENC, 200 .ctl_offs = 0x0304, 201 .pwr_sta_offs = 0x0180, 202 .pwr_sta2nd_offs = 0x0184, 203 .sram_pdn_bits = GENMASK(11, 8), 204 .sram_pdn_ack_bits = GENMASK(15, 12), 205 .bp_cfg = { 206 BUS_PROT_WR(SMI, 207 MT8183_SMI_COMMON_SMI_CLAMP_VENC, 208 MT8183_SMI_COMMON_CLAMP_EN_SET, 209 MT8183_SMI_COMMON_CLAMP_EN_CLR, 210 MT8183_SMI_COMMON_CLAMP_EN), 211 }, 212 }, 213 [MT8183_POWER_DOMAIN_VPU_TOP] = { 214 .name = "vpu_top", 215 .sta_mask = BIT(26), 216 .ctl_offs = 0x0324, 217 .pwr_sta_offs = 0x0180, 218 .pwr_sta2nd_offs = 0x0184, 219 .sram_pdn_bits = GENMASK(8, 8), 220 .sram_pdn_ack_bits = GENMASK(12, 12), 221 .bp_cfg = { 222 BUS_PROT_WR(INFRA, 223 MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, 224 MT8183_TOP_AXI_PROT_EN_MM_SET, 225 MT8183_TOP_AXI_PROT_EN_MM_CLR, 226 MT8183_TOP_AXI_PROT_EN_MM_STA1), 227 BUS_PROT_WR(INFRA, 228 MT8183_TOP_AXI_PROT_EN_VPU_TOP, 229 MT8183_TOP_AXI_PROT_EN_SET, 230 MT8183_TOP_AXI_PROT_EN_CLR, 231 MT8183_TOP_AXI_PROT_EN_STA1), 232 BUS_PROT_WR(INFRA, 233 MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, 234 MT8183_TOP_AXI_PROT_EN_MM_SET, 235 MT8183_TOP_AXI_PROT_EN_MM_CLR, 236 MT8183_TOP_AXI_PROT_EN_MM_STA1), 237 BUS_PROT_WR(SMI, 238 MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, 239 MT8183_SMI_COMMON_CLAMP_EN_SET, 240 MT8183_SMI_COMMON_CLAMP_EN_CLR, 241 MT8183_SMI_COMMON_CLAMP_EN), 242 }, 243 }, 244 [MT8183_POWER_DOMAIN_VPU_CORE0] = { 245 .name = "vpu_core0", 246 .sta_mask = BIT(27), 247 .ctl_offs = 0x33c, 248 .pwr_sta_offs = 0x0180, 249 .pwr_sta2nd_offs = 0x0184, 250 .sram_pdn_bits = GENMASK(11, 8), 251 .sram_pdn_ack_bits = GENMASK(13, 12), 252 .bp_cfg = { 253 BUS_PROT_WR(INFRA, 254 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, 255 MT8183_TOP_AXI_PROT_EN_MCU_SET, 256 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 257 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 258 BUS_PROT_WR(INFRA, 259 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, 260 MT8183_TOP_AXI_PROT_EN_MCU_SET, 261 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 262 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 263 }, 264 .caps = MTK_SCPD_SRAM_ISO, 265 }, 266 [MT8183_POWER_DOMAIN_VPU_CORE1] = { 267 .name = "vpu_core1", 268 .sta_mask = BIT(28), 269 .ctl_offs = 0x0340, 270 .pwr_sta_offs = 0x0180, 271 .pwr_sta2nd_offs = 0x0184, 272 .sram_pdn_bits = GENMASK(11, 8), 273 .sram_pdn_ack_bits = GENMASK(13, 12), 274 .bp_cfg = { 275 BUS_PROT_WR(INFRA, 276 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, 277 MT8183_TOP_AXI_PROT_EN_MCU_SET, 278 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 279 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 280 BUS_PROT_WR(INFRA, 281 MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, 282 MT8183_TOP_AXI_PROT_EN_MCU_SET, 283 MT8183_TOP_AXI_PROT_EN_MCU_CLR, 284 MT8183_TOP_AXI_PROT_EN_MCU_STA1), 285 }, 286 .caps = MTK_SCPD_SRAM_ISO, 287 }, 288 }; 289 290 static const struct scpsys_soc_data mt8183_scpsys_data = { 291 .domains_data = scpsys_domain_data_mt8183, 292 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), 293 }; 294 295 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ 296