1*e2ad626fSUlf Hansson /* SPDX-License-Identifier: GPL-2.0-only */ 2*e2ad626fSUlf Hansson 3*e2ad626fSUlf Hansson #ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 4*e2ad626fSUlf Hansson #define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H 5*e2ad626fSUlf Hansson 6*e2ad626fSUlf Hansson #include "mtk-pm-domains.h" 7*e2ad626fSUlf Hansson #include <dt-bindings/power/mt8183-power.h> 8*e2ad626fSUlf Hansson 9*e2ad626fSUlf Hansson /* 10*e2ad626fSUlf Hansson * MT8183 power domain support 11*e2ad626fSUlf Hansson */ 12*e2ad626fSUlf Hansson 13*e2ad626fSUlf Hansson static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { 14*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_AUDIO] = { 15*e2ad626fSUlf Hansson .name = "audio", 16*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_AUDIO, 17*e2ad626fSUlf Hansson .ctl_offs = 0x0314, 18*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 19*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 20*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 21*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 22*e2ad626fSUlf Hansson }, 23*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_CONN] = { 24*e2ad626fSUlf Hansson .name = "conn", 25*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_CONN, 26*e2ad626fSUlf Hansson .ctl_offs = 0x032c, 27*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 28*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 29*e2ad626fSUlf Hansson .sram_pdn_bits = 0, 30*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 31*e2ad626fSUlf Hansson .bp_infracfg = { 32*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, 33*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 34*e2ad626fSUlf Hansson }, 35*e2ad626fSUlf Hansson }, 36*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_MFG_ASYNC] = { 37*e2ad626fSUlf Hansson .name = "mfg_async", 38*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG_ASYNC, 39*e2ad626fSUlf Hansson .ctl_offs = 0x0334, 40*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 41*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 42*e2ad626fSUlf Hansson .sram_pdn_bits = 0, 43*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 44*e2ad626fSUlf Hansson .caps = MTK_SCPD_DOMAIN_SUPPLY, 45*e2ad626fSUlf Hansson }, 46*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_MFG] = { 47*e2ad626fSUlf Hansson .name = "mfg", 48*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG, 49*e2ad626fSUlf Hansson .ctl_offs = 0x0338, 50*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 51*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 52*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 53*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 54*e2ad626fSUlf Hansson .caps = MTK_SCPD_DOMAIN_SUPPLY, 55*e2ad626fSUlf Hansson }, 56*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_MFG_CORE0] = { 57*e2ad626fSUlf Hansson .name = "mfg_core0", 58*e2ad626fSUlf Hansson .sta_mask = BIT(7), 59*e2ad626fSUlf Hansson .ctl_offs = 0x034c, 60*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 61*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 62*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 63*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 64*e2ad626fSUlf Hansson }, 65*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_MFG_CORE1] = { 66*e2ad626fSUlf Hansson .name = "mfg_core1", 67*e2ad626fSUlf Hansson .sta_mask = BIT(20), 68*e2ad626fSUlf Hansson .ctl_offs = 0x0310, 69*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 70*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 71*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 72*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 73*e2ad626fSUlf Hansson }, 74*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_MFG_2D] = { 75*e2ad626fSUlf Hansson .name = "mfg_2d", 76*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG_2D, 77*e2ad626fSUlf Hansson .ctl_offs = 0x0348, 78*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 79*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 80*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 81*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 82*e2ad626fSUlf Hansson .bp_infracfg = { 83*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, 84*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 85*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, 86*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 87*e2ad626fSUlf Hansson }, 88*e2ad626fSUlf Hansson }, 89*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_DISP] = { 90*e2ad626fSUlf Hansson .name = "disp", 91*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_DISP, 92*e2ad626fSUlf Hansson .ctl_offs = 0x030c, 93*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 94*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 95*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 96*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 97*e2ad626fSUlf Hansson .bp_infracfg = { 98*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, 99*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), 100*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, 101*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 102*e2ad626fSUlf Hansson }, 103*e2ad626fSUlf Hansson .bp_smi = { 104*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, 105*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 106*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 107*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 108*e2ad626fSUlf Hansson }, 109*e2ad626fSUlf Hansson }, 110*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_CAM] = { 111*e2ad626fSUlf Hansson .name = "cam", 112*e2ad626fSUlf Hansson .sta_mask = BIT(25), 113*e2ad626fSUlf Hansson .ctl_offs = 0x0344, 114*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 115*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 116*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(9, 8), 117*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 118*e2ad626fSUlf Hansson .bp_infracfg = { 119*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, 120*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), 121*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, 122*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), 123*e2ad626fSUlf Hansson BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, 124*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_SET, 125*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, 126*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_STA1), 127*e2ad626fSUlf Hansson }, 128*e2ad626fSUlf Hansson .bp_smi = { 129*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, 130*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 131*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 132*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 133*e2ad626fSUlf Hansson }, 134*e2ad626fSUlf Hansson }, 135*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_ISP] = { 136*e2ad626fSUlf Hansson .name = "isp", 137*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_ISP, 138*e2ad626fSUlf Hansson .ctl_offs = 0x0308, 139*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 140*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 141*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(9, 8), 142*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 143*e2ad626fSUlf Hansson .bp_infracfg = { 144*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, 145*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_SET, 146*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, 147*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_STA1), 148*e2ad626fSUlf Hansson BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, 149*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_SET, 150*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, 151*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_STA1), 152*e2ad626fSUlf Hansson }, 153*e2ad626fSUlf Hansson .bp_smi = { 154*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, 155*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 156*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 157*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 158*e2ad626fSUlf Hansson }, 159*e2ad626fSUlf Hansson }, 160*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_VDEC] = { 161*e2ad626fSUlf Hansson .name = "vdec", 162*e2ad626fSUlf Hansson .sta_mask = BIT(31), 163*e2ad626fSUlf Hansson .ctl_offs = 0x0300, 164*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 165*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 166*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 167*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 168*e2ad626fSUlf Hansson .bp_smi = { 169*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, 170*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 171*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 172*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 173*e2ad626fSUlf Hansson }, 174*e2ad626fSUlf Hansson }, 175*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_VENC] = { 176*e2ad626fSUlf Hansson .name = "venc", 177*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_VENC, 178*e2ad626fSUlf Hansson .ctl_offs = 0x0304, 179*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 180*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 181*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 182*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 183*e2ad626fSUlf Hansson .bp_smi = { 184*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, 185*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 186*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 187*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 188*e2ad626fSUlf Hansson }, 189*e2ad626fSUlf Hansson }, 190*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_VPU_TOP] = { 191*e2ad626fSUlf Hansson .name = "vpu_top", 192*e2ad626fSUlf Hansson .sta_mask = BIT(26), 193*e2ad626fSUlf Hansson .ctl_offs = 0x0324, 194*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 195*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 196*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 197*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 198*e2ad626fSUlf Hansson .bp_infracfg = { 199*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, 200*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_SET, 201*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, 202*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_STA1), 203*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, 204*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_SET, 205*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_CLR, 206*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_STA1), 207*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, 208*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_SET, 209*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_CLR, 210*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MM_STA1), 211*e2ad626fSUlf Hansson }, 212*e2ad626fSUlf Hansson .bp_smi = { 213*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, 214*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_SET, 215*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN_CLR, 216*e2ad626fSUlf Hansson MT8183_SMI_COMMON_CLAMP_EN), 217*e2ad626fSUlf Hansson }, 218*e2ad626fSUlf Hansson }, 219*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_VPU_CORE0] = { 220*e2ad626fSUlf Hansson .name = "vpu_core0", 221*e2ad626fSUlf Hansson .sta_mask = BIT(27), 222*e2ad626fSUlf Hansson .ctl_offs = 0x33c, 223*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 224*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 225*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 226*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 227*e2ad626fSUlf Hansson .bp_infracfg = { 228*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, 229*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_SET, 230*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_CLR, 231*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_STA1), 232*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, 233*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_SET, 234*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_CLR, 235*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_STA1), 236*e2ad626fSUlf Hansson }, 237*e2ad626fSUlf Hansson .caps = MTK_SCPD_SRAM_ISO, 238*e2ad626fSUlf Hansson }, 239*e2ad626fSUlf Hansson [MT8183_POWER_DOMAIN_VPU_CORE1] = { 240*e2ad626fSUlf Hansson .name = "vpu_core1", 241*e2ad626fSUlf Hansson .sta_mask = BIT(28), 242*e2ad626fSUlf Hansson .ctl_offs = 0x0340, 243*e2ad626fSUlf Hansson .pwr_sta_offs = 0x0180, 244*e2ad626fSUlf Hansson .pwr_sta2nd_offs = 0x0184, 245*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 246*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 247*e2ad626fSUlf Hansson .bp_infracfg = { 248*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, 249*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_SET, 250*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_CLR, 251*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_STA1), 252*e2ad626fSUlf Hansson BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, 253*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_SET, 254*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_CLR, 255*e2ad626fSUlf Hansson MT8183_TOP_AXI_PROT_EN_MCU_STA1), 256*e2ad626fSUlf Hansson }, 257*e2ad626fSUlf Hansson .caps = MTK_SCPD_SRAM_ISO, 258*e2ad626fSUlf Hansson }, 259*e2ad626fSUlf Hansson }; 260*e2ad626fSUlf Hansson 261*e2ad626fSUlf Hansson static const struct scpsys_soc_data mt8183_scpsys_data = { 262*e2ad626fSUlf Hansson .domains_data = scpsys_domain_data_mt8183, 263*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), 264*e2ad626fSUlf Hansson }; 265*e2ad626fSUlf Hansson 266*e2ad626fSUlf Hansson #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ 267