1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H 4 #define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H 5 6 #include "mtk-pm-domains.h" 7 #include <dt-bindings/power/mt8173-power.h> 8 9 /* 10 * MT8173 power domain support 11 */ 12 static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8173[] = { 13 BUS_PROT_BLOCK_INFRA 14 }; 15 16 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { 17 [MT8173_POWER_DOMAIN_VDEC] = { 18 .name = "vdec", 19 .sta_mask = PWR_STATUS_VDEC, 20 .ctl_offs = SPM_VDE_PWR_CON, 21 .pwr_sta_offs = SPM_PWR_STATUS, 22 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 23 .sram_pdn_bits = GENMASK(11, 8), 24 .sram_pdn_ack_bits = GENMASK(12, 12), 25 }, 26 [MT8173_POWER_DOMAIN_VENC] = { 27 .name = "venc", 28 .sta_mask = PWR_STATUS_VENC, 29 .ctl_offs = SPM_VEN_PWR_CON, 30 .pwr_sta_offs = SPM_PWR_STATUS, 31 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 32 .sram_pdn_bits = GENMASK(11, 8), 33 .sram_pdn_ack_bits = GENMASK(15, 12), 34 }, 35 [MT8173_POWER_DOMAIN_ISP] = { 36 .name = "isp", 37 .sta_mask = PWR_STATUS_ISP, 38 .ctl_offs = SPM_ISP_PWR_CON, 39 .pwr_sta_offs = SPM_PWR_STATUS, 40 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 41 .sram_pdn_bits = GENMASK(11, 8), 42 .sram_pdn_ack_bits = GENMASK(13, 12), 43 }, 44 [MT8173_POWER_DOMAIN_MM] = { 45 .name = "mm", 46 .sta_mask = PWR_STATUS_DISP, 47 .ctl_offs = SPM_DIS_PWR_CON, 48 .pwr_sta_offs = SPM_PWR_STATUS, 49 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 50 .sram_pdn_bits = GENMASK(11, 8), 51 .sram_pdn_ack_bits = GENMASK(12, 12), 52 .bp_cfg = { 53 BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | 54 MT8173_TOP_AXI_PROT_EN_MM_M1), 55 }, 56 }, 57 [MT8173_POWER_DOMAIN_VENC_LT] = { 58 .name = "venc_lt", 59 .sta_mask = PWR_STATUS_VENC_LT, 60 .ctl_offs = SPM_VEN2_PWR_CON, 61 .pwr_sta_offs = SPM_PWR_STATUS, 62 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 63 .sram_pdn_bits = GENMASK(11, 8), 64 .sram_pdn_ack_bits = GENMASK(15, 12), 65 }, 66 [MT8173_POWER_DOMAIN_AUDIO] = { 67 .name = "audio", 68 .sta_mask = PWR_STATUS_AUDIO, 69 .ctl_offs = SPM_AUDIO_PWR_CON, 70 .pwr_sta_offs = SPM_PWR_STATUS, 71 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 72 .sram_pdn_bits = GENMASK(11, 8), 73 .sram_pdn_ack_bits = GENMASK(15, 12), 74 }, 75 [MT8173_POWER_DOMAIN_USB] = { 76 .name = "usb", 77 .sta_mask = PWR_STATUS_USB, 78 .ctl_offs = SPM_USB_PWR_CON, 79 .pwr_sta_offs = SPM_PWR_STATUS, 80 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 81 .sram_pdn_bits = GENMASK(11, 8), 82 .sram_pdn_ack_bits = GENMASK(15, 12), 83 .caps = MTK_SCPD_ACTIVE_WAKEUP, 84 }, 85 [MT8173_POWER_DOMAIN_MFG_ASYNC] = { 86 .name = "mfg_async", 87 .sta_mask = PWR_STATUS_MFG_ASYNC, 88 .ctl_offs = SPM_MFG_ASYNC_PWR_CON, 89 .pwr_sta_offs = SPM_PWR_STATUS, 90 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 91 .sram_pdn_bits = GENMASK(11, 8), 92 .sram_pdn_ack_bits = 0, 93 .caps = MTK_SCPD_DOMAIN_SUPPLY, 94 }, 95 [MT8173_POWER_DOMAIN_MFG_2D] = { 96 .name = "mfg_2d", 97 .sta_mask = PWR_STATUS_MFG_2D, 98 .ctl_offs = SPM_MFG_2D_PWR_CON, 99 .pwr_sta_offs = SPM_PWR_STATUS, 100 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 101 .sram_pdn_bits = GENMASK(11, 8), 102 .sram_pdn_ack_bits = GENMASK(13, 12), 103 }, 104 [MT8173_POWER_DOMAIN_MFG] = { 105 .name = "mfg", 106 .sta_mask = PWR_STATUS_MFG, 107 .ctl_offs = SPM_MFG_PWR_CON, 108 .pwr_sta_offs = SPM_PWR_STATUS, 109 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 110 .sram_pdn_bits = GENMASK(13, 8), 111 .sram_pdn_ack_bits = GENMASK(21, 16), 112 .bp_cfg = { 113 BUS_PROT_INFRA_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | 114 MT8173_TOP_AXI_PROT_EN_MFG_M0 | 115 MT8173_TOP_AXI_PROT_EN_MFG_M1 | 116 MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), 117 }, 118 }, 119 }; 120 121 static const struct scpsys_soc_data mt8173_scpsys_data = { 122 .domains_data = scpsys_domain_data_mt8173, 123 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), 124 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8173, 125 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8173), 126 }; 127 128 #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ 129