1*e2ad626fSUlf Hansson /* SPDX-License-Identifier: GPL-2.0-only */ 2*e2ad626fSUlf Hansson 3*e2ad626fSUlf Hansson #ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H 4*e2ad626fSUlf Hansson #define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H 5*e2ad626fSUlf Hansson 6*e2ad626fSUlf Hansson #include "mtk-pm-domains.h" 7*e2ad626fSUlf Hansson #include <dt-bindings/power/mt8167-power.h> 8*e2ad626fSUlf Hansson 9*e2ad626fSUlf Hansson #define MT8167_PWR_STATUS_MFG_2D BIT(24) 10*e2ad626fSUlf Hansson #define MT8167_PWR_STATUS_MFG_ASYNC BIT(25) 11*e2ad626fSUlf Hansson 12*e2ad626fSUlf Hansson /* 13*e2ad626fSUlf Hansson * MT8167 power domain support 14*e2ad626fSUlf Hansson */ 15*e2ad626fSUlf Hansson 16*e2ad626fSUlf Hansson static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { 17*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_MM] = { 18*e2ad626fSUlf Hansson .name = "mm", 19*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_DISP, 20*e2ad626fSUlf Hansson .ctl_offs = SPM_DIS_PWR_CON, 21*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 22*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 23*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 24*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 25*e2ad626fSUlf Hansson .bp_infracfg = { 26*e2ad626fSUlf Hansson BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI | 27*e2ad626fSUlf Hansson MT8167_TOP_AXI_PROT_EN_MCU_MM), 28*e2ad626fSUlf Hansson }, 29*e2ad626fSUlf Hansson .caps = MTK_SCPD_ACTIVE_WAKEUP, 30*e2ad626fSUlf Hansson }, 31*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_VDEC] = { 32*e2ad626fSUlf Hansson .name = "vdec", 33*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_VDEC, 34*e2ad626fSUlf Hansson .ctl_offs = SPM_VDE_PWR_CON, 35*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 36*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 37*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 38*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(12, 12), 39*e2ad626fSUlf Hansson .caps = MTK_SCPD_ACTIVE_WAKEUP, 40*e2ad626fSUlf Hansson }, 41*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_ISP] = { 42*e2ad626fSUlf Hansson .name = "isp", 43*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_ISP, 44*e2ad626fSUlf Hansson .ctl_offs = SPM_ISP_PWR_CON, 45*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 46*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 47*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 48*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(13, 12), 49*e2ad626fSUlf Hansson .caps = MTK_SCPD_ACTIVE_WAKEUP, 50*e2ad626fSUlf Hansson }, 51*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_MFG_ASYNC] = { 52*e2ad626fSUlf Hansson .name = "mfg_async", 53*e2ad626fSUlf Hansson .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, 54*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_ASYNC_PWR_CON, 55*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 56*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 57*e2ad626fSUlf Hansson .sram_pdn_bits = 0, 58*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 59*e2ad626fSUlf Hansson .bp_infracfg = { 60*e2ad626fSUlf Hansson BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG | 61*e2ad626fSUlf Hansson MT8167_TOP_AXI_PROT_EN_MFG_EMI), 62*e2ad626fSUlf Hansson }, 63*e2ad626fSUlf Hansson }, 64*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_MFG_2D] = { 65*e2ad626fSUlf Hansson .name = "mfg_2d", 66*e2ad626fSUlf Hansson .sta_mask = MT8167_PWR_STATUS_MFG_2D, 67*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_2D_PWR_CON, 68*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 69*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 70*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 71*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 72*e2ad626fSUlf Hansson }, 73*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_MFG] = { 74*e2ad626fSUlf Hansson .name = "mfg", 75*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_MFG, 76*e2ad626fSUlf Hansson .ctl_offs = SPM_MFG_PWR_CON, 77*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 78*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 79*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(11, 8), 80*e2ad626fSUlf Hansson .sram_pdn_ack_bits = GENMASK(15, 12), 81*e2ad626fSUlf Hansson }, 82*e2ad626fSUlf Hansson [MT8167_POWER_DOMAIN_CONN] = { 83*e2ad626fSUlf Hansson .name = "conn", 84*e2ad626fSUlf Hansson .sta_mask = PWR_STATUS_CONN, 85*e2ad626fSUlf Hansson .ctl_offs = SPM_CONN_PWR_CON, 86*e2ad626fSUlf Hansson .pwr_sta_offs = SPM_PWR_STATUS, 87*e2ad626fSUlf Hansson .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, 88*e2ad626fSUlf Hansson .sram_pdn_bits = GENMASK(8, 8), 89*e2ad626fSUlf Hansson .sram_pdn_ack_bits = 0, 90*e2ad626fSUlf Hansson .caps = MTK_SCPD_ACTIVE_WAKEUP, 91*e2ad626fSUlf Hansson .bp_infracfg = { 92*e2ad626fSUlf Hansson BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI | 93*e2ad626fSUlf Hansson MT8167_TOP_AXI_PROT_EN_CONN_MCU | 94*e2ad626fSUlf Hansson MT8167_TOP_AXI_PROT_EN_MCU_CONN), 95*e2ad626fSUlf Hansson }, 96*e2ad626fSUlf Hansson }, 97*e2ad626fSUlf Hansson }; 98*e2ad626fSUlf Hansson 99*e2ad626fSUlf Hansson static const struct scpsys_soc_data mt8167_scpsys_data = { 100*e2ad626fSUlf Hansson .domains_data = scpsys_domain_data_mt8167, 101*e2ad626fSUlf Hansson .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167), 102*e2ad626fSUlf Hansson }; 103*e2ad626fSUlf Hansson 104*e2ad626fSUlf Hansson #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */ 105*e2ad626fSUlf Hansson 106