1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2022 NXP 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/iopoll.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_domain.h> 13 14 #define MIX_SLICE_SW_CTRL_OFF 0x20 15 #define SLICE_SW_CTRL_PSW_CTRL_OFF_MASK BIT(4) 16 #define SLICE_SW_CTRL_PDN_SOFT_MASK BIT(31) 17 18 #define MIX_FUNC_STAT_OFF 0xB4 19 20 #define FUNC_STAT_PSW_STAT_MASK BIT(0) 21 #define FUNC_STAT_RST_STAT_MASK BIT(2) 22 #define FUNC_STAT_ISO_STAT_MASK BIT(4) 23 #define FUNC_STAT_SSAR_STAT_MASK BIT(8) 24 25 struct imx93_power_domain { 26 struct generic_pm_domain genpd; 27 struct device *dev; 28 void __iomem *addr; 29 struct clk_bulk_data *clks; 30 int num_clks; 31 }; 32 33 #define to_imx93_pd(_genpd) container_of(_genpd, struct imx93_power_domain, genpd) 34 35 static int imx93_pd_on(struct generic_pm_domain *genpd) 36 { 37 struct imx93_power_domain *domain = to_imx93_pd(genpd); 38 void __iomem *addr = domain->addr; 39 u32 val; 40 int ret; 41 42 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); 43 if (ret) { 44 dev_err(domain->dev, "failed to enable clocks for domain: %s\n", genpd->name); 45 return ret; 46 } 47 48 val = readl(addr + MIX_SLICE_SW_CTRL_OFF); 49 val &= ~SLICE_SW_CTRL_PDN_SOFT_MASK; 50 writel(val, addr + MIX_SLICE_SW_CTRL_OFF); 51 52 ret = readl_poll_timeout(addr + MIX_FUNC_STAT_OFF, val, 53 !(val & FUNC_STAT_SSAR_STAT_MASK), 1, 10000); 54 if (ret) { 55 dev_err(domain->dev, "pd_on timeout: name: %s, stat: %x\n", genpd->name, val); 56 return ret; 57 } 58 59 return 0; 60 } 61 62 static int imx93_pd_off(struct generic_pm_domain *genpd) 63 { 64 struct imx93_power_domain *domain = to_imx93_pd(genpd); 65 void __iomem *addr = domain->addr; 66 int ret; 67 u32 val; 68 69 /* Power off MIX */ 70 val = readl(addr + MIX_SLICE_SW_CTRL_OFF); 71 val |= SLICE_SW_CTRL_PDN_SOFT_MASK; 72 writel(val, addr + MIX_SLICE_SW_CTRL_OFF); 73 74 ret = readl_poll_timeout(addr + MIX_FUNC_STAT_OFF, val, 75 val & FUNC_STAT_PSW_STAT_MASK, 1, 10000); 76 if (ret) { 77 dev_err(domain->dev, "pd_off timeout: name: %s, stat: %x\n", genpd->name, val); 78 return ret; 79 } 80 81 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 82 83 return 0; 84 }; 85 86 static void imx93_pd_remove(struct platform_device *pdev) 87 { 88 struct imx93_power_domain *domain = platform_get_drvdata(pdev); 89 struct device *dev = &pdev->dev; 90 struct device_node *np = dev->of_node; 91 92 of_genpd_del_provider(np); 93 pm_genpd_remove(&domain->genpd); 94 } 95 96 static int imx93_pd_probe(struct platform_device *pdev) 97 { 98 struct device *dev = &pdev->dev; 99 struct device_node *np = dev->of_node; 100 struct imx93_power_domain *domain; 101 bool init_off; 102 int ret; 103 104 domain = devm_kzalloc(dev, sizeof(*domain), GFP_KERNEL); 105 if (!domain) 106 return -ENOMEM; 107 108 domain->addr = devm_platform_ioremap_resource(pdev, 0); 109 if (IS_ERR(domain->addr)) 110 return PTR_ERR(domain->addr); 111 112 domain->num_clks = devm_clk_bulk_get_all(dev, &domain->clks); 113 if (domain->num_clks < 0) 114 return dev_err_probe(dev, domain->num_clks, "Failed to get domain's clocks\n"); 115 116 domain->genpd.name = dev_name(dev); 117 domain->genpd.power_off = imx93_pd_off; 118 domain->genpd.power_on = imx93_pd_on; 119 domain->dev = dev; 120 121 init_off = readl(domain->addr + MIX_FUNC_STAT_OFF) & FUNC_STAT_ISO_STAT_MASK; 122 /* Just to sync the status of hardware */ 123 if (!init_off) { 124 ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); 125 if (ret) 126 return dev_err_probe(domain->dev, ret, 127 "failed to enable clocks for domain: %s\n", 128 domain->genpd.name); 129 } 130 131 ret = pm_genpd_init(&domain->genpd, NULL, init_off); 132 if (ret) 133 goto err_clk_unprepare; 134 135 platform_set_drvdata(pdev, domain); 136 137 ret = of_genpd_add_provider_simple(np, &domain->genpd); 138 if (ret) 139 goto err_genpd_remove; 140 141 return 0; 142 143 err_genpd_remove: 144 pm_genpd_remove(&domain->genpd); 145 146 err_clk_unprepare: 147 if (!init_off) 148 clk_bulk_disable_unprepare(domain->num_clks, domain->clks); 149 150 return ret; 151 } 152 153 static const struct of_device_id imx93_pd_ids[] = { 154 { .compatible = "fsl,imx93-src-slice" }, 155 { } 156 }; 157 MODULE_DEVICE_TABLE(of, imx93_pd_ids); 158 159 static struct platform_driver imx93_power_domain_driver = { 160 .driver = { 161 .name = "imx93_power_domain", 162 .of_match_table = imx93_pd_ids, 163 }, 164 .probe = imx93_pd_probe, 165 .remove_new = imx93_pd_remove, 166 }; 167 module_platform_driver(imx93_power_domain_driver); 168 169 MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>"); 170 MODULE_DESCRIPTION("NXP i.MX93 power domain driver"); 171 MODULE_LICENSE("GPL"); 172