1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 2 /* 3 * Mellanox platform driver 4 * 5 * Copyright (C) 2016-2018 Mellanox Technologies 6 * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> 7 */ 8 9 #include <linux/device.h> 10 #include <linux/dmi.h> 11 #include <linux/i2c.h> 12 #include <linux/i2c-mux.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/platform_data/i2c-mux-reg.h> 17 #include <linux/platform_data/mlxreg.h> 18 #include <linux/regmap.h> 19 20 #define MLX_PLAT_DEVICE_NAME "mlxplat" 21 22 /* LPC bus IO offsets */ 23 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0x2000 24 #define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0x2500 25 #define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0x00 26 #define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0x01 27 #define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0x02 28 #define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0x03 29 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0x04 30 #define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0x05 31 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0x06 32 #define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0x07 33 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0x08 34 #define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0x09 35 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0x0a 36 #define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0x0b 37 #define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0x1c 38 #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d 39 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e 40 #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f 41 #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 42 #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 43 #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 44 #define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0x23 45 #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 46 #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 47 #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 48 #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a 49 #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b 50 #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d 51 #define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0x2e 52 #define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0x2f 53 #define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0x30 54 #define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0x31 55 #define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0x32 56 #define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0x33 57 #define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0x34 58 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0x35 59 #define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0x36 60 #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 61 #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a 62 #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b 63 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 64 #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 65 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 66 #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 67 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 68 #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 69 #define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0x50 70 #define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0x51 71 #define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0x52 72 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0x56 73 #define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0x57 74 #define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0x58 75 #define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0x59 76 #define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0x5a 77 #define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0x64 78 #define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0x65 79 #define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0x66 80 #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 81 #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 82 #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 83 #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 84 #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 85 #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a 86 #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a 87 #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b 88 #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c 89 #define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0x9d 90 #define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0x9e 91 #define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0x9f 92 #define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0xa0 93 #define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0xa1 94 #define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0xa2 95 #define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0xa3 96 #define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0xa4 97 #define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0xa5 98 #define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0xa6 99 #define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0xa7 100 #define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0xa8 101 #define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0xa9 102 #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa 103 #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab 104 #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 105 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 106 #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 107 #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 108 #define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0xcb 109 #define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0xcd 110 #define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0xce 111 #define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0xcf 112 #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 113 #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 114 #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 115 #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde 116 #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf 117 #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 118 #define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0xe1 119 #define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0xe2 120 #define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0xe3 121 #define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0xe4 122 #define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0xe5 123 #define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0xe6 124 #define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0xe7 125 #define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0xe8 126 #define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0xe9 127 #define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0xea 128 #define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0xeb 129 #define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0xec 130 #define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0xed 131 #define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0xee 132 #define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0xef 133 #define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0xf0 134 #define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0xf1 135 #define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0xf2 136 #define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0xf3 137 #define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0xf4 138 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0xf5 139 #define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0xf6 140 #define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0xf7 141 #define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0xf8 142 #define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0xf9 143 #define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0xfa 144 #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb 145 #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc 146 #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 147 #define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb 148 #define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda 149 #define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc 150 #define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd 151 152 #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL 153 #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 154 MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ 155 MLXPLAT_CPLD_LPC_PIO_OFFSET) 156 #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 157 MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ 158 MLXPLAT_CPLD_LPC_PIO_OFFSET) 159 #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 160 MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ 161 MLXPLAT_CPLD_LPC_PIO_OFFSET) 162 #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ 163 MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ 164 MLXPLAT_CPLD_LPC_PIO_OFFSET) 165 166 /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ 167 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0x04 168 #define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0x08 169 #define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0x08 170 #define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0x40 171 #define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 172 MLXPLAT_CPLD_AGGR_PSU_MASK_DEF | \ 173 MLXPLAT_CPLD_AGGR_FAN_MASK_DEF) 174 #define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0x01 175 #define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0x04 176 #define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0) 177 #define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3) 178 #define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \ 179 MLXPLAT_CPLD_AGGR_MASK_COMEX | \ 180 MLXPLAT_CPLD_AGGR_MASK_LC) 181 #define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0) 182 #define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1) 183 #define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2) 184 #define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3) 185 #define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4) 186 #define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5) 187 #define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6) 188 #define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \ 189 MLXPLAT_CPLD_AGGR_MASK_LC_RDY | \ 190 MLXPLAT_CPLD_AGGR_MASK_LC_PG | \ 191 MLXPLAT_CPLD_AGGR_MASK_LC_SCRD | \ 192 MLXPLAT_CPLD_AGGR_MASK_LC_SYNC | \ 193 MLXPLAT_CPLD_AGGR_MASK_LC_ACT | \ 194 MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) 195 #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 196 #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) 197 #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) 198 #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) 199 #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) 200 #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) 201 #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) 202 #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) 203 #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) 204 #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) 205 #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) 206 #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) 207 #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 208 #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) 209 210 /* Masks for aggregation for comex carriers */ 211 #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1) 212 #define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \ 213 MLXPLAT_CPLD_AGGR_MASK_CARRIER) 214 #define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0xc1 215 216 /* Masks for aggregation for modular systems */ 217 #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) 218 219 /* Default I2C parent bus number */ 220 #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 221 222 /* Maximum number of possible physical buses equipped on system */ 223 #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 224 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 225 226 /* Number of channels in group */ 227 #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 228 229 /* Start channel numbers */ 230 #define MLXPLAT_CPLD_CH1 2 231 #define MLXPLAT_CPLD_CH2 10 232 #define MLXPLAT_CPLD_CH3 18 233 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 234 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 235 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 236 237 /* Number of LPC attached MUX platform devices */ 238 #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 239 240 /* Hotplug devices adapter numbers */ 241 #define MLXPLAT_CPLD_NR_NONE -1 242 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 243 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 244 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 245 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 246 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 247 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 248 #define MLXPLAT_CPLD_NR_ASIC 3 249 #define MLXPLAT_CPLD_NR_LC_BASE 34 250 251 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr)) 252 #define MLXPLAT_CPLD_LC_ADDR 0x32 253 254 /* Masks and default values for watchdogs */ 255 #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7, 1) 256 #define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7, 0) & ~BIT(1)) 257 258 #define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7, 4) 259 #define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 260 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7, 1) 261 #define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7, 0) & ~BIT(4)) 262 #define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7, 0) & ~BIT(7)) 263 #define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7, 0) & ~BIT(6)) 264 #define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 265 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 266 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 267 268 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 269 270 /* Minimum power required for turning on Ethernet modular system (WATT) */ 271 #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 272 273 /* mlxplat_priv - platform private data 274 * @pdev_i2c - i2c controller platform device 275 * @pdev_mux - array of mux platform devices 276 * @pdev_hotplug - hotplug platform devices 277 * @pdev_led - led platform devices 278 * @pdev_io_regs - register access platform devices 279 * @pdev_fan - FAN platform devices 280 * @pdev_wd - array of watchdog platform devices 281 * @regmap: device register map 282 */ 283 struct mlxplat_priv { 284 struct platform_device *pdev_i2c; 285 struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS]; 286 struct platform_device *pdev_hotplug; 287 struct platform_device *pdev_led; 288 struct platform_device *pdev_io_regs; 289 struct platform_device *pdev_fan; 290 struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; 291 void *regmap; 292 }; 293 294 /* Regions for LPC I2C controller and LPC base register space */ 295 static const struct resource mlxplat_lpc_resources[] = { 296 [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, 297 MLXPLAT_CPLD_LPC_IO_RANGE, 298 "mlxplat_cpld_lpc_i2c_ctrl", IORESOURCE_IO), 299 [1] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR, 300 MLXPLAT_CPLD_LPC_IO_RANGE, 301 "mlxplat_cpld_lpc_regs", 302 IORESOURCE_IO), 303 }; 304 305 /* Platform i2c next generation systems data */ 306 static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { 307 { 308 .reg = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 309 .mask = MLXPLAT_CPLD_I2C_CAP_MASK, 310 .bit = MLXPLAT_CPLD_I2C_CAP_BIT, 311 }, 312 }; 313 314 static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = { 315 { 316 .data = mlxplat_mlxcpld_i2c_ng_items_data, 317 }, 318 }; 319 320 /* Platform next generation systems i2c data */ 321 static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { 322 .items = mlxplat_mlxcpld_i2c_ng_items, 323 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 324 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, 325 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, 326 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, 327 }; 328 329 /* Platform default channels */ 330 static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = { 331 { 332 MLXPLAT_CPLD_CH1, MLXPLAT_CPLD_CH1 + 1, MLXPLAT_CPLD_CH1 + 2, 333 MLXPLAT_CPLD_CH1 + 3, MLXPLAT_CPLD_CH1 + 4, MLXPLAT_CPLD_CH1 + 334 5, MLXPLAT_CPLD_CH1 + 6, MLXPLAT_CPLD_CH1 + 7 335 }, 336 { 337 MLXPLAT_CPLD_CH2, MLXPLAT_CPLD_CH2 + 1, MLXPLAT_CPLD_CH2 + 2, 338 MLXPLAT_CPLD_CH2 + 3, MLXPLAT_CPLD_CH2 + 4, MLXPLAT_CPLD_CH2 + 339 5, MLXPLAT_CPLD_CH2 + 6, MLXPLAT_CPLD_CH2 + 7 340 }, 341 }; 342 343 /* Platform channels for MSN21xx system family */ 344 static const int mlxplat_msn21xx_channels[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; 345 346 /* Platform mux data */ 347 static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { 348 { 349 .parent = 1, 350 .base_nr = MLXPLAT_CPLD_CH1, 351 .write_only = 1, 352 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 353 .reg_size = 1, 354 .idle_in_use = 1, 355 }, 356 { 357 .parent = 1, 358 .base_nr = MLXPLAT_CPLD_CH2, 359 .write_only = 1, 360 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 361 .reg_size = 1, 362 .idle_in_use = 1, 363 }, 364 365 }; 366 367 /* Platform mux configuration variables */ 368 static int mlxplat_max_adap_num; 369 static int mlxplat_mux_num; 370 static struct i2c_mux_reg_platform_data *mlxplat_mux_data; 371 372 /* Platform extended mux data */ 373 static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { 374 { 375 .parent = 1, 376 .base_nr = MLXPLAT_CPLD_CH1, 377 .write_only = 1, 378 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 379 .reg_size = 1, 380 .idle_in_use = 1, 381 }, 382 { 383 .parent = 1, 384 .base_nr = MLXPLAT_CPLD_CH2, 385 .write_only = 1, 386 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 387 .reg_size = 1, 388 .idle_in_use = 1, 389 }, 390 { 391 .parent = 1, 392 .base_nr = MLXPLAT_CPLD_CH3, 393 .write_only = 1, 394 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 395 .reg_size = 1, 396 .idle_in_use = 1, 397 }, 398 399 }; 400 401 /* Platform channels for modular system family */ 402 static const int mlxplat_modular_upper_channel[] = { 1 }; 403 static const int mlxplat_modular_channels[] = { 404 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 405 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 406 38, 39, 40 407 }; 408 409 /* Platform modular mux data */ 410 static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { 411 { 412 .parent = 1, 413 .base_nr = MLXPLAT_CPLD_CH1, 414 .write_only = 1, 415 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG4, 416 .reg_size = 1, 417 .idle_in_use = 1, 418 .values = mlxplat_modular_upper_channel, 419 .n_values = ARRAY_SIZE(mlxplat_modular_upper_channel), 420 }, 421 { 422 .parent = 1, 423 .base_nr = MLXPLAT_CPLD_CH2_ETH_MODULAR, 424 .write_only = 1, 425 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, 426 .reg_size = 1, 427 .idle_in_use = 1, 428 .values = mlxplat_modular_channels, 429 .n_values = ARRAY_SIZE(mlxplat_modular_channels), 430 }, 431 { 432 .parent = MLXPLAT_CPLD_CH1, 433 .base_nr = MLXPLAT_CPLD_CH3_ETH_MODULAR, 434 .write_only = 1, 435 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG3, 436 .reg_size = 1, 437 .idle_in_use = 1, 438 .values = mlxplat_msn21xx_channels, 439 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 440 }, 441 { 442 .parent = 1, 443 .base_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR, 444 .write_only = 1, 445 .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, 446 .reg_size = 1, 447 .idle_in_use = 1, 448 .values = mlxplat_msn21xx_channels, 449 .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), 450 }, 451 }; 452 453 /* Platform hotplug devices */ 454 static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { 455 { 456 I2C_BOARD_INFO("dps460", 0x59), 457 }, 458 { 459 I2C_BOARD_INFO("dps460", 0x58), 460 }, 461 }; 462 463 static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { 464 { 465 I2C_BOARD_INFO("dps460", 0x5b), 466 }, 467 { 468 I2C_BOARD_INFO("dps460", 0x5a), 469 }, 470 }; 471 472 static struct i2c_board_info mlxplat_mlxcpld_fan[] = { 473 { 474 I2C_BOARD_INFO("24c32", 0x50), 475 }, 476 { 477 I2C_BOARD_INFO("24c32", 0x50), 478 }, 479 { 480 I2C_BOARD_INFO("24c32", 0x50), 481 }, 482 { 483 I2C_BOARD_INFO("24c32", 0x50), 484 }, 485 }; 486 487 /* Platform hotplug comex carrier system family data */ 488 static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = { 489 { 490 .label = "psu1", 491 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 492 .mask = BIT(0), 493 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 494 }, 495 { 496 .label = "psu2", 497 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 498 .mask = BIT(1), 499 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 500 }, 501 }; 502 503 /* Platform hotplug default data */ 504 static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = { 505 { 506 .label = "psu1", 507 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 508 .mask = BIT(0), 509 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 510 }, 511 { 512 .label = "psu2", 513 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 514 .mask = BIT(1), 515 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 516 }, 517 }; 518 519 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = { 520 { 521 .label = "pwr1", 522 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 523 .mask = BIT(0), 524 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 525 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 526 }, 527 { 528 .label = "pwr2", 529 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 530 .mask = BIT(1), 531 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 532 .hpdev.nr = MLXPLAT_CPLD_PSU_DEFAULT_NR, 533 }, 534 }; 535 536 static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = { 537 { 538 .label = "pwr1", 539 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 540 .mask = BIT(0), 541 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 542 }, 543 { 544 .label = "pwr2", 545 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 546 .mask = BIT(1), 547 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 548 }, 549 }; 550 551 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = { 552 { 553 .label = "fan1", 554 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 555 .mask = BIT(0), 556 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[0], 557 .hpdev.nr = MLXPLAT_CPLD_FAN1_DEFAULT_NR, 558 }, 559 { 560 .label = "fan2", 561 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 562 .mask = BIT(1), 563 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[1], 564 .hpdev.nr = MLXPLAT_CPLD_FAN2_DEFAULT_NR, 565 }, 566 { 567 .label = "fan3", 568 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 569 .mask = BIT(2), 570 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[2], 571 .hpdev.nr = MLXPLAT_CPLD_FAN3_DEFAULT_NR, 572 }, 573 { 574 .label = "fan4", 575 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 576 .mask = BIT(3), 577 .hpdev.brdinfo = &mlxplat_mlxcpld_fan[3], 578 .hpdev.nr = MLXPLAT_CPLD_FAN4_DEFAULT_NR, 579 }, 580 }; 581 582 static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = { 583 { 584 .label = "asic1", 585 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 586 .mask = MLXPLAT_CPLD_ASIC_MASK, 587 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 588 }, 589 }; 590 591 static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = { 592 { 593 .data = mlxplat_mlxcpld_default_psu_items_data, 594 .aggr_mask = MLXPLAT_CPLD_AGGR_PSU_MASK_DEF, 595 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 596 .mask = MLXPLAT_CPLD_PSU_MASK, 597 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 598 .inversed = 1, 599 .health = false, 600 }, 601 { 602 .data = mlxplat_mlxcpld_default_pwr_items_data, 603 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 604 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 605 .mask = MLXPLAT_CPLD_PWR_MASK, 606 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 607 .inversed = 0, 608 .health = false, 609 }, 610 { 611 .data = mlxplat_mlxcpld_default_fan_items_data, 612 .aggr_mask = MLXPLAT_CPLD_AGGR_FAN_MASK_DEF, 613 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 614 .mask = MLXPLAT_CPLD_FAN_MASK, 615 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 616 .inversed = 1, 617 .health = false, 618 }, 619 { 620 .data = mlxplat_mlxcpld_default_asic_items_data, 621 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 622 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 623 .mask = MLXPLAT_CPLD_ASIC_MASK, 624 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 625 .inversed = 0, 626 .health = true, 627 }, 628 }; 629 630 static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = { 631 { 632 .data = mlxplat_mlxcpld_comex_psu_items_data, 633 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 634 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 635 .mask = MLXPLAT_CPLD_PSU_MASK, 636 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 637 .inversed = 1, 638 .health = false, 639 }, 640 { 641 .data = mlxplat_mlxcpld_default_pwr_items_data, 642 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 643 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 644 .mask = MLXPLAT_CPLD_PWR_MASK, 645 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 646 .inversed = 0, 647 .health = false, 648 }, 649 { 650 .data = mlxplat_mlxcpld_default_fan_items_data, 651 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 652 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 653 .mask = MLXPLAT_CPLD_FAN_MASK, 654 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_items_data), 655 .inversed = 1, 656 .health = false, 657 }, 658 { 659 .data = mlxplat_mlxcpld_default_asic_items_data, 660 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 661 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 662 .mask = MLXPLAT_CPLD_ASIC_MASK, 663 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 664 .inversed = 0, 665 .health = true, 666 }, 667 }; 668 669 static 670 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = { 671 .items = mlxplat_mlxcpld_default_items, 672 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_items), 673 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 674 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 675 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 676 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 677 }; 678 679 static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = { 680 { 681 .data = mlxplat_mlxcpld_comex_psu_items_data, 682 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 683 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 684 .mask = MLXPLAT_CPLD_PSU_MASK, 685 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_psu_items_data), 686 .inversed = 1, 687 .health = false, 688 }, 689 { 690 .data = mlxplat_mlxcpld_default_pwr_wc_items_data, 691 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_CARRIER, 692 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 693 .mask = MLXPLAT_CPLD_PWR_MASK, 694 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_pwr_items_data), 695 .inversed = 0, 696 .health = false, 697 }, 698 { 699 .data = mlxplat_mlxcpld_default_asic_items_data, 700 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 701 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 702 .mask = MLXPLAT_CPLD_ASIC_MASK, 703 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 704 .inversed = 0, 705 .health = true, 706 }, 707 }; 708 709 static 710 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = { 711 .items = mlxplat_mlxcpld_default_wc_items, 712 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_wc_items), 713 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 714 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 715 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 716 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 717 }; 718 719 static 720 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = { 721 .items = mlxplat_mlxcpld_comex_items, 722 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_items), 723 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 724 .mask = MLXPLAT_CPLD_AGGR_MASK_CARR_DEF, 725 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET, 726 .mask_low = MLXPLAT_CPLD_LOW_AGGRCX_MASK, 727 }; 728 729 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = { 730 { 731 .label = "pwr1", 732 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 733 .mask = BIT(0), 734 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 735 }, 736 { 737 .label = "pwr2", 738 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 739 .mask = BIT(1), 740 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 741 }, 742 }; 743 744 /* Platform hotplug MSN21xx system family data */ 745 static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = { 746 { 747 .data = mlxplat_mlxcpld_msn21xx_pwr_items_data, 748 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 749 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 750 .mask = MLXPLAT_CPLD_PWR_MASK, 751 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_pwr_items_data), 752 .inversed = 0, 753 .health = false, 754 }, 755 { 756 .data = mlxplat_mlxcpld_default_asic_items_data, 757 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 758 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 759 .mask = MLXPLAT_CPLD_ASIC_MASK, 760 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 761 .inversed = 0, 762 .health = true, 763 }, 764 }; 765 766 static 767 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = { 768 .items = mlxplat_mlxcpld_msn21xx_items, 769 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_items), 770 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 771 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 772 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 773 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 774 }; 775 776 /* Platform hotplug msn274x system family data */ 777 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = { 778 { 779 .label = "psu1", 780 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 781 .mask = BIT(0), 782 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 783 }, 784 { 785 .label = "psu2", 786 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 787 .mask = BIT(1), 788 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 789 }, 790 }; 791 792 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = { 793 { 794 .label = "pwr1", 795 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 796 .mask = BIT(0), 797 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 798 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 799 }, 800 { 801 .label = "pwr2", 802 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 803 .mask = BIT(1), 804 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 805 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 806 }, 807 }; 808 809 static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = { 810 { 811 .label = "fan1", 812 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 813 .mask = BIT(0), 814 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 815 }, 816 { 817 .label = "fan2", 818 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 819 .mask = BIT(1), 820 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 821 }, 822 { 823 .label = "fan3", 824 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 825 .mask = BIT(2), 826 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 827 }, 828 { 829 .label = "fan4", 830 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 831 .mask = BIT(3), 832 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 833 }, 834 }; 835 836 static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = { 837 { 838 .data = mlxplat_mlxcpld_msn274x_psu_items_data, 839 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 840 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 841 .mask = MLXPLAT_CPLD_PSU_MASK, 842 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_psu_items_data), 843 .inversed = 1, 844 .health = false, 845 }, 846 { 847 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 848 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 849 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 850 .mask = MLXPLAT_CPLD_PWR_MASK, 851 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 852 .inversed = 0, 853 .health = false, 854 }, 855 { 856 .data = mlxplat_mlxcpld_msn274x_fan_items_data, 857 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 858 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 859 .mask = MLXPLAT_CPLD_FAN_MASK, 860 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_fan_items_data), 861 .inversed = 1, 862 .health = false, 863 }, 864 { 865 .data = mlxplat_mlxcpld_default_asic_items_data, 866 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 867 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 868 .mask = MLXPLAT_CPLD_ASIC_MASK, 869 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 870 .inversed = 0, 871 .health = true, 872 }, 873 }; 874 875 static 876 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = { 877 .items = mlxplat_mlxcpld_msn274x_items, 878 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn274x_items), 879 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 880 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 881 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 882 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 883 }; 884 885 /* Platform hotplug MSN201x system family data */ 886 static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = { 887 { 888 .label = "pwr1", 889 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 890 .mask = BIT(0), 891 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 892 }, 893 { 894 .label = "pwr2", 895 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 896 .mask = BIT(1), 897 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 898 }, 899 }; 900 901 static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = { 902 { 903 .data = mlxplat_mlxcpld_msn201x_pwr_items_data, 904 .aggr_mask = MLXPLAT_CPLD_AGGR_PWR_MASK_DEF, 905 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 906 .mask = MLXPLAT_CPLD_PWR_MASK, 907 .count = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_pwr_items_data), 908 .inversed = 0, 909 .health = false, 910 }, 911 { 912 .data = mlxplat_mlxcpld_default_asic_items_data, 913 .aggr_mask = MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF, 914 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 915 .mask = MLXPLAT_CPLD_ASIC_MASK, 916 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 917 .inversed = 0, 918 .health = true, 919 }, 920 }; 921 922 static 923 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = { 924 .items = mlxplat_mlxcpld_msn201x_items, 925 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn201x_items), 926 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 927 .mask = MLXPLAT_CPLD_AGGR_MASK_DEF, 928 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 929 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 930 }; 931 932 /* Platform hotplug next generation system family data */ 933 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = { 934 { 935 .label = "psu1", 936 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 937 .mask = BIT(0), 938 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 939 }, 940 { 941 .label = "psu2", 942 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 943 .mask = BIT(1), 944 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 945 }, 946 }; 947 948 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = { 949 { 950 .label = "fan1", 951 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 952 .mask = BIT(0), 953 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 954 .bit = BIT(0), 955 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 956 }, 957 { 958 .label = "fan2", 959 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 960 .mask = BIT(1), 961 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 962 .bit = BIT(1), 963 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 964 }, 965 { 966 .label = "fan3", 967 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 968 .mask = BIT(2), 969 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 970 .bit = BIT(2), 971 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 972 }, 973 { 974 .label = "fan4", 975 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 976 .mask = BIT(3), 977 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 978 .bit = BIT(3), 979 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 980 }, 981 { 982 .label = "fan5", 983 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 984 .mask = BIT(4), 985 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 986 .bit = BIT(4), 987 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 988 }, 989 { 990 .label = "fan6", 991 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 992 .mask = BIT(5), 993 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 994 .bit = BIT(5), 995 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 996 }, 997 { 998 .label = "fan7", 999 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1000 .mask = BIT(6), 1001 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 1002 .bit = BIT(6), 1003 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1004 }, 1005 }; 1006 1007 static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = { 1008 { 1009 .data = mlxplat_mlxcpld_default_ng_psu_items_data, 1010 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1011 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1012 .mask = MLXPLAT_CPLD_PSU_MASK, 1013 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_psu_items_data), 1014 .inversed = 1, 1015 .health = false, 1016 }, 1017 { 1018 .data = mlxplat_mlxcpld_default_ng_pwr_items_data, 1019 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1020 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1021 .mask = MLXPLAT_CPLD_PWR_MASK, 1022 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_pwr_items_data), 1023 .inversed = 0, 1024 .health = false, 1025 }, 1026 { 1027 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1028 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1029 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1030 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1031 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1032 .inversed = 1, 1033 .health = false, 1034 }, 1035 { 1036 .data = mlxplat_mlxcpld_default_asic_items_data, 1037 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1038 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1039 .mask = MLXPLAT_CPLD_ASIC_MASK, 1040 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1041 .inversed = 0, 1042 .health = true, 1043 }, 1044 }; 1045 1046 static 1047 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = { 1048 .items = mlxplat_mlxcpld_default_ng_items, 1049 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_items), 1050 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1051 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1052 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1053 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1054 }; 1055 1056 /* Platform hotplug extended system family data */ 1057 static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = { 1058 { 1059 .label = "psu1", 1060 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1061 .mask = BIT(0), 1062 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1063 }, 1064 { 1065 .label = "psu2", 1066 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1067 .mask = BIT(1), 1068 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1069 }, 1070 { 1071 .label = "psu3", 1072 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1073 .mask = BIT(2), 1074 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1075 }, 1076 { 1077 .label = "psu4", 1078 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1079 .mask = BIT(3), 1080 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1081 }, 1082 }; 1083 1084 static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = { 1085 { 1086 .label = "pwr1", 1087 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1088 .mask = BIT(0), 1089 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1090 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1091 }, 1092 { 1093 .label = "pwr2", 1094 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1095 .mask = BIT(1), 1096 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1097 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1098 }, 1099 { 1100 .label = "pwr3", 1101 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1102 .mask = BIT(2), 1103 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1104 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1105 }, 1106 { 1107 .label = "pwr4", 1108 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1109 .mask = BIT(3), 1110 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1111 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1112 }, 1113 }; 1114 1115 static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = { 1116 { 1117 .data = mlxplat_mlxcpld_ext_psu_items_data, 1118 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1119 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1120 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1121 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1122 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1123 .inversed = 1, 1124 .health = false, 1125 }, 1126 { 1127 .data = mlxplat_mlxcpld_ext_pwr_items_data, 1128 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1129 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1130 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1131 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1132 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1133 .inversed = 0, 1134 .health = false, 1135 }, 1136 { 1137 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1138 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1139 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1140 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1141 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1142 .inversed = 1, 1143 .health = false, 1144 }, 1145 { 1146 .data = mlxplat_mlxcpld_default_asic_items_data, 1147 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1148 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1149 .mask = MLXPLAT_CPLD_ASIC_MASK, 1150 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_asic_items_data), 1151 .inversed = 0, 1152 .health = true, 1153 }, 1154 }; 1155 1156 static 1157 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { 1158 .items = mlxplat_mlxcpld_ext_items, 1159 .counter = ARRAY_SIZE(mlxplat_mlxcpld_ext_items), 1160 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 1161 .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, 1162 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 1163 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 1164 }; 1165 1166 static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { 1167 { 1168 .label = "pwr1", 1169 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1170 .mask = BIT(0), 1171 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], 1172 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1173 }, 1174 { 1175 .label = "pwr2", 1176 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1177 .mask = BIT(1), 1178 .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], 1179 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1180 }, 1181 { 1182 .label = "pwr3", 1183 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1184 .mask = BIT(2), 1185 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], 1186 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1187 }, 1188 { 1189 .label = "pwr4", 1190 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1191 .mask = BIT(3), 1192 .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], 1193 .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, 1194 }, 1195 }; 1196 1197 static 1198 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = { 1199 .irq = MLXPLAT_CPLD_LPC_SYSIRQ, 1200 }; 1201 1202 static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = { 1203 { 1204 .label = "asic1", 1205 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1206 .mask = MLXPLAT_CPLD_ASIC_MASK, 1207 .hpdev.nr = MLXPLAT_CPLD_NR_NONE, 1208 }, 1209 }; 1210 1211 static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = { 1212 { 1213 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1214 .platform_data = &mlxplat_mlxcpld_lc_act, 1215 }, 1216 { 1217 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1218 .platform_data = &mlxplat_mlxcpld_lc_act, 1219 }, 1220 { 1221 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1222 .platform_data = &mlxplat_mlxcpld_lc_act, 1223 }, 1224 { 1225 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1226 .platform_data = &mlxplat_mlxcpld_lc_act, 1227 }, 1228 { 1229 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1230 .platform_data = &mlxplat_mlxcpld_lc_act, 1231 }, 1232 { 1233 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1234 .platform_data = &mlxplat_mlxcpld_lc_act, 1235 }, 1236 { 1237 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1238 .platform_data = &mlxplat_mlxcpld_lc_act, 1239 }, 1240 { 1241 I2C_BOARD_INFO("mlxreg-lc", MLXPLAT_CPLD_LC_ADDR), 1242 .platform_data = &mlxplat_mlxcpld_lc_act, 1243 }, 1244 }; 1245 1246 static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = { 1247 { 1248 .identity = "lc1", 1249 }, 1250 { 1251 .identity = "lc2", 1252 }, 1253 { 1254 .identity = "lc3", 1255 }, 1256 { 1257 .identity = "lc4", 1258 }, 1259 { 1260 .identity = "lc5", 1261 }, 1262 { 1263 .identity = "lc6", 1264 }, 1265 { 1266 .identity = "lc7", 1267 }, 1268 { 1269 .identity = "lc8", 1270 }, 1271 }; 1272 1273 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = { 1274 { 1275 .label = "lc1_present", 1276 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1277 .mask = BIT(0), 1278 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1279 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1280 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1281 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1282 .slot = 1, 1283 }, 1284 { 1285 .label = "lc2_present", 1286 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1287 .mask = BIT(1), 1288 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1289 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1290 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1291 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1292 .slot = 2, 1293 }, 1294 { 1295 .label = "lc3_present", 1296 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1297 .mask = BIT(2), 1298 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1299 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1300 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1301 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1302 .slot = 3, 1303 }, 1304 { 1305 .label = "lc4_present", 1306 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1307 .mask = BIT(3), 1308 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1309 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1310 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1311 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1312 .slot = 4, 1313 }, 1314 { 1315 .label = "lc5_present", 1316 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1317 .mask = BIT(4), 1318 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1319 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1320 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1321 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1322 .slot = 5, 1323 }, 1324 { 1325 .label = "lc6_present", 1326 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1327 .mask = BIT(5), 1328 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1329 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1330 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1331 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1332 .slot = 6, 1333 }, 1334 { 1335 .label = "lc7_present", 1336 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1337 .mask = BIT(6), 1338 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1339 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1340 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1341 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1342 .slot = 7, 1343 }, 1344 { 1345 .label = "lc8_present", 1346 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1347 .mask = BIT(7), 1348 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1349 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1350 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1351 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1352 .slot = 8, 1353 }, 1354 }; 1355 1356 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = { 1357 { 1358 .label = "lc1_verified", 1359 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1360 .mask = BIT(0), 1361 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1362 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1363 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1364 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1365 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1366 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1367 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1368 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1369 .slot = 1, 1370 }, 1371 { 1372 .label = "lc2_verified", 1373 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1374 .mask = BIT(1), 1375 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1376 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1377 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1378 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1379 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1380 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1381 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1382 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1383 .slot = 2, 1384 }, 1385 { 1386 .label = "lc3_verified", 1387 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1388 .mask = BIT(2), 1389 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1390 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1391 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1392 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1393 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1394 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1395 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1396 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1397 .slot = 3, 1398 }, 1399 { 1400 .label = "lc4_verified", 1401 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1402 .mask = BIT(3), 1403 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1404 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1405 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1406 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1407 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1408 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1409 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1410 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1411 .slot = 4, 1412 }, 1413 { 1414 .label = "lc5_verified", 1415 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1416 .mask = BIT(4), 1417 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1418 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1419 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1420 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1421 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1422 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1423 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1424 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1425 .slot = 5, 1426 }, 1427 { 1428 .label = "lc6_verified", 1429 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1430 .mask = BIT(5), 1431 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1432 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1433 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1434 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1435 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1436 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1437 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1438 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1439 .slot = 6, 1440 }, 1441 { 1442 .label = "lc7_verified", 1443 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1444 .mask = BIT(6), 1445 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1446 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1447 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1448 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1449 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1450 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1451 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1452 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1453 .slot = 7, 1454 }, 1455 { 1456 .label = "lc8_verified", 1457 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1458 .mask = BIT(7), 1459 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1460 .reg_sync = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1461 .reg_pwr = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 1462 .reg_ena = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 1463 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1464 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1465 .hpdev.action = MLXREG_HOTPLUG_DEVICE_PLATFORM_ACTION, 1466 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1467 .slot = 8, 1468 }, 1469 }; 1470 1471 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = { 1472 { 1473 .label = "lc1_powered", 1474 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1475 .mask = BIT(0), 1476 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1477 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1478 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1479 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1480 .slot = 1, 1481 }, 1482 { 1483 .label = "lc2_powered", 1484 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1485 .mask = BIT(1), 1486 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1487 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1488 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1489 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1490 .slot = 2, 1491 }, 1492 { 1493 .label = "lc3_powered", 1494 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1495 .mask = BIT(2), 1496 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1497 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1498 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1499 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1500 .slot = 3, 1501 }, 1502 { 1503 .label = "lc4_powered", 1504 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1505 .mask = BIT(3), 1506 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1507 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1508 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1509 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1510 .slot = 4, 1511 }, 1512 { 1513 .label = "lc5_powered", 1514 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1515 .mask = BIT(4), 1516 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1517 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1518 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1519 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1520 .slot = 5, 1521 }, 1522 { 1523 .label = "lc6_powered", 1524 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1525 .mask = BIT(5), 1526 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1527 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1528 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1529 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1530 .slot = 6, 1531 }, 1532 { 1533 .label = "lc7_powered", 1534 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1535 .mask = BIT(6), 1536 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1537 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1538 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1539 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1540 .slot = 7, 1541 }, 1542 { 1543 .label = "lc8_powered", 1544 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1545 .mask = BIT(7), 1546 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1547 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1548 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1549 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1550 .slot = 8, 1551 }, 1552 }; 1553 1554 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = { 1555 { 1556 .label = "lc1_ready", 1557 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1558 .mask = BIT(0), 1559 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1560 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1561 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1562 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1563 .slot = 1, 1564 }, 1565 { 1566 .label = "lc2_ready", 1567 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1568 .mask = BIT(1), 1569 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1570 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1571 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1572 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1573 .slot = 2, 1574 }, 1575 { 1576 .label = "lc3_ready", 1577 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1578 .mask = BIT(2), 1579 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1580 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1581 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1582 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1583 .slot = 3, 1584 }, 1585 { 1586 .label = "lc4_ready", 1587 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1588 .mask = BIT(3), 1589 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1590 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1591 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1592 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1593 .slot = 4, 1594 }, 1595 { 1596 .label = "lc5_ready", 1597 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1598 .mask = BIT(4), 1599 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1600 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1601 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1602 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1603 .slot = 5, 1604 }, 1605 { 1606 .label = "lc6_ready", 1607 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1608 .mask = BIT(5), 1609 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1610 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1611 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1612 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1613 .slot = 6, 1614 }, 1615 { 1616 .label = "lc7_ready", 1617 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1618 .mask = BIT(6), 1619 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1620 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1621 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1622 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1623 .slot = 7, 1624 }, 1625 { 1626 .label = "lc8_ready", 1627 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1628 .mask = BIT(7), 1629 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1630 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1631 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1632 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1633 .slot = 8, 1634 }, 1635 }; 1636 1637 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = { 1638 { 1639 .label = "lc1_synced", 1640 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1641 .mask = BIT(0), 1642 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1643 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1644 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1645 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1646 .slot = 1, 1647 }, 1648 { 1649 .label = "lc2_synced", 1650 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1651 .mask = BIT(1), 1652 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1653 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1654 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1655 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1656 .slot = 2, 1657 }, 1658 { 1659 .label = "lc3_synced", 1660 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1661 .mask = BIT(2), 1662 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1663 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1664 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1665 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1666 .slot = 3, 1667 }, 1668 { 1669 .label = "lc4_synced", 1670 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1671 .mask = BIT(3), 1672 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1673 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1674 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1675 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1676 .slot = 4, 1677 }, 1678 { 1679 .label = "lc5_synced", 1680 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1681 .mask = BIT(4), 1682 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1683 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1684 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1685 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1686 .slot = 5, 1687 }, 1688 { 1689 .label = "lc6_synced", 1690 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1691 .mask = BIT(5), 1692 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1693 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1694 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1695 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1696 .slot = 6, 1697 }, 1698 { 1699 .label = "lc7_synced", 1700 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1701 .mask = BIT(6), 1702 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1703 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1704 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1705 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1706 .slot = 7, 1707 }, 1708 { 1709 .label = "lc8_synced", 1710 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1711 .mask = BIT(7), 1712 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1713 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1714 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1715 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1716 .slot = 8, 1717 }, 1718 }; 1719 1720 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = { 1721 { 1722 .label = "lc1_active", 1723 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1724 .mask = BIT(0), 1725 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1726 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1727 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1728 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1729 .slot = 1, 1730 }, 1731 { 1732 .label = "lc2_active", 1733 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1734 .mask = BIT(1), 1735 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1736 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1737 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1738 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1739 .slot = 2, 1740 }, 1741 { 1742 .label = "lc3_active", 1743 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1744 .mask = BIT(2), 1745 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1746 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1747 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1748 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1749 .slot = 3, 1750 }, 1751 { 1752 .label = "lc4_active", 1753 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1754 .mask = BIT(3), 1755 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1756 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1757 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1758 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1759 .slot = 4, 1760 }, 1761 { 1762 .label = "lc5_active", 1763 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1764 .mask = BIT(4), 1765 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1766 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1767 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1768 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1769 .slot = 5, 1770 }, 1771 { 1772 .label = "lc6_active", 1773 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1774 .mask = BIT(5), 1775 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1776 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1777 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1778 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1779 .slot = 6, 1780 }, 1781 { 1782 .label = "lc7_active", 1783 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1784 .mask = BIT(6), 1785 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1786 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1787 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1788 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1789 .slot = 7, 1790 }, 1791 { 1792 .label = "lc8_active", 1793 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1794 .mask = BIT(7), 1795 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1796 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1797 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1798 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1799 .slot = 8, 1800 }, 1801 }; 1802 1803 static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = { 1804 { 1805 .label = "lc1_shutdown", 1806 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1807 .mask = BIT(0), 1808 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[0], 1809 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(0), 1810 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1811 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[0], 1812 .slot = 1, 1813 }, 1814 { 1815 .label = "lc2_shutdown", 1816 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1817 .mask = BIT(1), 1818 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[1], 1819 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(1), 1820 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1821 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[1], 1822 .slot = 2, 1823 }, 1824 { 1825 .label = "lc3_shutdown", 1826 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1827 .mask = BIT(2), 1828 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[2], 1829 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(2), 1830 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1831 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[2], 1832 .slot = 3, 1833 }, 1834 { 1835 .label = "lc4_shutdown", 1836 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1837 .mask = BIT(3), 1838 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[3], 1839 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(3), 1840 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1841 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[3], 1842 .slot = 4, 1843 }, 1844 { 1845 .label = "lc5_shutdown", 1846 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1847 .mask = BIT(4), 1848 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[4], 1849 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(4), 1850 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1851 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[4], 1852 .slot = 5, 1853 }, 1854 { 1855 .label = "lc6_shutdown", 1856 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1857 .mask = BIT(5), 1858 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[5], 1859 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(5), 1860 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1861 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[5], 1862 .slot = 6, 1863 }, 1864 { 1865 .label = "lc7_shutdown", 1866 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1867 .mask = BIT(6), 1868 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[6], 1869 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(6), 1870 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1871 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[6], 1872 .slot = 7, 1873 }, 1874 { 1875 .label = "lc8_shutdown", 1876 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1877 .mask = BIT(7), 1878 .hpdev.brdinfo = &mlxplat_mlxcpld_lc_i2c_dev[7], 1879 .hpdev.nr = MLXPLAT_CPLD_NR_LC_SET(7), 1880 .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, 1881 .hpdev.notifier = &mlxplat_mlxcpld_modular_lc_notifier[7], 1882 .slot = 8, 1883 }, 1884 }; 1885 1886 static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = { 1887 { 1888 .data = mlxplat_mlxcpld_ext_psu_items_data, 1889 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1890 .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, 1891 .mask = MLXPLAT_CPLD_PSU_EXT_MASK, 1892 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1893 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_psu_items_data), 1894 .inversed = 1, 1895 .health = false, 1896 }, 1897 { 1898 .data = mlxplat_mlxcpld_modular_pwr_items_data, 1899 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1900 .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, 1901 .mask = MLXPLAT_CPLD_PWR_EXT_MASK, 1902 .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 1903 .count = ARRAY_SIZE(mlxplat_mlxcpld_ext_pwr_items_data), 1904 .inversed = 0, 1905 .health = false, 1906 }, 1907 { 1908 .data = mlxplat_mlxcpld_default_ng_fan_items_data, 1909 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1910 .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 1911 .mask = MLXPLAT_CPLD_FAN_NG_MASK, 1912 .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), 1913 .inversed = 1, 1914 .health = false, 1915 }, 1916 { 1917 .data = mlxplat_mlxcpld_modular_asic_items_data, 1918 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, 1919 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 1920 .mask = MLXPLAT_CPLD_ASIC_MASK, 1921 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_asic_items_data), 1922 .inversed = 0, 1923 .health = true, 1924 }, 1925 { 1926 .data = mlxplat_mlxcpld_modular_lc_pr_items_data, 1927 .kind = MLXREG_HOTPLUG_LC_PRESENT, 1928 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1929 .reg = MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET, 1930 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1931 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pr_items_data), 1932 .inversed = 1, 1933 .health = false, 1934 }, 1935 { 1936 .data = mlxplat_mlxcpld_modular_lc_ver_items_data, 1937 .kind = MLXREG_HOTPLUG_LC_VERIFIED, 1938 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1939 .reg = MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET, 1940 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1941 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ver_items_data), 1942 .inversed = 0, 1943 .health = false, 1944 }, 1945 { 1946 .data = mlxplat_mlxcpld_modular_lc_pg_data, 1947 .kind = MLXREG_HOTPLUG_LC_POWERED, 1948 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1949 .reg = MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET, 1950 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1951 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_pg_data), 1952 .inversed = 0, 1953 .health = false, 1954 }, 1955 { 1956 .data = mlxplat_mlxcpld_modular_lc_ready_data, 1957 .kind = MLXREG_HOTPLUG_LC_READY, 1958 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1959 .reg = MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET, 1960 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1961 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_ready_data), 1962 .inversed = 0, 1963 .health = false, 1964 }, 1965 { 1966 .data = mlxplat_mlxcpld_modular_lc_synced_data, 1967 .kind = MLXREG_HOTPLUG_LC_SYNCED, 1968 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1969 .reg = MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET, 1970 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1971 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_synced_data), 1972 .inversed = 0, 1973 .health = false, 1974 }, 1975 { 1976 .data = mlxplat_mlxcpld_modular_lc_act_data, 1977 .kind = MLXREG_HOTPLUG_LC_ACTIVE, 1978 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1979 .reg = MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET, 1980 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1981 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_act_data), 1982 .inversed = 0, 1983 .health = false, 1984 }, 1985 { 1986 .data = mlxplat_mlxcpld_modular_lc_sd_data, 1987 .kind = MLXREG_HOTPLUG_LC_THERMAL, 1988 .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_LC, 1989 .reg = MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET, 1990 .mask = MLXPLAT_CPLD_LPC_LC_MASK, 1991 .count = ARRAY_SIZE(mlxplat_mlxcpld_modular_lc_sd_data), 1992 .inversed = 0, 1993 .health = false, 1994 }, 1995 }; 1996 1997 static 1998 struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = { 1999 .items = mlxplat_mlxcpld_modular_items, 2000 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_items), 2001 .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, 2002 .mask = MLXPLAT_CPLD_AGGR_MASK_MODULAR, 2003 .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, 2004 .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, 2005 }; 2006 2007 /* Platform led default data */ 2008 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { 2009 { 2010 .label = "status:green", 2011 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2012 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2013 }, 2014 { 2015 .label = "status:red", 2016 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2017 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2018 }, 2019 { 2020 .label = "psu:green", 2021 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2022 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2023 }, 2024 { 2025 .label = "psu:red", 2026 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2027 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2028 }, 2029 { 2030 .label = "fan1:green", 2031 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2032 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2033 }, 2034 { 2035 .label = "fan1:red", 2036 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2037 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2038 }, 2039 { 2040 .label = "fan2:green", 2041 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2042 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2043 }, 2044 { 2045 .label = "fan2:red", 2046 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2047 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2048 }, 2049 { 2050 .label = "fan3:green", 2051 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2052 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2053 }, 2054 { 2055 .label = "fan3:red", 2056 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2057 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2058 }, 2059 { 2060 .label = "fan4:green", 2061 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2062 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2063 }, 2064 { 2065 .label = "fan4:red", 2066 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2067 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2068 }, 2069 }; 2070 2071 static struct mlxreg_core_platform_data mlxplat_default_led_data = { 2072 .data = mlxplat_mlxcpld_default_led_data, 2073 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_data), 2074 }; 2075 2076 /* Platform led default data for water cooling */ 2077 static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = { 2078 { 2079 .label = "status:green", 2080 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2081 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2082 }, 2083 { 2084 .label = "status:red", 2085 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2086 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2087 }, 2088 { 2089 .label = "psu:green", 2090 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2091 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2092 }, 2093 { 2094 .label = "psu:red", 2095 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2096 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2097 }, 2098 }; 2099 2100 static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = { 2101 .data = mlxplat_mlxcpld_default_led_wc_data, 2102 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_led_wc_data), 2103 }; 2104 2105 /* Platform led MSN21xx system family data */ 2106 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = { 2107 { 2108 .label = "status:green", 2109 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2110 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2111 }, 2112 { 2113 .label = "status:red", 2114 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2115 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2116 }, 2117 { 2118 .label = "fan:green", 2119 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2120 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2121 }, 2122 { 2123 .label = "fan:red", 2124 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2125 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2126 }, 2127 { 2128 .label = "psu1:green", 2129 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2130 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2131 }, 2132 { 2133 .label = "psu1:red", 2134 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2135 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2136 }, 2137 { 2138 .label = "psu2:green", 2139 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2140 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2141 }, 2142 { 2143 .label = "psu2:red", 2144 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2145 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2146 }, 2147 { 2148 .label = "uid:blue", 2149 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2150 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2151 }, 2152 }; 2153 2154 static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = { 2155 .data = mlxplat_mlxcpld_msn21xx_led_data, 2156 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_led_data), 2157 }; 2158 2159 /* Platform led for default data for 200GbE systems */ 2160 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = { 2161 { 2162 .label = "status:green", 2163 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2164 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2165 }, 2166 { 2167 .label = "status:orange", 2168 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2169 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2170 }, 2171 { 2172 .label = "psu:green", 2173 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2174 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2175 }, 2176 { 2177 .label = "psu:orange", 2178 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2179 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2180 }, 2181 { 2182 .label = "fan1:green", 2183 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2184 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2185 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2186 .bit = BIT(0), 2187 }, 2188 { 2189 .label = "fan1:orange", 2190 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2191 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2192 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2193 .bit = BIT(0), 2194 }, 2195 { 2196 .label = "fan2:green", 2197 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2198 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2199 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2200 .bit = BIT(1), 2201 }, 2202 { 2203 .label = "fan2:orange", 2204 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2205 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2206 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2207 .bit = BIT(1), 2208 }, 2209 { 2210 .label = "fan3:green", 2211 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2212 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2213 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2214 .bit = BIT(2), 2215 }, 2216 { 2217 .label = "fan3:orange", 2218 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2219 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2220 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2221 .bit = BIT(2), 2222 }, 2223 { 2224 .label = "fan4:green", 2225 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2226 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2227 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2228 .bit = BIT(3), 2229 }, 2230 { 2231 .label = "fan4:orange", 2232 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2233 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2234 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2235 .bit = BIT(3), 2236 }, 2237 { 2238 .label = "fan5:green", 2239 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2240 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2241 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2242 .bit = BIT(4), 2243 }, 2244 { 2245 .label = "fan5:orange", 2246 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2247 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2248 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2249 .bit = BIT(4), 2250 }, 2251 { 2252 .label = "fan6:green", 2253 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2254 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2255 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2256 .bit = BIT(5), 2257 }, 2258 { 2259 .label = "fan6:orange", 2260 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2261 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2262 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2263 .bit = BIT(5), 2264 }, 2265 { 2266 .label = "fan7:green", 2267 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2268 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2269 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2270 .bit = BIT(6), 2271 }, 2272 { 2273 .label = "fan7:orange", 2274 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2275 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2276 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2277 .bit = BIT(6), 2278 }, 2279 { 2280 .label = "uid:blue", 2281 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2282 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2283 }, 2284 }; 2285 2286 static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = { 2287 .data = mlxplat_mlxcpld_default_ng_led_data, 2288 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_led_data), 2289 }; 2290 2291 /* Platform led for Comex based 100GbE systems */ 2292 static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = { 2293 { 2294 .label = "status:green", 2295 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2296 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2297 }, 2298 { 2299 .label = "status:red", 2300 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2301 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2302 }, 2303 { 2304 .label = "psu:green", 2305 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2306 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2307 }, 2308 { 2309 .label = "psu:red", 2310 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2311 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2312 }, 2313 { 2314 .label = "fan1:green", 2315 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2316 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2317 }, 2318 { 2319 .label = "fan1:red", 2320 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2321 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2322 }, 2323 { 2324 .label = "fan2:green", 2325 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2326 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2327 }, 2328 { 2329 .label = "fan2:red", 2330 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2331 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2332 }, 2333 { 2334 .label = "fan3:green", 2335 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2336 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2337 }, 2338 { 2339 .label = "fan3:red", 2340 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2341 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2342 }, 2343 { 2344 .label = "fan4:green", 2345 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2346 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2347 }, 2348 { 2349 .label = "fan4:red", 2350 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2351 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2352 }, 2353 { 2354 .label = "uid:blue", 2355 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2356 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2357 }, 2358 }; 2359 2360 static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = { 2361 .data = mlxplat_mlxcpld_comex_100G_led_data, 2362 .counter = ARRAY_SIZE(mlxplat_mlxcpld_comex_100G_led_data), 2363 }; 2364 2365 /* Platform led for data for modular systems */ 2366 static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = { 2367 { 2368 .label = "status:green", 2369 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2370 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2371 }, 2372 { 2373 .label = "status:orange", 2374 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2375 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK 2376 }, 2377 { 2378 .label = "psu:green", 2379 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2380 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2381 }, 2382 { 2383 .label = "psu:orange", 2384 .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, 2385 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2386 }, 2387 { 2388 .label = "fan1:green", 2389 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2390 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2391 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2392 .bit = BIT(0), 2393 }, 2394 { 2395 .label = "fan1:orange", 2396 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2397 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2398 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2399 .bit = BIT(0), 2400 }, 2401 { 2402 .label = "fan2:green", 2403 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2404 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2405 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2406 .bit = BIT(1), 2407 }, 2408 { 2409 .label = "fan2:orange", 2410 .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, 2411 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2412 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2413 .bit = BIT(1), 2414 }, 2415 { 2416 .label = "fan3:green", 2417 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2418 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2419 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2420 .bit = BIT(2), 2421 }, 2422 { 2423 .label = "fan3:orange", 2424 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2425 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2426 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2427 .bit = BIT(2), 2428 }, 2429 { 2430 .label = "fan4:green", 2431 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2432 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2433 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2434 .bit = BIT(3), 2435 }, 2436 { 2437 .label = "fan4:orange", 2438 .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, 2439 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2440 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2441 .bit = BIT(3), 2442 }, 2443 { 2444 .label = "fan5:green", 2445 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2446 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2447 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2448 .bit = BIT(4), 2449 }, 2450 { 2451 .label = "fan5:orange", 2452 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2453 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2454 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2455 .bit = BIT(4), 2456 }, 2457 { 2458 .label = "fan6:green", 2459 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2460 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2461 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2462 .bit = BIT(5), 2463 }, 2464 { 2465 .label = "fan6:orange", 2466 .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, 2467 .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, 2468 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2469 .bit = BIT(5), 2470 }, 2471 { 2472 .label = "fan7:green", 2473 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2474 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2475 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2476 .bit = BIT(6), 2477 }, 2478 { 2479 .label = "fan7:orange", 2480 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2481 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2482 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 2483 .bit = BIT(6), 2484 }, 2485 { 2486 .label = "uid:blue", 2487 .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, 2488 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2489 }, 2490 { 2491 .label = "fan_front:green", 2492 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2493 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2494 }, 2495 { 2496 .label = "fan_front:orange", 2497 .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, 2498 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2499 }, 2500 { 2501 .label = "mgmt:green", 2502 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 2503 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2504 }, 2505 { 2506 .label = "mgmt:orange", 2507 .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, 2508 .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, 2509 }, 2510 }; 2511 2512 static struct mlxreg_core_platform_data mlxplat_modular_led_data = { 2513 .data = mlxplat_mlxcpld_modular_led_data, 2514 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_led_data), 2515 }; 2516 2517 /* Platform register access default */ 2518 static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { 2519 { 2520 .label = "cpld1_version", 2521 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2522 .bit = GENMASK(7, 0), 2523 .mode = 0444, 2524 }, 2525 { 2526 .label = "cpld2_version", 2527 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2528 .bit = GENMASK(7, 0), 2529 .mode = 0444, 2530 }, 2531 { 2532 .label = "cpld1_pn", 2533 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2534 .bit = GENMASK(15, 0), 2535 .mode = 0444, 2536 .regnum = 2, 2537 }, 2538 { 2539 .label = "cpld2_pn", 2540 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2541 .bit = GENMASK(15, 0), 2542 .mode = 0444, 2543 .regnum = 2, 2544 }, 2545 { 2546 .label = "cpld1_version_min", 2547 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2548 .bit = GENMASK(7, 0), 2549 .mode = 0444, 2550 }, 2551 { 2552 .label = "cpld2_version_min", 2553 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2554 .bit = GENMASK(7, 0), 2555 .mode = 0444, 2556 }, 2557 { 2558 .label = "reset_long_pb", 2559 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2560 .mask = GENMASK(7, 0) & ~BIT(0), 2561 .mode = 0444, 2562 }, 2563 { 2564 .label = "reset_short_pb", 2565 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2566 .mask = GENMASK(7, 0) & ~BIT(1), 2567 .mode = 0444, 2568 }, 2569 { 2570 .label = "reset_aux_pwr_or_ref", 2571 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2572 .mask = GENMASK(7, 0) & ~BIT(2), 2573 .mode = 0444, 2574 }, 2575 { 2576 .label = "reset_main_pwr_fail", 2577 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2578 .mask = GENMASK(7, 0) & ~BIT(3), 2579 .mode = 0444, 2580 }, 2581 { 2582 .label = "reset_sw_reset", 2583 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2584 .mask = GENMASK(7, 0) & ~BIT(4), 2585 .mode = 0444, 2586 }, 2587 { 2588 .label = "reset_fw_reset", 2589 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2590 .mask = GENMASK(7, 0) & ~BIT(5), 2591 .mode = 0444, 2592 }, 2593 { 2594 .label = "reset_hotswap_or_wd", 2595 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2596 .mask = GENMASK(7, 0) & ~BIT(6), 2597 .mode = 0444, 2598 }, 2599 { 2600 .label = "reset_asic_thermal", 2601 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2602 .mask = GENMASK(7, 0) & ~BIT(7), 2603 .mode = 0444, 2604 }, 2605 { 2606 .label = "psu1_on", 2607 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2608 .mask = GENMASK(7, 0) & ~BIT(0), 2609 .mode = 0200, 2610 }, 2611 { 2612 .label = "psu2_on", 2613 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2614 .mask = GENMASK(7, 0) & ~BIT(1), 2615 .mode = 0200, 2616 }, 2617 { 2618 .label = "pwr_cycle", 2619 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2620 .mask = GENMASK(7, 0) & ~BIT(2), 2621 .mode = 0200, 2622 }, 2623 { 2624 .label = "pwr_down", 2625 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2626 .mask = GENMASK(7, 0) & ~BIT(3), 2627 .mode = 0200, 2628 }, 2629 { 2630 .label = "select_iio", 2631 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 2632 .mask = GENMASK(7, 0) & ~BIT(6), 2633 .mode = 0644, 2634 }, 2635 { 2636 .label = "asic_health", 2637 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2638 .mask = MLXPLAT_CPLD_ASIC_MASK, 2639 .bit = 1, 2640 .mode = 0444, 2641 }, 2642 }; 2643 2644 static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = { 2645 .data = mlxplat_mlxcpld_default_regs_io_data, 2646 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_regs_io_data), 2647 }; 2648 2649 /* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ 2650 static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = { 2651 { 2652 .label = "cpld1_version", 2653 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2654 .bit = GENMASK(7, 0), 2655 .mode = 0444, 2656 }, 2657 { 2658 .label = "cpld2_version", 2659 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2660 .bit = GENMASK(7, 0), 2661 .mode = 0444, 2662 }, 2663 { 2664 .label = "cpld1_pn", 2665 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2666 .bit = GENMASK(15, 0), 2667 .mode = 0444, 2668 .regnum = 2, 2669 }, 2670 { 2671 .label = "cpld2_pn", 2672 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2673 .bit = GENMASK(15, 0), 2674 .mode = 0444, 2675 .regnum = 2, 2676 }, 2677 { 2678 .label = "cpld1_version_min", 2679 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2680 .bit = GENMASK(7, 0), 2681 .mode = 0444, 2682 }, 2683 { 2684 .label = "cpld2_version_min", 2685 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2686 .bit = GENMASK(7, 0), 2687 .mode = 0444, 2688 }, 2689 { 2690 .label = "reset_long_pb", 2691 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2692 .mask = GENMASK(7, 0) & ~BIT(0), 2693 .mode = 0444, 2694 }, 2695 { 2696 .label = "reset_short_pb", 2697 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2698 .mask = GENMASK(7, 0) & ~BIT(1), 2699 .mode = 0444, 2700 }, 2701 { 2702 .label = "reset_aux_pwr_or_ref", 2703 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2704 .mask = GENMASK(7, 0) & ~BIT(2), 2705 .mode = 0444, 2706 }, 2707 { 2708 .label = "reset_sw_reset", 2709 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2710 .mask = GENMASK(7, 0) & ~BIT(3), 2711 .mode = 0444, 2712 }, 2713 { 2714 .label = "reset_main_pwr_fail", 2715 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2716 .mask = GENMASK(7, 0) & ~BIT(4), 2717 .mode = 0444, 2718 }, 2719 { 2720 .label = "reset_asic_thermal", 2721 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2722 .mask = GENMASK(7, 0) & ~BIT(5), 2723 .mode = 0444, 2724 }, 2725 { 2726 .label = "reset_hotswap_or_halt", 2727 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2728 .mask = GENMASK(7, 0) & ~BIT(6), 2729 .mode = 0444, 2730 }, 2731 { 2732 .label = "reset_sff_wd", 2733 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2734 .mask = GENMASK(7, 0) & ~BIT(6), 2735 .mode = 0444, 2736 }, 2737 { 2738 .label = "psu1_on", 2739 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2740 .mask = GENMASK(7, 0) & ~BIT(0), 2741 .mode = 0200, 2742 }, 2743 { 2744 .label = "psu2_on", 2745 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2746 .mask = GENMASK(7, 0) & ~BIT(1), 2747 .mode = 0200, 2748 }, 2749 { 2750 .label = "pwr_cycle", 2751 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2752 .mask = GENMASK(7, 0) & ~BIT(2), 2753 .mode = 0200, 2754 }, 2755 { 2756 .label = "pwr_down", 2757 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2758 .mask = GENMASK(7, 0) & ~BIT(3), 2759 .mode = 0200, 2760 }, 2761 { 2762 .label = "select_iio", 2763 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 2764 .mask = GENMASK(7, 0) & ~BIT(6), 2765 .mode = 0644, 2766 }, 2767 { 2768 .label = "asic_health", 2769 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2770 .mask = MLXPLAT_CPLD_ASIC_MASK, 2771 .bit = 1, 2772 .mode = 0444, 2773 }, 2774 }; 2775 2776 static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = { 2777 .data = mlxplat_mlxcpld_msn21xx_regs_io_data, 2778 .counter = ARRAY_SIZE(mlxplat_mlxcpld_msn21xx_regs_io_data), 2779 }; 2780 2781 /* Platform register access for next generation systems families data */ 2782 static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { 2783 { 2784 .label = "cpld1_version", 2785 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 2786 .bit = GENMASK(7, 0), 2787 .mode = 0444, 2788 }, 2789 { 2790 .label = "cpld2_version", 2791 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 2792 .bit = GENMASK(7, 0), 2793 .mode = 0444, 2794 }, 2795 { 2796 .label = "cpld3_version", 2797 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 2798 .bit = GENMASK(7, 0), 2799 .mode = 0444, 2800 }, 2801 { 2802 .label = "cpld4_version", 2803 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 2804 .bit = GENMASK(7, 0), 2805 .mode = 0444, 2806 }, 2807 { 2808 .label = "cpld1_pn", 2809 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 2810 .bit = GENMASK(15, 0), 2811 .mode = 0444, 2812 .regnum = 2, 2813 }, 2814 { 2815 .label = "cpld2_pn", 2816 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 2817 .bit = GENMASK(15, 0), 2818 .mode = 0444, 2819 .regnum = 2, 2820 }, 2821 { 2822 .label = "cpld3_pn", 2823 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 2824 .bit = GENMASK(15, 0), 2825 .mode = 0444, 2826 .regnum = 2, 2827 }, 2828 { 2829 .label = "cpld4_pn", 2830 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 2831 .bit = GENMASK(15, 0), 2832 .mode = 0444, 2833 .regnum = 2, 2834 }, 2835 { 2836 .label = "cpld1_version_min", 2837 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 2838 .bit = GENMASK(7, 0), 2839 .mode = 0444, 2840 }, 2841 { 2842 .label = "cpld2_version_min", 2843 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 2844 .bit = GENMASK(7, 0), 2845 .mode = 0444, 2846 }, 2847 { 2848 .label = "cpld3_version_min", 2849 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 2850 .bit = GENMASK(7, 0), 2851 .mode = 0444, 2852 }, 2853 { 2854 .label = "cpld4_version_min", 2855 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 2856 .bit = GENMASK(7, 0), 2857 .mode = 0444, 2858 }, 2859 { 2860 .label = "reset_long_pb", 2861 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2862 .mask = GENMASK(7, 0) & ~BIT(0), 2863 .mode = 0444, 2864 }, 2865 { 2866 .label = "reset_short_pb", 2867 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2868 .mask = GENMASK(7, 0) & ~BIT(1), 2869 .mode = 0444, 2870 }, 2871 { 2872 .label = "reset_aux_pwr_or_ref", 2873 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2874 .mask = GENMASK(7, 0) & ~BIT(2), 2875 .mode = 0444, 2876 }, 2877 { 2878 .label = "reset_from_comex", 2879 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2880 .mask = GENMASK(7, 0) & ~BIT(4), 2881 .mode = 0444, 2882 }, 2883 { 2884 .label = "reset_from_asic", 2885 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2886 .mask = GENMASK(7, 0) & ~BIT(5), 2887 .mode = 0444, 2888 }, 2889 { 2890 .label = "reset_swb_wd", 2891 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2892 .mask = GENMASK(7, 0) & ~BIT(6), 2893 .mode = 0444, 2894 }, 2895 { 2896 .label = "reset_asic_thermal", 2897 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 2898 .mask = GENMASK(7, 0) & ~BIT(7), 2899 .mode = 0444, 2900 }, 2901 { 2902 .label = "reset_comex_pwr_fail", 2903 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2904 .mask = GENMASK(7, 0) & ~BIT(3), 2905 .mode = 0444, 2906 }, 2907 { 2908 .label = "reset_platform", 2909 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2910 .mask = GENMASK(7, 0) & ~BIT(4), 2911 .mode = 0444, 2912 }, 2913 { 2914 .label = "reset_soc", 2915 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2916 .mask = GENMASK(7, 0) & ~BIT(5), 2917 .mode = 0444, 2918 }, 2919 { 2920 .label = "reset_comex_wd", 2921 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 2922 .mask = GENMASK(7, 0) & ~BIT(6), 2923 .mode = 0444, 2924 }, 2925 { 2926 .label = "reset_voltmon_upgrade_fail", 2927 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2928 .mask = GENMASK(7, 0) & ~BIT(0), 2929 .mode = 0444, 2930 }, 2931 { 2932 .label = "reset_system", 2933 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2934 .mask = GENMASK(7, 0) & ~BIT(1), 2935 .mode = 0444, 2936 }, 2937 { 2938 .label = "reset_sw_pwr_off", 2939 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2940 .mask = GENMASK(7, 0) & ~BIT(2), 2941 .mode = 0444, 2942 }, 2943 { 2944 .label = "reset_comex_thermal", 2945 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2946 .mask = GENMASK(7, 0) & ~BIT(3), 2947 .mode = 0444, 2948 }, 2949 { 2950 .label = "reset_reload_bios", 2951 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2952 .mask = GENMASK(7, 0) & ~BIT(5), 2953 .mode = 0444, 2954 }, 2955 { 2956 .label = "reset_ac_pwr_fail", 2957 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 2958 .mask = GENMASK(7, 0) & ~BIT(6), 2959 .mode = 0444, 2960 }, 2961 { 2962 .label = "psu1_on", 2963 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2964 .mask = GENMASK(7, 0) & ~BIT(0), 2965 .mode = 0200, 2966 }, 2967 { 2968 .label = "psu2_on", 2969 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2970 .mask = GENMASK(7, 0) & ~BIT(1), 2971 .mode = 0200, 2972 }, 2973 { 2974 .label = "pwr_cycle", 2975 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2976 .mask = GENMASK(7, 0) & ~BIT(2), 2977 .mode = 0200, 2978 }, 2979 { 2980 .label = "pwr_down", 2981 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 2982 .mask = GENMASK(7, 0) & ~BIT(3), 2983 .mode = 0200, 2984 }, 2985 { 2986 .label = "jtag_enable", 2987 .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 2988 .mask = GENMASK(7, 0) & ~BIT(4), 2989 .mode = 0644, 2990 }, 2991 { 2992 .label = "asic_health", 2993 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 2994 .mask = MLXPLAT_CPLD_ASIC_MASK, 2995 .bit = 1, 2996 .mode = 0444, 2997 }, 2998 { 2999 .label = "fan_dir", 3000 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3001 .bit = GENMASK(7, 0), 3002 .mode = 0444, 3003 }, 3004 { 3005 .label = "bios_safe_mode", 3006 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3007 .mask = GENMASK(7, 0) & ~BIT(4), 3008 .mode = 0444, 3009 }, 3010 { 3011 .label = "bios_active_image", 3012 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3013 .mask = GENMASK(7, 0) & ~BIT(5), 3014 .mode = 0444, 3015 }, 3016 { 3017 .label = "bios_auth_fail", 3018 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3019 .mask = GENMASK(7, 0) & ~BIT(6), 3020 .mode = 0444, 3021 }, 3022 { 3023 .label = "bios_upgrade_fail", 3024 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3025 .mask = GENMASK(7, 0) & ~BIT(7), 3026 .mode = 0444, 3027 }, 3028 { 3029 .label = "voltreg_update_status", 3030 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3031 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3032 .bit = 5, 3033 .mode = 0444, 3034 }, 3035 { 3036 .label = "vpd_wp", 3037 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3038 .mask = GENMASK(7, 0) & ~BIT(3), 3039 .mode = 0644, 3040 }, 3041 { 3042 .label = "pcie_asic_reset_dis", 3043 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3044 .mask = GENMASK(7, 0) & ~BIT(4), 3045 .mode = 0644, 3046 }, 3047 { 3048 .label = "config1", 3049 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3050 .bit = GENMASK(7, 0), 3051 .mode = 0444, 3052 }, 3053 { 3054 .label = "config2", 3055 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3056 .bit = GENMASK(7, 0), 3057 .mode = 0444, 3058 }, 3059 { 3060 .label = "ufm_version", 3061 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3062 .bit = GENMASK(7, 0), 3063 .mode = 0444, 3064 }, 3065 }; 3066 3067 static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = { 3068 .data = mlxplat_mlxcpld_default_ng_regs_io_data, 3069 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_regs_io_data), 3070 }; 3071 3072 /* Platform register access for modular systems families data */ 3073 static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = { 3074 { 3075 .label = "cpld1_version", 3076 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET, 3077 .bit = GENMASK(7, 0), 3078 .mode = 0444, 3079 }, 3080 { 3081 .label = "cpld2_version", 3082 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET, 3083 .bit = GENMASK(7, 0), 3084 .mode = 0444, 3085 }, 3086 { 3087 .label = "cpld3_version", 3088 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET, 3089 .bit = GENMASK(7, 0), 3090 .mode = 0444, 3091 }, 3092 { 3093 .label = "cpld4_version", 3094 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET, 3095 .bit = GENMASK(7, 0), 3096 .mode = 0444, 3097 }, 3098 { 3099 .label = "cpld1_pn", 3100 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, 3101 .bit = GENMASK(15, 0), 3102 .mode = 0444, 3103 .regnum = 2, 3104 }, 3105 { 3106 .label = "cpld2_pn", 3107 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET, 3108 .bit = GENMASK(15, 0), 3109 .mode = 0444, 3110 .regnum = 2, 3111 }, 3112 { 3113 .label = "cpld3_pn", 3114 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET, 3115 .bit = GENMASK(15, 0), 3116 .mode = 0444, 3117 .regnum = 2, 3118 }, 3119 { 3120 .label = "cpld4_pn", 3121 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET, 3122 .bit = GENMASK(15, 0), 3123 .mode = 0444, 3124 .regnum = 2, 3125 }, 3126 { 3127 .label = "cpld1_version_min", 3128 .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, 3129 .bit = GENMASK(7, 0), 3130 .mode = 0444, 3131 }, 3132 { 3133 .label = "cpld2_version_min", 3134 .reg = MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET, 3135 .bit = GENMASK(7, 0), 3136 .mode = 0444, 3137 }, 3138 { 3139 .label = "cpld3_version_min", 3140 .reg = MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET, 3141 .bit = GENMASK(7, 0), 3142 .mode = 0444, 3143 }, 3144 { 3145 .label = "cpld4_version_min", 3146 .reg = MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET, 3147 .bit = GENMASK(7, 0), 3148 .mode = 0444, 3149 }, 3150 { 3151 .label = "lc1_enable", 3152 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3153 .mask = GENMASK(7, 0) & ~BIT(0), 3154 .mode = 0644, 3155 }, 3156 { 3157 .label = "lc2_enable", 3158 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3159 .mask = GENMASK(7, 0) & ~BIT(1), 3160 .mode = 0644, 3161 }, 3162 { 3163 .label = "lc3_enable", 3164 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3165 .mask = GENMASK(7, 0) & ~BIT(2), 3166 .mode = 0644, 3167 }, 3168 { 3169 .label = "lc4_enable", 3170 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3171 .mask = GENMASK(7, 0) & ~BIT(3), 3172 .mode = 0644, 3173 }, 3174 { 3175 .label = "lc5_enable", 3176 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3177 .mask = GENMASK(7, 0) & ~BIT(4), 3178 .mode = 0644, 3179 }, 3180 { 3181 .label = "lc6_enable", 3182 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3183 .mask = GENMASK(7, 0) & ~BIT(5), 3184 .mode = 0644, 3185 }, 3186 { 3187 .label = "lc7_enable", 3188 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3189 .mask = GENMASK(7, 0) & ~BIT(6), 3190 .mode = 0644, 3191 }, 3192 { 3193 .label = "lc8_enable", 3194 .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET, 3195 .mask = GENMASK(7, 0) & ~BIT(7), 3196 .mode = 0644, 3197 }, 3198 { 3199 .label = "reset_long_pb", 3200 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3201 .mask = GENMASK(7, 0) & ~BIT(0), 3202 .mode = 0444, 3203 }, 3204 { 3205 .label = "reset_short_pb", 3206 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3207 .mask = GENMASK(7, 0) & ~BIT(1), 3208 .mode = 0444, 3209 }, 3210 { 3211 .label = "reset_aux_pwr_or_fu", 3212 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3213 .mask = GENMASK(7, 0) & ~BIT(2), 3214 .mode = 0444, 3215 }, 3216 { 3217 .label = "reset_mgmt_dc_dc_pwr_fail", 3218 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3219 .mask = GENMASK(7, 0) & ~BIT(3), 3220 .mode = 0444, 3221 }, 3222 { 3223 .label = "reset_sys_comex_bios", 3224 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3225 .mask = GENMASK(7, 0) & ~BIT(5), 3226 .mode = 0444, 3227 }, 3228 { 3229 .label = "reset_sw_reset", 3230 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3231 .mask = GENMASK(7, 0) & ~BIT(0), 3232 .mode = 0444, 3233 }, 3234 { 3235 .label = "reset_aux_pwr_or_reload", 3236 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3237 .mask = GENMASK(7, 0) & ~BIT(2), 3238 .mode = 0444, 3239 }, 3240 { 3241 .label = "reset_comex_pwr_fail", 3242 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3243 .mask = GENMASK(7, 0) & ~BIT(3), 3244 .mode = 0444, 3245 }, 3246 { 3247 .label = "reset_platform", 3248 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3249 .mask = GENMASK(7, 0) & ~BIT(4), 3250 .mode = 0444, 3251 }, 3252 { 3253 .label = "reset_soc", 3254 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3255 .mask = GENMASK(7, 0) & ~BIT(5), 3256 .mode = 0444, 3257 }, 3258 { 3259 .label = "reset_pwr_off_from_carrier", 3260 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, 3261 .mask = GENMASK(7, 0) & ~BIT(7), 3262 .mode = 0444, 3263 }, 3264 { 3265 .label = "reset_swb_wd", 3266 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3267 .mask = GENMASK(7, 0) & ~BIT(0), 3268 .mode = 0444, 3269 }, 3270 { 3271 .label = "reset_swb_aux_pwr_or_fu", 3272 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3273 .mask = GENMASK(7, 0) & ~BIT(2), 3274 .mode = 0444, 3275 }, 3276 { 3277 .label = "reset_swb_dc_dc_pwr_fail", 3278 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3279 .mask = GENMASK(7, 0) & ~BIT(3), 3280 .mode = 0444, 3281 }, 3282 { 3283 .label = "reset_swb_12v_fail", 3284 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3285 .mask = GENMASK(7, 0) & ~BIT(4), 3286 .mode = 0444, 3287 }, 3288 { 3289 .label = "reset_system", 3290 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3291 .mask = GENMASK(7, 0) & ~BIT(5), 3292 .mode = 0444, 3293 }, 3294 { 3295 .label = "reset_thermal_spc_or_pciesw", 3296 .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, 3297 .mask = GENMASK(7, 0) & ~BIT(7), 3298 .mode = 0444, 3299 }, 3300 { 3301 .label = "bios_safe_mode", 3302 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3303 .mask = GENMASK(7, 0) & ~BIT(4), 3304 .mode = 0444, 3305 }, 3306 { 3307 .label = "bios_active_image", 3308 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3309 .mask = GENMASK(7, 0) & ~BIT(5), 3310 .mode = 0444, 3311 }, 3312 { 3313 .label = "bios_auth_fail", 3314 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3315 .mask = GENMASK(7, 0) & ~BIT(6), 3316 .mode = 0444, 3317 }, 3318 { 3319 .label = "bios_upgrade_fail", 3320 .reg = MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET, 3321 .mask = GENMASK(7, 0) & ~BIT(7), 3322 .mode = 0444, 3323 }, 3324 { 3325 .label = "voltreg_update_status", 3326 .reg = MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET, 3327 .mask = MLXPLAT_CPLD_VOLTREG_UPD_MASK, 3328 .bit = 5, 3329 .mode = 0444, 3330 }, 3331 { 3332 .label = "vpd_wp", 3333 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3334 .mask = GENMASK(7, 0) & ~BIT(3), 3335 .mode = 0644, 3336 }, 3337 { 3338 .label = "pcie_asic_reset_dis", 3339 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3340 .mask = GENMASK(7, 0) & ~BIT(4), 3341 .mode = 0644, 3342 }, 3343 { 3344 .label = "shutdown_unlock", 3345 .reg = MLXPLAT_CPLD_LPC_REG_GP0_OFFSET, 3346 .mask = GENMASK(7, 0) & ~BIT(5), 3347 .mode = 0644, 3348 }, 3349 { 3350 .label = "lc1_rst_mask", 3351 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3352 .mask = GENMASK(7, 0) & ~BIT(0), 3353 .mode = 0200, 3354 }, 3355 { 3356 .label = "lc2_rst_mask", 3357 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3358 .mask = GENMASK(7, 0) & ~BIT(1), 3359 .mode = 0200, 3360 }, 3361 { 3362 .label = "lc3_rst_mask", 3363 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3364 .mask = GENMASK(7, 0) & ~BIT(2), 3365 .mode = 0200, 3366 }, 3367 { 3368 .label = "lc4_rst_mask", 3369 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3370 .mask = GENMASK(7, 0) & ~BIT(3), 3371 .mode = 0200, 3372 }, 3373 { 3374 .label = "lc5_rst_mask", 3375 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3376 .mask = GENMASK(7, 0) & ~BIT(4), 3377 .mode = 0200, 3378 }, 3379 { 3380 .label = "lc6_rst_mask", 3381 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3382 .mask = GENMASK(7, 0) & ~BIT(5), 3383 .mode = 0200, 3384 }, 3385 { 3386 .label = "lc7_rst_mask", 3387 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3388 .mask = GENMASK(7, 0) & ~BIT(6), 3389 .mode = 0200, 3390 }, 3391 { 3392 .label = "lc8_rst_mask", 3393 .reg = MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET, 3394 .mask = GENMASK(7, 0) & ~BIT(7), 3395 .mode = 0200, 3396 }, 3397 { 3398 .label = "psu1_on", 3399 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3400 .mask = GENMASK(7, 0) & ~BIT(0), 3401 .mode = 0200, 3402 }, 3403 { 3404 .label = "psu2_on", 3405 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3406 .mask = GENMASK(7, 0) & ~BIT(1), 3407 .mode = 0200, 3408 }, 3409 { 3410 .label = "pwr_cycle", 3411 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3412 .mask = GENMASK(7, 0) & ~BIT(2), 3413 .mode = 0200, 3414 }, 3415 { 3416 .label = "pwr_down", 3417 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3418 .mask = GENMASK(7, 0) & ~BIT(3), 3419 .mode = 0200, 3420 }, 3421 { 3422 .label = "psu3_on", 3423 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3424 .mask = GENMASK(7, 0) & ~BIT(4), 3425 .mode = 0200, 3426 }, 3427 { 3428 .label = "psu4_on", 3429 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3430 .mask = GENMASK(7, 0) & ~BIT(5), 3431 .mode = 0200, 3432 }, 3433 { 3434 .label = "auto_power_mode", 3435 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3436 .mask = GENMASK(7, 0) & ~BIT(6), 3437 .mode = 0644, 3438 }, 3439 { 3440 .label = "pm_mgmt_en", 3441 .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, 3442 .mask = GENMASK(7, 0) & ~BIT(7), 3443 .mode = 0644, 3444 }, 3445 { 3446 .label = "jtag_enable", 3447 .reg = MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE, 3448 .mask = GENMASK(3, 0), 3449 .bit = 1, 3450 .mode = 0644, 3451 }, 3452 { 3453 .label = "safe_bios_dis", 3454 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET, 3455 .mask = GENMASK(7, 0) & ~BIT(5), 3456 .mode = 0644, 3457 }, 3458 { 3459 .label = "safe_bios_dis_wp", 3460 .reg = MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET, 3461 .mask = GENMASK(7, 0) & ~BIT(5), 3462 .mode = 0644, 3463 }, 3464 { 3465 .label = "asic_health", 3466 .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, 3467 .mask = MLXPLAT_CPLD_ASIC_MASK, 3468 .bit = 1, 3469 .mode = 0444, 3470 }, 3471 { 3472 .label = "fan_dir", 3473 .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, 3474 .bit = GENMASK(7, 0), 3475 .mode = 0444, 3476 }, 3477 { 3478 .label = "lc1_pwr", 3479 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3480 .mask = GENMASK(7, 0) & ~BIT(0), 3481 .mode = 0644, 3482 }, 3483 { 3484 .label = "lc2_pwr", 3485 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3486 .mask = GENMASK(7, 0) & ~BIT(1), 3487 .mode = 0644, 3488 }, 3489 { 3490 .label = "lc3_pwr", 3491 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3492 .mask = GENMASK(7, 0) & ~BIT(2), 3493 .mode = 0644, 3494 }, 3495 { 3496 .label = "lc4_pwr", 3497 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3498 .mask = GENMASK(7, 0) & ~BIT(3), 3499 .mode = 0644, 3500 }, 3501 { 3502 .label = "lc5_pwr", 3503 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3504 .mask = GENMASK(7, 0) & ~BIT(4), 3505 .mode = 0644, 3506 }, 3507 { 3508 .label = "lc6_pwr", 3509 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3510 .mask = GENMASK(7, 0) & ~BIT(5), 3511 .mode = 0644, 3512 }, 3513 { 3514 .label = "lc7_pwr", 3515 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3516 .mask = GENMASK(7, 0) & ~BIT(6), 3517 .mode = 0644, 3518 }, 3519 { 3520 .label = "lc8_pwr", 3521 .reg = MLXPLAT_CPLD_LPC_REG_LC_PWR_ON, 3522 .mask = GENMASK(7, 0) & ~BIT(7), 3523 .mode = 0644, 3524 }, 3525 { 3526 .label = "config1", 3527 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET, 3528 .bit = GENMASK(7, 0), 3529 .mode = 0444, 3530 }, 3531 { 3532 .label = "config2", 3533 .reg = MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET, 3534 .bit = GENMASK(7, 0), 3535 .mode = 0444, 3536 }, 3537 { 3538 .label = "ufm_version", 3539 .reg = MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET, 3540 .bit = GENMASK(7, 0), 3541 .mode = 0444, 3542 }, 3543 }; 3544 3545 static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = { 3546 .data = mlxplat_mlxcpld_modular_regs_io_data, 3547 .counter = ARRAY_SIZE(mlxplat_mlxcpld_modular_regs_io_data), 3548 }; 3549 3550 /* Platform FAN default */ 3551 static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = { 3552 { 3553 .label = "pwm1", 3554 .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, 3555 }, 3556 { 3557 .label = "pwm2", 3558 .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 3559 }, 3560 { 3561 .label = "pwm3", 3562 .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 3563 }, 3564 { 3565 .label = "pwm4", 3566 .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 3567 }, 3568 { 3569 .label = "tacho1", 3570 .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, 3571 .mask = GENMASK(7, 0), 3572 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3573 .bit = BIT(0), 3574 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3575 3576 }, 3577 { 3578 .label = "tacho2", 3579 .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, 3580 .mask = GENMASK(7, 0), 3581 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3582 .bit = BIT(1), 3583 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3584 }, 3585 { 3586 .label = "tacho3", 3587 .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, 3588 .mask = GENMASK(7, 0), 3589 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3590 .bit = BIT(2), 3591 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3592 }, 3593 { 3594 .label = "tacho4", 3595 .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, 3596 .mask = GENMASK(7, 0), 3597 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3598 .bit = BIT(3), 3599 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3600 }, 3601 { 3602 .label = "tacho5", 3603 .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, 3604 .mask = GENMASK(7, 0), 3605 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3606 .bit = BIT(4), 3607 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3608 }, 3609 { 3610 .label = "tacho6", 3611 .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, 3612 .mask = GENMASK(7, 0), 3613 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3614 .bit = BIT(5), 3615 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3616 }, 3617 { 3618 .label = "tacho7", 3619 .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, 3620 .mask = GENMASK(7, 0), 3621 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3622 .bit = BIT(6), 3623 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3624 }, 3625 { 3626 .label = "tacho8", 3627 .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, 3628 .mask = GENMASK(7, 0), 3629 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, 3630 .bit = BIT(7), 3631 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3632 }, 3633 { 3634 .label = "tacho9", 3635 .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, 3636 .mask = GENMASK(7, 0), 3637 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3638 .bit = BIT(0), 3639 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3640 }, 3641 { 3642 .label = "tacho10", 3643 .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, 3644 .mask = GENMASK(7, 0), 3645 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3646 .bit = BIT(1), 3647 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3648 }, 3649 { 3650 .label = "tacho11", 3651 .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, 3652 .mask = GENMASK(7, 0), 3653 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3654 .bit = BIT(2), 3655 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3656 }, 3657 { 3658 .label = "tacho12", 3659 .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, 3660 .mask = GENMASK(7, 0), 3661 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3662 .bit = BIT(3), 3663 .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, 3664 }, 3665 { 3666 .label = "tacho13", 3667 .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, 3668 .mask = GENMASK(7, 0), 3669 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3670 .bit = BIT(4), 3671 }, 3672 { 3673 .label = "tacho14", 3674 .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, 3675 .mask = GENMASK(7, 0), 3676 .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET, 3677 .bit = BIT(5), 3678 }, 3679 { 3680 .label = "conf", 3681 .capability = MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET, 3682 }, 3683 }; 3684 3685 static struct mlxreg_core_platform_data mlxplat_default_fan_data = { 3686 .data = mlxplat_mlxcpld_default_fan_data, 3687 .counter = ARRAY_SIZE(mlxplat_mlxcpld_default_fan_data), 3688 .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, 3689 }; 3690 3691 /* Watchdog type1: hardware implementation version1 3692 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). 3693 */ 3694 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = { 3695 { 3696 .label = "action", 3697 .reg = MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 3698 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 3699 .bit = 0, 3700 }, 3701 { 3702 .label = "timeout", 3703 .reg = MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET, 3704 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 3705 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 3706 }, 3707 { 3708 .label = "ping", 3709 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 3710 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 3711 .bit = 0, 3712 }, 3713 { 3714 .label = "reset", 3715 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3716 .mask = GENMASK(7, 0) & ~BIT(6), 3717 .bit = 6, 3718 }, 3719 }; 3720 3721 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = { 3722 { 3723 .label = "action", 3724 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 3725 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 3726 .bit = 4, 3727 }, 3728 { 3729 .label = "timeout", 3730 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 3731 .mask = MLXPLAT_CPLD_WD_TYPE1_TO_MASK, 3732 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 3733 }, 3734 { 3735 .label = "ping", 3736 .reg = MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET, 3737 .mask = MLXPLAT_CPLD_WD1_CLEAR_MASK, 3738 .bit = 1, 3739 }, 3740 }; 3741 3742 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = { 3743 { 3744 .data = mlxplat_mlxcpld_wd_main_regs_type1, 3745 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type1), 3746 .version = MLX_WDT_TYPE1, 3747 .identity = "mlx-wdt-main", 3748 }, 3749 { 3750 .data = mlxplat_mlxcpld_wd_aux_regs_type1, 3751 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type1), 3752 .version = MLX_WDT_TYPE1, 3753 .identity = "mlx-wdt-aux", 3754 }, 3755 }; 3756 3757 /* Watchdog type2: hardware implementation version 2 3758 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). 3759 */ 3760 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = { 3761 { 3762 .label = "action", 3763 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 3764 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 3765 .bit = 0, 3766 }, 3767 { 3768 .label = "timeout", 3769 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 3770 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3771 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 3772 }, 3773 { 3774 .label = "timeleft", 3775 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET, 3776 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3777 }, 3778 { 3779 .label = "ping", 3780 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 3781 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 3782 .bit = 0, 3783 }, 3784 { 3785 .label = "reset", 3786 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3787 .mask = GENMASK(7, 0) & ~BIT(6), 3788 .bit = 6, 3789 }, 3790 }; 3791 3792 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = { 3793 { 3794 .label = "action", 3795 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 3796 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 3797 .bit = 4, 3798 }, 3799 { 3800 .label = "timeout", 3801 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 3802 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3803 .health_cntr = MLXPLAT_CPLD_WD_DFLT_TIMEOUT, 3804 }, 3805 { 3806 .label = "timeleft", 3807 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET, 3808 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3809 }, 3810 { 3811 .label = "ping", 3812 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 3813 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 3814 .bit = 4, 3815 }, 3816 }; 3817 3818 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = { 3819 { 3820 .data = mlxplat_mlxcpld_wd_main_regs_type2, 3821 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type2), 3822 .version = MLX_WDT_TYPE2, 3823 .identity = "mlx-wdt-main", 3824 }, 3825 { 3826 .data = mlxplat_mlxcpld_wd_aux_regs_type2, 3827 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type2), 3828 .version = MLX_WDT_TYPE2, 3829 .identity = "mlx-wdt-aux", 3830 }, 3831 }; 3832 3833 /* Watchdog type3: hardware implementation version 3 3834 * Can be on all systems. It's differentiated by WD capability bit. 3835 * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) 3836 * still have only one main watchdog. 3837 */ 3838 static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = { 3839 { 3840 .label = "action", 3841 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 3842 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 3843 .bit = 0, 3844 }, 3845 { 3846 .label = "timeout", 3847 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 3848 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3849 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 3850 }, 3851 { 3852 .label = "timeleft", 3853 .reg = MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET, 3854 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3855 }, 3856 { 3857 .label = "ping", 3858 .reg = MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 3859 .mask = MLXPLAT_CPLD_WD_RESET_ACT_MASK, 3860 .bit = 0, 3861 }, 3862 { 3863 .label = "reset", 3864 .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, 3865 .mask = GENMASK(7, 0) & ~BIT(6), 3866 .bit = 6, 3867 }, 3868 }; 3869 3870 static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = { 3871 { 3872 .label = "action", 3873 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 3874 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 3875 .bit = 4, 3876 }, 3877 { 3878 .label = "timeout", 3879 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 3880 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3881 .health_cntr = MLXPLAT_CPLD_WD3_DFLT_TIMEOUT, 3882 }, 3883 { 3884 .label = "timeleft", 3885 .reg = MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET, 3886 .mask = MLXPLAT_CPLD_WD_TYPE2_TO_MASK, 3887 }, 3888 { 3889 .label = "ping", 3890 .reg = MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 3891 .mask = MLXPLAT_CPLD_WD_FAN_ACT_MASK, 3892 .bit = 4, 3893 }, 3894 }; 3895 3896 static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = { 3897 { 3898 .data = mlxplat_mlxcpld_wd_main_regs_type3, 3899 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_main_regs_type3), 3900 .version = MLX_WDT_TYPE3, 3901 .identity = "mlx-wdt-main", 3902 }, 3903 { 3904 .data = mlxplat_mlxcpld_wd_aux_regs_type3, 3905 .counter = ARRAY_SIZE(mlxplat_mlxcpld_wd_aux_regs_type3), 3906 .version = MLX_WDT_TYPE3, 3907 .identity = "mlx-wdt-aux", 3908 }, 3909 }; 3910 3911 static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) 3912 { 3913 switch (reg) { 3914 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 3915 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 3916 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 3917 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 3918 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 3919 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 3920 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 3921 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 3922 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 3923 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 3924 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 3925 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 3926 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 3927 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 3928 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 3929 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 3930 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 3931 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 3932 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 3933 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 3934 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 3935 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 3936 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 3937 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 3938 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 3939 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 3940 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 3941 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 3942 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 3943 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 3944 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 3945 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 3946 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 3947 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 3948 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 3949 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 3950 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 3951 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 3952 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 3953 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 3954 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 3955 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 3956 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 3957 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 3958 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 3959 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 3960 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 3961 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 3962 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 3963 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 3964 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 3965 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 3966 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 3967 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 3968 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 3969 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 3970 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 3971 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 3972 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 3973 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 3974 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 3975 return true; 3976 } 3977 return false; 3978 } 3979 3980 static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) 3981 { 3982 switch (reg) { 3983 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 3984 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 3985 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 3986 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 3987 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 3988 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 3989 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 3990 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 3991 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 3992 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 3993 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 3994 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 3995 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 3996 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 3997 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 3998 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 3999 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4000 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4001 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4002 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4003 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4004 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4005 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4006 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 4007 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 4008 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 4009 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4010 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4011 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4012 case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET: 4013 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4014 case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET: 4015 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4016 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4017 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4018 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 4019 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4020 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 4021 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4022 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 4023 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4024 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 4025 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4026 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 4027 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4028 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4029 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 4030 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4031 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4032 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 4033 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4034 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4035 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 4036 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4037 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4038 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 4039 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4040 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 4041 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4042 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4043 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 4044 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4045 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4046 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4047 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4048 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4049 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 4050 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4051 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4052 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 4053 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4054 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4055 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 4056 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4057 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4058 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 4059 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4060 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4061 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4062 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET: 4063 case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET: 4064 case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET: 4065 case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET: 4066 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4067 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4068 case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET: 4069 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4070 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4071 case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: 4072 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 4073 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 4074 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 4075 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 4076 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4077 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4078 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4079 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4080 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 4081 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 4082 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 4083 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 4084 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 4085 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 4086 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 4087 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 4088 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 4089 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 4090 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 4091 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 4092 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 4093 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 4094 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4095 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 4096 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 4097 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 4098 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 4099 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 4100 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 4101 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 4102 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 4103 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 4104 return true; 4105 } 4106 return false; 4107 } 4108 4109 static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) 4110 { 4111 switch (reg) { 4112 case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET: 4113 case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: 4114 case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: 4115 case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: 4116 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: 4117 case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: 4118 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: 4119 case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: 4120 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: 4121 case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: 4122 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: 4123 case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: 4124 case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: 4125 case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: 4126 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: 4127 case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: 4128 case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: 4129 case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: 4130 case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: 4131 case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: 4132 case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: 4133 case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: 4134 case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: 4135 case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: 4136 case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: 4137 case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: 4138 case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: 4139 case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: 4140 case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: 4141 case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET: 4142 case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE: 4143 case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: 4144 case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: 4145 case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: 4146 case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: 4147 case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: 4148 case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: 4149 case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: 4150 case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: 4151 case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET: 4152 case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: 4153 case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: 4154 case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: 4155 case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: 4156 case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: 4157 case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: 4158 case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: 4159 case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET: 4160 case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: 4161 case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: 4162 case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: 4163 case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: 4164 case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: 4165 case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: 4166 case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: 4167 case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: 4168 case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: 4169 case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: 4170 case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET: 4171 case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET: 4172 case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET: 4173 case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET: 4174 case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET: 4175 case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET: 4176 case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET: 4177 case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET: 4178 case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET: 4179 case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET: 4180 case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET: 4181 case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET: 4182 case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET: 4183 case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET: 4184 case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET: 4185 case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET: 4186 case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET: 4187 case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET: 4188 case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON: 4189 case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET: 4190 case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: 4191 case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: 4192 case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: 4193 case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: 4194 case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: 4195 case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: 4196 case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: 4197 case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: 4198 case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: 4199 case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: 4200 case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: 4201 case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET: 4202 case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET: 4203 case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET: 4204 case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET: 4205 case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET: 4206 case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET: 4207 case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET: 4208 case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET: 4209 case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET: 4210 case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET: 4211 case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET: 4212 case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: 4213 case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: 4214 case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: 4215 case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: 4216 case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: 4217 case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: 4218 case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET: 4219 case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET: 4220 case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET: 4221 case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET: 4222 case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET: 4223 case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: 4224 case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: 4225 return true; 4226 } 4227 return false; 4228 } 4229 4230 static const struct reg_default mlxplat_mlxcpld_regmap_default[] = { 4231 { MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, 0x00 }, 4232 { MLXPLAT_CPLD_LPC_REG_WP2_OFFSET, 0x00 }, 4233 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4234 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 4235 }; 4236 4237 static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = { 4238 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4239 { MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET, 0x00 }, 4240 }; 4241 4242 static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = { 4243 { MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET, 4244 MLXPLAT_CPLD_LOW_AGGRCX_MASK }, 4245 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4246 }; 4247 4248 static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { 4249 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4250 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 4251 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 4252 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 4253 }; 4254 4255 static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = { 4256 { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0x61 }, 4257 { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, 4258 { MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, 0x00 }, 4259 { MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, 0x00 }, 4260 { MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, 0x00 }, 4261 { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, 4262 { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, 4263 { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, 4264 { MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET, 4265 MLXPLAT_CPLD_AGGR_MASK_LC_LOW }, 4266 }; 4267 4268 struct mlxplat_mlxcpld_regmap_context { 4269 void __iomem *base; 4270 }; 4271 4272 static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx; 4273 4274 static int 4275 mlxplat_mlxcpld_reg_read(void *context, unsigned int reg, unsigned int *val) 4276 { 4277 struct mlxplat_mlxcpld_regmap_context *ctx = context; 4278 4279 *val = ioread8(ctx->base + reg); 4280 return 0; 4281 } 4282 4283 static int 4284 mlxplat_mlxcpld_reg_write(void *context, unsigned int reg, unsigned int val) 4285 { 4286 struct mlxplat_mlxcpld_regmap_context *ctx = context; 4287 4288 iowrite8(val, ctx->base + reg); 4289 return 0; 4290 } 4291 4292 static const struct regmap_config mlxplat_mlxcpld_regmap_config = { 4293 .reg_bits = 8, 4294 .val_bits = 8, 4295 .max_register = 255, 4296 .cache_type = REGCACHE_FLAT, 4297 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4298 .readable_reg = mlxplat_mlxcpld_readable_reg, 4299 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4300 .reg_defaults = mlxplat_mlxcpld_regmap_default, 4301 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_default), 4302 .reg_read = mlxplat_mlxcpld_reg_read, 4303 .reg_write = mlxplat_mlxcpld_reg_write, 4304 }; 4305 4306 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = { 4307 .reg_bits = 8, 4308 .val_bits = 8, 4309 .max_register = 255, 4310 .cache_type = REGCACHE_FLAT, 4311 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4312 .readable_reg = mlxplat_mlxcpld_readable_reg, 4313 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4314 .reg_defaults = mlxplat_mlxcpld_regmap_ng, 4315 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng), 4316 .reg_read = mlxplat_mlxcpld_reg_read, 4317 .reg_write = mlxplat_mlxcpld_reg_write, 4318 }; 4319 4320 static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = { 4321 .reg_bits = 8, 4322 .val_bits = 8, 4323 .max_register = 255, 4324 .cache_type = REGCACHE_FLAT, 4325 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4326 .readable_reg = mlxplat_mlxcpld_readable_reg, 4327 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4328 .reg_defaults = mlxplat_mlxcpld_regmap_comex_default, 4329 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_comex_default), 4330 .reg_read = mlxplat_mlxcpld_reg_read, 4331 .reg_write = mlxplat_mlxcpld_reg_write, 4332 }; 4333 4334 static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = { 4335 .reg_bits = 8, 4336 .val_bits = 8, 4337 .max_register = 255, 4338 .cache_type = REGCACHE_FLAT, 4339 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4340 .readable_reg = mlxplat_mlxcpld_readable_reg, 4341 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4342 .reg_defaults = mlxplat_mlxcpld_regmap_ng400, 4343 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), 4344 .reg_read = mlxplat_mlxcpld_reg_read, 4345 .reg_write = mlxplat_mlxcpld_reg_write, 4346 }; 4347 4348 static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { 4349 .reg_bits = 8, 4350 .val_bits = 8, 4351 .max_register = 255, 4352 .cache_type = REGCACHE_FLAT, 4353 .writeable_reg = mlxplat_mlxcpld_writeable_reg, 4354 .readable_reg = mlxplat_mlxcpld_readable_reg, 4355 .volatile_reg = mlxplat_mlxcpld_volatile_reg, 4356 .reg_defaults = mlxplat_mlxcpld_regmap_eth_modular, 4357 .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_eth_modular), 4358 .reg_read = mlxplat_mlxcpld_reg_read, 4359 .reg_write = mlxplat_mlxcpld_reg_write, 4360 }; 4361 4362 static struct resource mlxplat_mlxcpld_resources[] = { 4363 [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), 4364 }; 4365 4366 static struct platform_device *mlxplat_dev; 4367 static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; 4368 static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; 4369 static struct mlxreg_core_platform_data *mlxplat_led; 4370 static struct mlxreg_core_platform_data *mlxplat_regs_io; 4371 static struct mlxreg_core_platform_data *mlxplat_fan; 4372 static struct mlxreg_core_platform_data 4373 *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; 4374 static const struct regmap_config *mlxplat_regmap_config; 4375 4376 static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) 4377 { 4378 int i; 4379 4380 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4381 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4382 mlxplat_mux_data = mlxplat_default_mux_data; 4383 for (i = 0; i < mlxplat_mux_num; i++) { 4384 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 4385 mlxplat_mux_data[i].n_values = 4386 ARRAY_SIZE(mlxplat_default_channels[i]); 4387 } 4388 mlxplat_hotplug = &mlxplat_mlxcpld_default_data; 4389 mlxplat_hotplug->deferred_nr = 4390 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4391 mlxplat_led = &mlxplat_default_led_data; 4392 mlxplat_regs_io = &mlxplat_default_regs_io_data; 4393 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4394 4395 return 1; 4396 } 4397 4398 static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi) 4399 { 4400 int i; 4401 4402 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4403 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4404 mlxplat_mux_data = mlxplat_default_mux_data; 4405 for (i = 0; i < mlxplat_mux_num; i++) { 4406 mlxplat_mux_data[i].values = mlxplat_default_channels[i]; 4407 mlxplat_mux_data[i].n_values = 4408 ARRAY_SIZE(mlxplat_default_channels[i]); 4409 } 4410 mlxplat_hotplug = &mlxplat_mlxcpld_default_wc_data; 4411 mlxplat_hotplug->deferred_nr = 4412 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4413 mlxplat_led = &mlxplat_default_led_wc_data; 4414 mlxplat_regs_io = &mlxplat_default_regs_io_data; 4415 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4416 4417 return 1; 4418 } 4419 4420 static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) 4421 { 4422 int i; 4423 4424 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4425 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4426 mlxplat_mux_data = mlxplat_default_mux_data; 4427 for (i = 0; i < mlxplat_mux_num; i++) { 4428 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4429 mlxplat_mux_data[i].n_values = 4430 ARRAY_SIZE(mlxplat_msn21xx_channels); 4431 } 4432 mlxplat_hotplug = &mlxplat_mlxcpld_msn21xx_data; 4433 mlxplat_hotplug->deferred_nr = 4434 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4435 mlxplat_led = &mlxplat_msn21xx_led_data; 4436 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4437 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4438 4439 return 1; 4440 } 4441 4442 static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) 4443 { 4444 int i; 4445 4446 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4447 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4448 mlxplat_mux_data = mlxplat_default_mux_data; 4449 for (i = 0; i < mlxplat_mux_num; i++) { 4450 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4451 mlxplat_mux_data[i].n_values = 4452 ARRAY_SIZE(mlxplat_msn21xx_channels); 4453 } 4454 mlxplat_hotplug = &mlxplat_mlxcpld_msn274x_data; 4455 mlxplat_hotplug->deferred_nr = 4456 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4457 mlxplat_led = &mlxplat_default_led_data; 4458 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4459 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4460 4461 return 1; 4462 } 4463 4464 static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) 4465 { 4466 int i; 4467 4468 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4469 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4470 mlxplat_mux_data = mlxplat_default_mux_data; 4471 for (i = 0; i < mlxplat_mux_num; i++) { 4472 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4473 mlxplat_mux_data[i].n_values = 4474 ARRAY_SIZE(mlxplat_msn21xx_channels); 4475 } 4476 mlxplat_hotplug = &mlxplat_mlxcpld_msn201x_data; 4477 mlxplat_hotplug->deferred_nr = 4478 mlxplat_default_channels[i - 1][MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4479 mlxplat_led = &mlxplat_msn21xx_led_data; 4480 mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; 4481 mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; 4482 4483 return 1; 4484 } 4485 4486 static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi) 4487 { 4488 int i; 4489 4490 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4491 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4492 mlxplat_mux_data = mlxplat_default_mux_data; 4493 for (i = 0; i < mlxplat_mux_num; i++) { 4494 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4495 mlxplat_mux_data[i].n_values = 4496 ARRAY_SIZE(mlxplat_msn21xx_channels); 4497 } 4498 mlxplat_hotplug = &mlxplat_mlxcpld_default_ng_data; 4499 mlxplat_hotplug->deferred_nr = 4500 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4501 mlxplat_led = &mlxplat_default_ng_led_data; 4502 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4503 mlxplat_fan = &mlxplat_default_fan_data; 4504 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4505 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4506 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4507 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng; 4508 4509 return 1; 4510 } 4511 4512 static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) 4513 { 4514 int i; 4515 4516 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 4517 mlxplat_mux_num = ARRAY_SIZE(mlxplat_extended_mux_data); 4518 mlxplat_mux_data = mlxplat_extended_mux_data; 4519 for (i = 0; i < mlxplat_mux_num; i++) { 4520 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4521 mlxplat_mux_data[i].n_values = 4522 ARRAY_SIZE(mlxplat_msn21xx_channels); 4523 } 4524 mlxplat_hotplug = &mlxplat_mlxcpld_comex_data; 4525 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM; 4526 mlxplat_led = &mlxplat_comex_100G_led_data; 4527 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4528 mlxplat_fan = &mlxplat_default_fan_data; 4529 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4530 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4531 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; 4532 4533 return 1; 4534 } 4535 4536 static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi) 4537 { 4538 int i; 4539 4540 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4541 mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_mux_data); 4542 mlxplat_mux_data = mlxplat_default_mux_data; 4543 for (i = 0; i < mlxplat_mux_num; i++) { 4544 mlxplat_mux_data[i].values = mlxplat_msn21xx_channels; 4545 mlxplat_mux_data[i].n_values = 4546 ARRAY_SIZE(mlxplat_msn21xx_channels); 4547 } 4548 mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; 4549 mlxplat_hotplug->deferred_nr = 4550 mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; 4551 mlxplat_led = &mlxplat_default_ng_led_data; 4552 mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; 4553 mlxplat_fan = &mlxplat_default_fan_data; 4554 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4555 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4556 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4557 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; 4558 4559 return 1; 4560 } 4561 4562 static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi) 4563 { 4564 int i; 4565 4566 mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; 4567 mlxplat_mux_num = ARRAY_SIZE(mlxplat_modular_mux_data); 4568 mlxplat_mux_data = mlxplat_modular_mux_data; 4569 mlxplat_hotplug = &mlxplat_mlxcpld_modular_data; 4570 mlxplat_hotplug->deferred_nr = MLXPLAT_CPLD_CH4_ETH_MODULAR; 4571 mlxplat_led = &mlxplat_modular_led_data; 4572 mlxplat_regs_io = &mlxplat_modular_regs_io_data; 4573 mlxplat_fan = &mlxplat_default_fan_data; 4574 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) 4575 mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; 4576 mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; 4577 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_eth_modular; 4578 4579 return 1; 4580 } 4581 4582 static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { 4583 { 4584 .callback = mlxplat_dmi_default_wc_matched, 4585 .matches = { 4586 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 4587 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "HI138"), 4588 }, 4589 }, 4590 { 4591 .callback = mlxplat_dmi_default_matched, 4592 .matches = { 4593 DMI_MATCH(DMI_BOARD_NAME, "VMOD0001"), 4594 }, 4595 }, 4596 { 4597 .callback = mlxplat_dmi_msn21xx_matched, 4598 .matches = { 4599 DMI_MATCH(DMI_BOARD_NAME, "VMOD0002"), 4600 }, 4601 }, 4602 { 4603 .callback = mlxplat_dmi_msn274x_matched, 4604 .matches = { 4605 DMI_MATCH(DMI_BOARD_NAME, "VMOD0003"), 4606 }, 4607 }, 4608 { 4609 .callback = mlxplat_dmi_msn201x_matched, 4610 .matches = { 4611 DMI_MATCH(DMI_BOARD_NAME, "VMOD0004"), 4612 }, 4613 }, 4614 { 4615 .callback = mlxplat_dmi_qmb7xx_matched, 4616 .matches = { 4617 DMI_MATCH(DMI_BOARD_NAME, "VMOD0005"), 4618 }, 4619 }, 4620 { 4621 .callback = mlxplat_dmi_qmb7xx_matched, 4622 .matches = { 4623 DMI_MATCH(DMI_BOARD_NAME, "VMOD0007"), 4624 }, 4625 }, 4626 { 4627 .callback = mlxplat_dmi_comex_matched, 4628 .matches = { 4629 DMI_MATCH(DMI_BOARD_NAME, "VMOD0009"), 4630 }, 4631 }, 4632 { 4633 .callback = mlxplat_dmi_ng400_matched, 4634 .matches = { 4635 DMI_MATCH(DMI_BOARD_NAME, "VMOD0010"), 4636 }, 4637 }, 4638 { 4639 .callback = mlxplat_dmi_modular_matched, 4640 .matches = { 4641 DMI_MATCH(DMI_BOARD_NAME, "VMOD0011"), 4642 }, 4643 }, 4644 { 4645 .callback = mlxplat_dmi_msn274x_matched, 4646 .matches = { 4647 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4648 DMI_MATCH(DMI_PRODUCT_NAME, "MSN274"), 4649 }, 4650 }, 4651 { 4652 .callback = mlxplat_dmi_default_matched, 4653 .matches = { 4654 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4655 DMI_MATCH(DMI_PRODUCT_NAME, "MSN24"), 4656 }, 4657 }, 4658 { 4659 .callback = mlxplat_dmi_default_matched, 4660 .matches = { 4661 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4662 DMI_MATCH(DMI_PRODUCT_NAME, "MSN27"), 4663 }, 4664 }, 4665 { 4666 .callback = mlxplat_dmi_default_matched, 4667 .matches = { 4668 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4669 DMI_MATCH(DMI_PRODUCT_NAME, "MSB"), 4670 }, 4671 }, 4672 { 4673 .callback = mlxplat_dmi_default_matched, 4674 .matches = { 4675 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4676 DMI_MATCH(DMI_PRODUCT_NAME, "MSX"), 4677 }, 4678 }, 4679 { 4680 .callback = mlxplat_dmi_msn21xx_matched, 4681 .matches = { 4682 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4683 DMI_MATCH(DMI_PRODUCT_NAME, "MSN21"), 4684 }, 4685 }, 4686 { 4687 .callback = mlxplat_dmi_msn201x_matched, 4688 .matches = { 4689 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4690 DMI_MATCH(DMI_PRODUCT_NAME, "MSN201"), 4691 }, 4692 }, 4693 { 4694 .callback = mlxplat_dmi_qmb7xx_matched, 4695 .matches = { 4696 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4697 DMI_MATCH(DMI_PRODUCT_NAME, "MQM87"), 4698 }, 4699 }, 4700 { 4701 .callback = mlxplat_dmi_qmb7xx_matched, 4702 .matches = { 4703 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4704 DMI_MATCH(DMI_PRODUCT_NAME, "MSN37"), 4705 }, 4706 }, 4707 { 4708 .callback = mlxplat_dmi_qmb7xx_matched, 4709 .matches = { 4710 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4711 DMI_MATCH(DMI_PRODUCT_NAME, "MSN34"), 4712 }, 4713 }, 4714 { 4715 .callback = mlxplat_dmi_qmb7xx_matched, 4716 .matches = { 4717 DMI_MATCH(DMI_BOARD_VENDOR, "Mellanox Technologies"), 4718 DMI_MATCH(DMI_PRODUCT_NAME, "MSN38"), 4719 }, 4720 }, 4721 { } 4722 }; 4723 4724 MODULE_DEVICE_TABLE(dmi, mlxplat_dmi_table); 4725 4726 static int mlxplat_mlxcpld_verify_bus_topology(int *nr) 4727 { 4728 struct i2c_adapter *search_adap; 4729 int shift, i; 4730 4731 /* Scan adapters from expected id to verify it is free. */ 4732 *nr = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; 4733 for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i < 4734 mlxplat_max_adap_num; i++) { 4735 search_adap = i2c_get_adapter(i); 4736 if (search_adap) { 4737 i2c_put_adapter(search_adap); 4738 continue; 4739 } 4740 4741 /* Return if expected parent adapter is free. */ 4742 if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR) 4743 return 0; 4744 break; 4745 } 4746 4747 /* Return with error if free id for adapter is not found. */ 4748 if (i == mlxplat_max_adap_num) 4749 return -ENODEV; 4750 4751 /* Shift adapter ids, since expected parent adapter is not free. */ 4752 *nr = i; 4753 for (i = 0; i < mlxplat_mux_num; i++) { 4754 shift = *nr - mlxplat_mux_data[i].parent; 4755 mlxplat_mux_data[i].parent = *nr; 4756 mlxplat_mux_data[i].base_nr += shift; 4757 if (shift > 0) 4758 mlxplat_hotplug->shift_nr = shift; 4759 } 4760 4761 return 0; 4762 } 4763 4764 static int mlxplat_mlxcpld_check_wd_capability(void *regmap) 4765 { 4766 u32 regval; 4767 int i, rc; 4768 4769 rc = regmap_read(regmap, MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, 4770 ®val); 4771 if (rc) 4772 return rc; 4773 4774 if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) { 4775 for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) { 4776 if (mlxplat_wd_data[i]) 4777 mlxplat_wd_data[i] = 4778 &mlxplat_mlxcpld_wd_set_type3[i]; 4779 } 4780 } 4781 4782 return 0; 4783 } 4784 4785 static int __init mlxplat_init(void) 4786 { 4787 struct mlxplat_priv *priv; 4788 int i, j, nr, err; 4789 4790 if (!dmi_check_system(mlxplat_dmi_table)) 4791 return -ENODEV; 4792 4793 mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, 4794 mlxplat_lpc_resources, 4795 ARRAY_SIZE(mlxplat_lpc_resources)); 4796 4797 if (IS_ERR(mlxplat_dev)) 4798 return PTR_ERR(mlxplat_dev); 4799 4800 priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), 4801 GFP_KERNEL); 4802 if (!priv) { 4803 err = -ENOMEM; 4804 goto fail_alloc; 4805 } 4806 platform_set_drvdata(mlxplat_dev, priv); 4807 4808 mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, 4809 mlxplat_lpc_resources[1].start, 1); 4810 if (!mlxplat_mlxcpld_regmap_ctx.base) { 4811 err = -ENOMEM; 4812 goto fail_alloc; 4813 } 4814 4815 if (!mlxplat_regmap_config) 4816 mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; 4817 4818 priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, 4819 &mlxplat_mlxcpld_regmap_ctx, 4820 mlxplat_regmap_config); 4821 if (IS_ERR(priv->regmap)) { 4822 err = PTR_ERR(priv->regmap); 4823 goto fail_alloc; 4824 } 4825 4826 err = mlxplat_mlxcpld_verify_bus_topology(&nr); 4827 if (nr < 0) 4828 goto fail_alloc; 4829 4830 nr = (nr == mlxplat_max_adap_num) ? -1 : nr; 4831 if (mlxplat_i2c) 4832 mlxplat_i2c->regmap = priv->regmap; 4833 priv->pdev_i2c = platform_device_register_resndata( 4834 &mlxplat_dev->dev, "i2c_mlxcpld", 4835 nr, mlxplat_mlxcpld_resources, 4836 ARRAY_SIZE(mlxplat_mlxcpld_resources), 4837 mlxplat_i2c, sizeof(*mlxplat_i2c)); 4838 if (IS_ERR(priv->pdev_i2c)) { 4839 err = PTR_ERR(priv->pdev_i2c); 4840 goto fail_alloc; 4841 } 4842 4843 for (i = 0; i < mlxplat_mux_num; i++) { 4844 priv->pdev_mux[i] = platform_device_register_resndata( 4845 &priv->pdev_i2c->dev, 4846 "i2c-mux-reg", i, NULL, 4847 0, &mlxplat_mux_data[i], 4848 sizeof(mlxplat_mux_data[i])); 4849 if (IS_ERR(priv->pdev_mux[i])) { 4850 err = PTR_ERR(priv->pdev_mux[i]); 4851 goto fail_platform_mux_register; 4852 } 4853 } 4854 4855 /* Add hotplug driver */ 4856 mlxplat_hotplug->regmap = priv->regmap; 4857 priv->pdev_hotplug = platform_device_register_resndata( 4858 &mlxplat_dev->dev, "mlxreg-hotplug", 4859 PLATFORM_DEVID_NONE, 4860 mlxplat_mlxcpld_resources, 4861 ARRAY_SIZE(mlxplat_mlxcpld_resources), 4862 mlxplat_hotplug, sizeof(*mlxplat_hotplug)); 4863 if (IS_ERR(priv->pdev_hotplug)) { 4864 err = PTR_ERR(priv->pdev_hotplug); 4865 goto fail_platform_mux_register; 4866 } 4867 4868 /* Set default registers. */ 4869 for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { 4870 err = regmap_write(priv->regmap, 4871 mlxplat_regmap_config->reg_defaults[j].reg, 4872 mlxplat_regmap_config->reg_defaults[j].def); 4873 if (err) 4874 goto fail_platform_mux_register; 4875 } 4876 4877 /* Add LED driver. */ 4878 mlxplat_led->regmap = priv->regmap; 4879 priv->pdev_led = platform_device_register_resndata( 4880 &mlxplat_dev->dev, "leds-mlxreg", 4881 PLATFORM_DEVID_NONE, NULL, 0, 4882 mlxplat_led, sizeof(*mlxplat_led)); 4883 if (IS_ERR(priv->pdev_led)) { 4884 err = PTR_ERR(priv->pdev_led); 4885 goto fail_platform_hotplug_register; 4886 } 4887 4888 /* Add registers io access driver. */ 4889 if (mlxplat_regs_io) { 4890 mlxplat_regs_io->regmap = priv->regmap; 4891 priv->pdev_io_regs = platform_device_register_resndata( 4892 &mlxplat_dev->dev, "mlxreg-io", 4893 PLATFORM_DEVID_NONE, NULL, 0, 4894 mlxplat_regs_io, 4895 sizeof(*mlxplat_regs_io)); 4896 if (IS_ERR(priv->pdev_io_regs)) { 4897 err = PTR_ERR(priv->pdev_io_regs); 4898 goto fail_platform_led_register; 4899 } 4900 } 4901 4902 /* Add FAN driver. */ 4903 if (mlxplat_fan) { 4904 mlxplat_fan->regmap = priv->regmap; 4905 priv->pdev_fan = platform_device_register_resndata( 4906 &mlxplat_dev->dev, "mlxreg-fan", 4907 PLATFORM_DEVID_NONE, NULL, 0, 4908 mlxplat_fan, 4909 sizeof(*mlxplat_fan)); 4910 if (IS_ERR(priv->pdev_fan)) { 4911 err = PTR_ERR(priv->pdev_fan); 4912 goto fail_platform_io_regs_register; 4913 } 4914 } 4915 4916 /* Add WD drivers. */ 4917 err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); 4918 if (err) 4919 goto fail_platform_wd_register; 4920 for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { 4921 if (mlxplat_wd_data[j]) { 4922 mlxplat_wd_data[j]->regmap = priv->regmap; 4923 priv->pdev_wd[j] = platform_device_register_resndata( 4924 &mlxplat_dev->dev, "mlx-wdt", 4925 j, NULL, 0, 4926 mlxplat_wd_data[j], 4927 sizeof(*mlxplat_wd_data[j])); 4928 if (IS_ERR(priv->pdev_wd[j])) { 4929 err = PTR_ERR(priv->pdev_wd[j]); 4930 goto fail_platform_wd_register; 4931 } 4932 } 4933 } 4934 4935 /* Sync registers with hardware. */ 4936 regcache_mark_dirty(priv->regmap); 4937 err = regcache_sync(priv->regmap); 4938 if (err) 4939 goto fail_platform_wd_register; 4940 4941 return 0; 4942 4943 fail_platform_wd_register: 4944 while (--j >= 0) 4945 platform_device_unregister(priv->pdev_wd[j]); 4946 if (mlxplat_fan) 4947 platform_device_unregister(priv->pdev_fan); 4948 fail_platform_io_regs_register: 4949 if (mlxplat_regs_io) 4950 platform_device_unregister(priv->pdev_io_regs); 4951 fail_platform_led_register: 4952 platform_device_unregister(priv->pdev_led); 4953 fail_platform_hotplug_register: 4954 platform_device_unregister(priv->pdev_hotplug); 4955 fail_platform_mux_register: 4956 while (--i >= 0) 4957 platform_device_unregister(priv->pdev_mux[i]); 4958 platform_device_unregister(priv->pdev_i2c); 4959 fail_alloc: 4960 platform_device_unregister(mlxplat_dev); 4961 4962 return err; 4963 } 4964 module_init(mlxplat_init); 4965 4966 static void __exit mlxplat_exit(void) 4967 { 4968 struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); 4969 int i; 4970 4971 for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) 4972 platform_device_unregister(priv->pdev_wd[i]); 4973 if (priv->pdev_fan) 4974 platform_device_unregister(priv->pdev_fan); 4975 if (priv->pdev_io_regs) 4976 platform_device_unregister(priv->pdev_io_regs); 4977 platform_device_unregister(priv->pdev_led); 4978 platform_device_unregister(priv->pdev_hotplug); 4979 4980 for (i = mlxplat_mux_num - 1; i >= 0 ; i--) 4981 platform_device_unregister(priv->pdev_mux[i]); 4982 4983 platform_device_unregister(priv->pdev_i2c); 4984 platform_device_unregister(mlxplat_dev); 4985 } 4986 module_exit(mlxplat_exit); 4987 4988 MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); 4989 MODULE_DESCRIPTION("Mellanox platform driver"); 4990 MODULE_LICENSE("Dual BSD/GPL"); 4991