1 /* 2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism 3 * 4 * (C) Copyright 2008-2010 Intel Corporation 5 * Author: Sreedhara DS (sreedhara.ds@intel.com) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 10 * of the License. 11 * 12 * SCU runing in ARC processor communicates with other entity running in IA 13 * core through IPC mechanism which in turn messaging between IA core ad SCU. 14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and 15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with 16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC) 17 * along with other APIs. 18 */ 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/init.h> 22 #include <linux/sysdev.h> 23 #include <linux/pm.h> 24 #include <linux/pci.h> 25 #include <linux/interrupt.h> 26 #include <asm/mrst.h> 27 #include <asm/intel_scu_ipc.h> 28 29 /* IPC defines the following message types */ 30 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */ 31 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */ 32 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */ 33 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */ 34 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */ 35 36 /* Command id associated with message IPCMSG_PCNTRL */ 37 #define IPC_CMD_PCNTRL_W 0 /* Register write */ 38 #define IPC_CMD_PCNTRL_R 1 /* Register read */ 39 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */ 40 41 /* 42 * IPC register summary 43 * 44 * IPC register blocks are memory mapped at fixed address of 0xFF11C000 45 * To read or write information to the SCU, driver writes to IPC-1 memory 46 * mapped registers (base address 0xFF11C000). The following is the IPC 47 * mechanism 48 * 49 * 1. IA core cDMI interface claims this transaction and converts it to a 50 * Transaction Layer Packet (TLP) message which is sent across the cDMI. 51 * 52 * 2. South Complex cDMI block receives this message and writes it to 53 * the IPC-1 register block, causing an interrupt to the SCU 54 * 55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate 56 * message handler is called within firmware. 57 */ 58 59 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */ 60 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */ 61 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */ 62 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */ 63 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */ 64 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */ 65 66 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id); 67 static void ipc_remove(struct pci_dev *pdev); 68 69 struct intel_scu_ipc_dev { 70 struct pci_dev *pdev; 71 void __iomem *ipc_base; 72 void __iomem *i2c_base; 73 }; 74 75 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */ 76 77 static int platform; /* Platform type */ 78 79 /* 80 * IPC Read Buffer (Read Only): 81 * 16 byte buffer for receiving data from SCU, if IPC command 82 * processing results in response data 83 */ 84 #define IPC_READ_BUFFER 0x90 85 86 #define IPC_I2C_CNTRL_ADDR 0 87 #define I2C_DATA_ADDR 0x04 88 89 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */ 90 91 /* 92 * Command Register (Write Only): 93 * A write to this register results in an interrupt to the SCU core processor 94 * Format: 95 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)| 96 */ 97 static inline void ipc_command(u32 cmd) /* Send ipc command */ 98 { 99 writel(cmd, ipcdev.ipc_base); 100 } 101 102 /* 103 * IPC Write Buffer (Write Only): 104 * 16-byte buffer for sending data associated with IPC command to 105 * SCU. Size of the data is specified in the IPC_COMMAND_REG register 106 */ 107 static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */ 108 { 109 writel(data, ipcdev.ipc_base + 0x80 + offset); 110 } 111 112 /* 113 * Status Register (Read Only): 114 * Driver will read this register to get the ready/busy status of the IPC 115 * block and error status of the IPC command that was just processed by SCU 116 * Format: 117 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)| 118 */ 119 120 static inline u8 ipc_read_status(void) 121 { 122 return __raw_readl(ipcdev.ipc_base + 0x04); 123 } 124 125 static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */ 126 { 127 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 128 } 129 130 static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */ 131 { 132 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset); 133 } 134 135 static inline int busy_loop(void) /* Wait till scu status is busy */ 136 { 137 u32 status = 0; 138 u32 loop_count = 0; 139 140 status = ipc_read_status(); 141 while (status & 1) { 142 udelay(1); /* scu processing time is in few u secods */ 143 status = ipc_read_status(); 144 loop_count++; 145 /* break if scu doesn't reset busy bit after huge retry */ 146 if (loop_count > 100000) { 147 dev_err(&ipcdev.pdev->dev, "IPC timed out"); 148 return -ETIMEDOUT; 149 } 150 } 151 if ((status >> 1) & 1) 152 return -EIO; 153 154 return 0; 155 } 156 157 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */ 158 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id) 159 { 160 int i, nc, bytes, d; 161 u32 offset = 0; 162 u32 err = 0; 163 u8 cbuf[IPC_WWBUF_SIZE] = { }; 164 u32 *wbuf = (u32 *)&cbuf; 165 166 mutex_lock(&ipclock); 167 168 memset(cbuf, 0, sizeof(cbuf)); 169 170 if (ipcdev.pdev == NULL) { 171 mutex_unlock(&ipclock); 172 return -ENODEV; 173 } 174 175 if (platform != MRST_CPU_CHIP_PENWELL) { 176 bytes = 0; 177 d = 0; 178 for (i = 0; i < count; i++) { 179 cbuf[bytes++] = addr[i]; 180 cbuf[bytes++] = addr[i] >> 8; 181 if (id != IPC_CMD_PCNTRL_R) 182 cbuf[bytes++] = data[d++]; 183 if (id == IPC_CMD_PCNTRL_M) 184 cbuf[bytes++] = data[d++]; 185 } 186 for (i = 0; i < bytes; i += 4) 187 ipc_data_writel(wbuf[i/4], i); 188 ipc_command(bytes << 16 | id << 12 | 0 << 8 | op); 189 } else { 190 for (nc = 0; nc < count; nc++, offset += 2) { 191 cbuf[offset] = addr[nc]; 192 cbuf[offset + 1] = addr[nc] >> 8; 193 } 194 195 if (id == IPC_CMD_PCNTRL_R) { 196 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 197 ipc_data_writel(wbuf[nc], offset); 198 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op); 199 } else if (id == IPC_CMD_PCNTRL_W) { 200 for (nc = 0; nc < count; nc++, offset += 1) 201 cbuf[offset] = data[nc]; 202 for (nc = 0, offset = 0; nc < count; nc++, offset += 4) 203 ipc_data_writel(wbuf[nc], offset); 204 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op); 205 } else if (id == IPC_CMD_PCNTRL_M) { 206 cbuf[offset] = data[0]; 207 cbuf[offset + 1] = data[1]; 208 ipc_data_writel(wbuf[0], 0); /* Write wbuff */ 209 ipc_command(4 << 16 | id << 12 | 0 << 8 | op); 210 } 211 } 212 213 err = busy_loop(); 214 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */ 215 /* Workaround: values are read as 0 without memcpy_fromio */ 216 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16); 217 if (platform != MRST_CPU_CHIP_PENWELL) { 218 for (nc = 0, offset = 2; nc < count; nc++, offset += 3) 219 data[nc] = ipc_data_readb(offset); 220 } else { 221 for (nc = 0; nc < count; nc++) 222 data[nc] = ipc_data_readb(nc); 223 } 224 } 225 mutex_unlock(&ipclock); 226 return err; 227 } 228 229 /** 230 * intel_scu_ipc_ioread8 - read a word via the SCU 231 * @addr: register on SCU 232 * @data: return pointer for read byte 233 * 234 * Read a single register. Returns 0 on success or an error code. All 235 * locking between SCU accesses is handled for the caller. 236 * 237 * This function may sleep. 238 */ 239 int intel_scu_ipc_ioread8(u16 addr, u8 *data) 240 { 241 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 242 } 243 EXPORT_SYMBOL(intel_scu_ipc_ioread8); 244 245 /** 246 * intel_scu_ipc_ioread16 - read a word via the SCU 247 * @addr: register on SCU 248 * @data: return pointer for read word 249 * 250 * Read a register pair. Returns 0 on success or an error code. All 251 * locking between SCU accesses is handled for the caller. 252 * 253 * This function may sleep. 254 */ 255 int intel_scu_ipc_ioread16(u16 addr, u16 *data) 256 { 257 u16 x[2] = {addr, addr + 1 }; 258 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 259 } 260 EXPORT_SYMBOL(intel_scu_ipc_ioread16); 261 262 /** 263 * intel_scu_ipc_ioread32 - read a dword via the SCU 264 * @addr: register on SCU 265 * @data: return pointer for read dword 266 * 267 * Read four registers. Returns 0 on success or an error code. All 268 * locking between SCU accesses is handled for the caller. 269 * 270 * This function may sleep. 271 */ 272 int intel_scu_ipc_ioread32(u16 addr, u32 *data) 273 { 274 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 275 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 276 } 277 EXPORT_SYMBOL(intel_scu_ipc_ioread32); 278 279 /** 280 * intel_scu_ipc_iowrite8 - write a byte via the SCU 281 * @addr: register on SCU 282 * @data: byte to write 283 * 284 * Write a single register. Returns 0 on success or an error code. All 285 * locking between SCU accesses is handled for the caller. 286 * 287 * This function may sleep. 288 */ 289 int intel_scu_ipc_iowrite8(u16 addr, u8 data) 290 { 291 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 292 } 293 EXPORT_SYMBOL(intel_scu_ipc_iowrite8); 294 295 /** 296 * intel_scu_ipc_iowrite16 - write a word via the SCU 297 * @addr: register on SCU 298 * @data: word to write 299 * 300 * Write two registers. Returns 0 on success or an error code. All 301 * locking between SCU accesses is handled for the caller. 302 * 303 * This function may sleep. 304 */ 305 int intel_scu_ipc_iowrite16(u16 addr, u16 data) 306 { 307 u16 x[2] = {addr, addr + 1 }; 308 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 309 } 310 EXPORT_SYMBOL(intel_scu_ipc_iowrite16); 311 312 /** 313 * intel_scu_ipc_iowrite32 - write a dword via the SCU 314 * @addr: register on SCU 315 * @data: dword to write 316 * 317 * Write four registers. Returns 0 on success or an error code. All 318 * locking between SCU accesses is handled for the caller. 319 * 320 * This function may sleep. 321 */ 322 int intel_scu_ipc_iowrite32(u16 addr, u32 data) 323 { 324 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3}; 325 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 326 } 327 EXPORT_SYMBOL(intel_scu_ipc_iowrite32); 328 329 /** 330 * intel_scu_ipc_readvv - read a set of registers 331 * @addr: register list 332 * @data: bytes to return 333 * @len: length of array 334 * 335 * Read registers. Returns 0 on success or an error code. All 336 * locking between SCU accesses is handled for the caller. 337 * 338 * The largest array length permitted by the hardware is 5 items. 339 * 340 * This function may sleep. 341 */ 342 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len) 343 { 344 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R); 345 } 346 EXPORT_SYMBOL(intel_scu_ipc_readv); 347 348 /** 349 * intel_scu_ipc_writev - write a set of registers 350 * @addr: register list 351 * @data: bytes to write 352 * @len: length of array 353 * 354 * Write registers. Returns 0 on success or an error code. All 355 * locking between SCU accesses is handled for the caller. 356 * 357 * The largest array length permitted by the hardware is 5 items. 358 * 359 * This function may sleep. 360 * 361 */ 362 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len) 363 { 364 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W); 365 } 366 EXPORT_SYMBOL(intel_scu_ipc_writev); 367 368 369 /** 370 * intel_scu_ipc_update_register - r/m/w a register 371 * @addr: register address 372 * @bits: bits to update 373 * @mask: mask of bits to update 374 * 375 * Read-modify-write power control unit register. The first data argument 376 * must be register value and second is mask value 377 * mask is a bitmap that indicates which bits to update. 378 * 0 = masked. Don't modify this bit, 1 = modify this bit. 379 * returns 0 on success or an error code. 380 * 381 * This function may sleep. Locking between SCU accesses is handled 382 * for the caller. 383 */ 384 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask) 385 { 386 u8 data[2] = { bits, mask }; 387 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M); 388 } 389 EXPORT_SYMBOL(intel_scu_ipc_update_register); 390 391 /** 392 * intel_scu_ipc_simple_command - send a simple command 393 * @cmd: command 394 * @sub: sub type 395 * 396 * Issue a simple command to the SCU. Do not use this interface if 397 * you must then access data as any data values may be overwritten 398 * by another SCU access by the time this function returns. 399 * 400 * This function may sleep. Locking for SCU accesses is handled for 401 * the caller. 402 */ 403 int intel_scu_ipc_simple_command(int cmd, int sub) 404 { 405 u32 err = 0; 406 407 mutex_lock(&ipclock); 408 if (ipcdev.pdev == NULL) { 409 mutex_unlock(&ipclock); 410 return -ENODEV; 411 } 412 ipc_command(sub << 12 | cmd); 413 err = busy_loop(); 414 mutex_unlock(&ipclock); 415 return err; 416 } 417 EXPORT_SYMBOL(intel_scu_ipc_simple_command); 418 419 /** 420 * intel_scu_ipc_command - command with data 421 * @cmd: command 422 * @sub: sub type 423 * @in: input data 424 * @inlen: input length in dwords 425 * @out: output data 426 * @outlein: output length in dwords 427 * 428 * Issue a command to the SCU which involves data transfers. Do the 429 * data copies under the lock but leave it for the caller to interpret 430 */ 431 432 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, 433 u32 *out, int outlen) 434 { 435 u32 err = 0; 436 int i = 0; 437 438 mutex_lock(&ipclock); 439 if (ipcdev.pdev == NULL) { 440 mutex_unlock(&ipclock); 441 return -ENODEV; 442 } 443 444 for (i = 0; i < inlen; i++) 445 ipc_data_writel(*in++, 4 * i); 446 447 ipc_command((inlen << 16) | (sub << 12) | cmd); 448 err = busy_loop(); 449 450 for (i = 0; i < outlen; i++) 451 *out++ = ipc_data_readl(4 * i); 452 453 mutex_unlock(&ipclock); 454 return err; 455 } 456 EXPORT_SYMBOL(intel_scu_ipc_command); 457 458 /*I2C commands */ 459 #define IPC_I2C_WRITE 1 /* I2C Write command */ 460 #define IPC_I2C_READ 2 /* I2C Read command */ 461 462 /** 463 * intel_scu_ipc_i2c_cntrl - I2C read/write operations 464 * @addr: I2C address + command bits 465 * @data: data to read/write 466 * 467 * Perform an an I2C read/write operation via the SCU. All locking is 468 * handled for the caller. This function may sleep. 469 * 470 * Returns an error code or 0 on success. 471 * 472 * This has to be in the IPC driver for the locking. 473 */ 474 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data) 475 { 476 u32 cmd = 0; 477 478 mutex_lock(&ipclock); 479 if (ipcdev.pdev == NULL) { 480 mutex_unlock(&ipclock); 481 return -ENODEV; 482 } 483 cmd = (addr >> 24) & 0xFF; 484 if (cmd == IPC_I2C_READ) { 485 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 486 /* Write not getting updated without delay */ 487 mdelay(1); 488 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR); 489 } else if (cmd == IPC_I2C_WRITE) { 490 writel(addr, ipcdev.i2c_base + I2C_DATA_ADDR); 491 mdelay(1); 492 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR); 493 } else { 494 dev_err(&ipcdev.pdev->dev, 495 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd); 496 497 mutex_unlock(&ipclock); 498 return -1; 499 } 500 mutex_unlock(&ipclock); 501 return 0; 502 } 503 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl); 504 505 #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */ 506 #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */ 507 #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */ 508 #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */ 509 /* IPC inform SCU to get ready for update process */ 510 #define IPC_CMD_FW_UPDATE_READY 0x10FE 511 /* IPC inform SCU to go for update process */ 512 #define IPC_CMD_FW_UPDATE_GO 0x20FE 513 /* Status code for fw update */ 514 #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */ 515 #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */ 516 #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */ 517 #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */ 518 519 struct fw_update_mailbox { 520 u32 status; 521 u32 scu_flag; 522 u32 driver_flag; 523 }; 524 525 526 /** 527 * intel_scu_ipc_fw_update - Firmware update utility 528 * @buffer: firmware buffer 529 * @length: size of firmware buffer 530 * 531 * This function provides an interface to load the firmware into 532 * the SCU. Returns 0 on success or -1 on failure 533 */ 534 int intel_scu_ipc_fw_update(u8 *buffer, u32 length) 535 { 536 void __iomem *fw_update_base; 537 struct fw_update_mailbox __iomem *mailbox = NULL; 538 int retry_cnt = 0; 539 u32 status; 540 541 mutex_lock(&ipclock); 542 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024)); 543 if (fw_update_base == NULL) { 544 mutex_unlock(&ipclock); 545 return -ENOMEM; 546 } 547 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR, 548 sizeof(struct fw_update_mailbox)); 549 if (mailbox == NULL) { 550 iounmap(fw_update_base); 551 mutex_unlock(&ipclock); 552 return -ENOMEM; 553 } 554 555 ipc_command(IPC_CMD_FW_UPDATE_READY); 556 557 /* Intitialize mailbox */ 558 writel(0, &mailbox->status); 559 writel(0, &mailbox->scu_flag); 560 writel(0, &mailbox->driver_flag); 561 562 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/ 563 memcpy_toio(fw_update_base, buffer, 0x800); 564 565 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02). 566 * Upon receiving this command, SCU will write the 2K MIP header 567 * from 0xFFFC0000 into NAND. 568 * SCU will write a status code into the Mailbox, and then set scu_flag. 569 */ 570 571 ipc_command(IPC_CMD_FW_UPDATE_GO); 572 573 /*Driver stalls until scu_flag is set */ 574 while (readl(&mailbox->scu_flag) != 1) { 575 rmb(); 576 mdelay(1); 577 } 578 579 /* Driver checks Mailbox status. 580 * If the status is 'BADN', then abort (bad NAND). 581 * If the status is 'IPC_FW_TXLOW', then continue. 582 */ 583 while (readl(&mailbox->status) != IPC_FW_TXLOW) { 584 rmb(); 585 mdelay(10); 586 } 587 mdelay(10); 588 589 update_retry: 590 if (retry_cnt > 5) 591 goto update_end; 592 593 if (readl(&mailbox->status) != IPC_FW_TXLOW) 594 goto update_end; 595 buffer = buffer + 0x800; 596 memcpy_toio(fw_update_base, buffer, 0x20000); 597 writel(1, &mailbox->driver_flag); 598 while (readl(&mailbox->scu_flag) == 1) { 599 rmb(); 600 mdelay(1); 601 } 602 603 /* check for 'BADN' */ 604 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) 605 goto update_end; 606 607 while (readl(&mailbox->status) != IPC_FW_TXHIGH) { 608 rmb(); 609 mdelay(10); 610 } 611 mdelay(10); 612 613 if (readl(&mailbox->status) != IPC_FW_TXHIGH) 614 goto update_end; 615 616 buffer = buffer + 0x20000; 617 memcpy_toio(fw_update_base, buffer, 0x20000); 618 writel(0, &mailbox->driver_flag); 619 620 while (mailbox->scu_flag == 0) { 621 rmb(); 622 mdelay(1); 623 } 624 625 /* check for 'BADN' */ 626 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN) 627 goto update_end; 628 629 if (readl(&mailbox->status) == IPC_FW_TXLOW) { 630 ++retry_cnt; 631 goto update_retry; 632 } 633 634 update_end: 635 status = readl(&mailbox->status); 636 637 iounmap(fw_update_base); 638 iounmap(mailbox); 639 mutex_unlock(&ipclock); 640 641 if (status == IPC_FW_UPDATE_SUCCESS) 642 return 0; 643 return -1; 644 } 645 EXPORT_SYMBOL(intel_scu_ipc_fw_update); 646 647 /* 648 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1 649 * When ioc bit is set to 1, caller api must wait for interrupt handler called 650 * which in turn unlocks the caller api. Currently this is not used 651 * 652 * This is edge triggered so we need take no action to clear anything 653 */ 654 static irqreturn_t ioc(int irq, void *dev_id) 655 { 656 return IRQ_HANDLED; 657 } 658 659 /** 660 * ipc_probe - probe an Intel SCU IPC 661 * @dev: the PCI device matching 662 * @id: entry in the match table 663 * 664 * Enable and install an intel SCU IPC. This appears in the PCI space 665 * but uses some hard coded addresses as well. 666 */ 667 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id) 668 { 669 int err; 670 resource_size_t pci_resource; 671 672 if (ipcdev.pdev) /* We support only one SCU */ 673 return -EBUSY; 674 675 ipcdev.pdev = pci_dev_get(dev); 676 677 err = pci_enable_device(dev); 678 if (err) 679 return err; 680 681 err = pci_request_regions(dev, "intel_scu_ipc"); 682 if (err) 683 return err; 684 685 pci_resource = pci_resource_start(dev, 0); 686 if (!pci_resource) 687 return -ENOMEM; 688 689 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev)) 690 return -EBUSY; 691 692 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR); 693 if (!ipcdev.ipc_base) 694 return -ENOMEM; 695 696 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR); 697 if (!ipcdev.i2c_base) { 698 iounmap(ipcdev.ipc_base); 699 return -ENOMEM; 700 } 701 return 0; 702 } 703 704 /** 705 * ipc_remove - remove a bound IPC device 706 * @pdev: PCI device 707 * 708 * In practice the SCU is not removable but this function is also 709 * called for each device on a module unload or cleanup which is the 710 * path that will get used. 711 * 712 * Free up the mappings and release the PCI resources 713 */ 714 static void ipc_remove(struct pci_dev *pdev) 715 { 716 free_irq(pdev->irq, &ipcdev); 717 pci_release_regions(pdev); 718 pci_dev_put(ipcdev.pdev); 719 iounmap(ipcdev.ipc_base); 720 iounmap(ipcdev.i2c_base); 721 ipcdev.pdev = NULL; 722 } 723 724 static const struct pci_device_id pci_ids[] = { 725 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)}, 726 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)}, 727 { 0,} 728 }; 729 MODULE_DEVICE_TABLE(pci, pci_ids); 730 731 static struct pci_driver ipc_driver = { 732 .name = "intel_scu_ipc", 733 .id_table = pci_ids, 734 .probe = ipc_probe, 735 .remove = ipc_remove, 736 }; 737 738 739 static int __init intel_scu_ipc_init(void) 740 { 741 platform = mrst_identify_cpu(); 742 if (platform == 0) 743 return -ENODEV; 744 return pci_register_driver(&ipc_driver); 745 } 746 747 static void __exit intel_scu_ipc_exit(void) 748 { 749 pci_unregister_driver(&ipc_driver); 750 } 751 752 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>"); 753 MODULE_DESCRIPTION("Intel SCU IPC driver"); 754 MODULE_LICENSE("GPL"); 755 756 module_init(intel_scu_ipc_init); 757 module_exit(intel_scu_ipc_exit); 758