1 /* 2 * Copyright (c) 2009-2010 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * The full GNU General Public License is included in this distribution in 14 * the file called "COPYING". 15 * 16 * Authors: 17 * Jesse Barnes <jbarnes@virtuousgeek.org> 18 */ 19 20 /* 21 * Some Intel Ibex Peak based platforms support so-called "intelligent 22 * power sharing", which allows the CPU and GPU to cooperate to maximize 23 * performance within a given TDP (thermal design point). This driver 24 * performs the coordination between the CPU and GPU, monitors thermal and 25 * power statistics in the platform, and initializes power monitoring 26 * hardware. It also provides a few tunables to control behavior. Its 27 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled 28 * by tracking power and thermal budget; secondarily it can boost turbo 29 * performance by allocating more power or thermal budget to the CPU or GPU 30 * based on available headroom and activity. 31 * 32 * The basic algorithm is driven by a 5s moving average of temperature. If 33 * thermal headroom is available, the CPU and/or GPU power clamps may be 34 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger, 35 * we scale back the clamp. Aside from trigger events (when we're critically 36 * close or over our TDP) we don't adjust the clamps more than once every 37 * five seconds. 38 * 39 * The thermal device (device 31, function 6) has a set of registers that 40 * are updated by the ME firmware. The ME should also take the clamp values 41 * written to those registers and write them to the CPU, but we currently 42 * bypass that functionality and write the CPU MSR directly. 43 * 44 * UNSUPPORTED: 45 * - dual MCP configs 46 * 47 * TODO: 48 * - handle CPU hotplug 49 * - provide turbo enable/disable api 50 * 51 * Related documents: 52 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2 53 * - CDI 401376 - Ibex Peak EDS 54 * - ref 26037, 26641 - IPS BIOS spec 55 * - ref 26489 - Nehalem BIOS writer's guide 56 * - ref 26921 - Ibex Peak BIOS Specification 57 */ 58 59 #include <linux/debugfs.h> 60 #include <linux/delay.h> 61 #include <linux/interrupt.h> 62 #include <linux/kernel.h> 63 #include <linux/kthread.h> 64 #include <linux/module.h> 65 #include <linux/pci.h> 66 #include <linux/sched.h> 67 #include <linux/sched/loadavg.h> 68 #include <linux/seq_file.h> 69 #include <linux/string.h> 70 #include <linux/tick.h> 71 #include <linux/timer.h> 72 #include <linux/dmi.h> 73 #include <drm/i915_drm.h> 74 #include <asm/msr.h> 75 #include <asm/processor.h> 76 #include "intel_ips.h" 77 78 #include <linux/io-64-nonatomic-lo-hi.h> 79 80 #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32 81 82 /* 83 * Package level MSRs for monitor/control 84 */ 85 #define PLATFORM_INFO 0xce 86 #define PLATFORM_TDP (1<<29) 87 #define PLATFORM_RATIO (1<<28) 88 89 #define IA32_MISC_ENABLE 0x1a0 90 #define IA32_MISC_TURBO_EN (1ULL<<38) 91 92 #define TURBO_POWER_CURRENT_LIMIT 0x1ac 93 #define TURBO_TDC_OVR_EN (1UL<<31) 94 #define TURBO_TDC_MASK (0x000000007fff0000UL) 95 #define TURBO_TDC_SHIFT (16) 96 #define TURBO_TDP_OVR_EN (1UL<<15) 97 #define TURBO_TDP_MASK (0x0000000000003fffUL) 98 99 /* 100 * Core/thread MSRs for monitoring 101 */ 102 #define IA32_PERF_CTL 0x199 103 #define IA32_PERF_TURBO_DIS (1ULL<<32) 104 105 /* 106 * Thermal PCI device regs 107 */ 108 #define THM_CFG_TBAR 0x10 109 #define THM_CFG_TBAR_HI 0x14 110 111 #define THM_TSIU 0x00 112 #define THM_TSE 0x01 113 #define TSE_EN 0xb8 114 #define THM_TSS 0x02 115 #define THM_TSTR 0x03 116 #define THM_TSTTP 0x04 117 #define THM_TSCO 0x08 118 #define THM_TSES 0x0c 119 #define THM_TSGPEN 0x0d 120 #define TSGPEN_HOT_LOHI (1<<1) 121 #define TSGPEN_CRIT_LOHI (1<<2) 122 #define THM_TSPC 0x0e 123 #define THM_PPEC 0x10 124 #define THM_CTA 0x12 125 #define THM_PTA 0x14 126 #define PTA_SLOPE_MASK (0xff00) 127 #define PTA_SLOPE_SHIFT 8 128 #define PTA_OFFSET_MASK (0x00ff) 129 #define THM_MGTA 0x16 130 #define MGTA_SLOPE_MASK (0xff00) 131 #define MGTA_SLOPE_SHIFT 8 132 #define MGTA_OFFSET_MASK (0x00ff) 133 #define THM_TRC 0x1a 134 #define TRC_CORE2_EN (1<<15) 135 #define TRC_THM_EN (1<<12) 136 #define TRC_C6_WAR (1<<8) 137 #define TRC_CORE1_EN (1<<7) 138 #define TRC_CORE_PWR (1<<6) 139 #define TRC_PCH_EN (1<<5) 140 #define TRC_MCH_EN (1<<4) 141 #define TRC_DIMM4 (1<<3) 142 #define TRC_DIMM3 (1<<2) 143 #define TRC_DIMM2 (1<<1) 144 #define TRC_DIMM1 (1<<0) 145 #define THM_TES 0x20 146 #define THM_TEN 0x21 147 #define TEN_UPDATE_EN 1 148 #define THM_PSC 0x24 149 #define PSC_NTG (1<<0) /* No GFX turbo support */ 150 #define PSC_NTPC (1<<1) /* No CPU turbo support */ 151 #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */ 152 #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */ 153 #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */ 154 #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */ 155 #define PSP_PBRT (1<<4) /* BIOS run time support */ 156 #define THM_CTV1 0x30 157 #define CTV_TEMP_ERROR (1<<15) 158 #define CTV_TEMP_MASK 0x3f 159 #define CTV_ 160 #define THM_CTV2 0x32 161 #define THM_CEC 0x34 /* undocumented power accumulator in joules */ 162 #define THM_AE 0x3f 163 #define THM_HTS 0x50 /* 32 bits */ 164 #define HTS_PCPL_MASK (0x7fe00000) 165 #define HTS_PCPL_SHIFT 21 166 #define HTS_GPL_MASK (0x001ff000) 167 #define HTS_GPL_SHIFT 12 168 #define HTS_PP_MASK (0x00000c00) 169 #define HTS_PP_SHIFT 10 170 #define HTS_PP_DEF 0 171 #define HTS_PP_PROC 1 172 #define HTS_PP_BAL 2 173 #define HTS_PP_GFX 3 174 #define HTS_PCTD_DIS (1<<9) 175 #define HTS_GTD_DIS (1<<8) 176 #define HTS_PTL_MASK (0x000000fe) 177 #define HTS_PTL_SHIFT 1 178 #define HTS_NVV (1<<0) 179 #define THM_HTSHI 0x54 /* 16 bits */ 180 #define HTS2_PPL_MASK (0x03ff) 181 #define HTS2_PRST_MASK (0x3c00) 182 #define HTS2_PRST_SHIFT 10 183 #define HTS2_PRST_UNLOADED 0 184 #define HTS2_PRST_RUNNING 1 185 #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */ 186 #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */ 187 #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */ 188 #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */ 189 #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */ 190 #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */ 191 #define THM_PTL 0x56 192 #define THM_MGTV 0x58 193 #define TV_MASK 0x000000000000ff00 194 #define TV_SHIFT 8 195 #define THM_PTV 0x60 196 #define PTV_MASK 0x00ff 197 #define THM_MMGPC 0x64 198 #define THM_MPPC 0x66 199 #define THM_MPCPC 0x68 200 #define THM_TSPIEN 0x82 201 #define TSPIEN_AUX_LOHI (1<<0) 202 #define TSPIEN_HOT_LOHI (1<<1) 203 #define TSPIEN_CRIT_LOHI (1<<2) 204 #define TSPIEN_AUX2_LOHI (1<<3) 205 #define THM_TSLOCK 0x83 206 #define THM_ATR 0x84 207 #define THM_TOF 0x87 208 #define THM_STS 0x98 209 #define STS_PCPL_MASK (0x7fe00000) 210 #define STS_PCPL_SHIFT 21 211 #define STS_GPL_MASK (0x001ff000) 212 #define STS_GPL_SHIFT 12 213 #define STS_PP_MASK (0x00000c00) 214 #define STS_PP_SHIFT 10 215 #define STS_PP_DEF 0 216 #define STS_PP_PROC 1 217 #define STS_PP_BAL 2 218 #define STS_PP_GFX 3 219 #define STS_PCTD_DIS (1<<9) 220 #define STS_GTD_DIS (1<<8) 221 #define STS_PTL_MASK (0x000000fe) 222 #define STS_PTL_SHIFT 1 223 #define STS_NVV (1<<0) 224 #define THM_SEC 0x9c 225 #define SEC_ACK (1<<0) 226 #define THM_TC3 0xa4 227 #define THM_TC1 0xa8 228 #define STS_PPL_MASK (0x0003ff00) 229 #define STS_PPL_SHIFT 16 230 #define THM_TC2 0xac 231 #define THM_DTV 0xb0 232 #define THM_ITV 0xd8 233 #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */ 234 #define ITV_ME_SEQNO_SHIFT (16) 235 #define ITV_MCH_TEMP_MASK 0x0000ff00 236 #define ITV_MCH_TEMP_SHIFT (8) 237 #define ITV_PCH_TEMP_MASK 0x000000ff 238 239 #define thm_readb(off) readb(ips->regmap + (off)) 240 #define thm_readw(off) readw(ips->regmap + (off)) 241 #define thm_readl(off) readl(ips->regmap + (off)) 242 #define thm_readq(off) readq(ips->regmap + (off)) 243 244 #define thm_writeb(off, val) writeb((val), ips->regmap + (off)) 245 #define thm_writew(off, val) writew((val), ips->regmap + (off)) 246 #define thm_writel(off, val) writel((val), ips->regmap + (off)) 247 248 static const int IPS_ADJUST_PERIOD = 5000; /* ms */ 249 static bool late_i915_load = false; 250 251 /* For initial average collection */ 252 static const int IPS_SAMPLE_PERIOD = 200; /* ms */ 253 static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */ 254 #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD) 255 256 /* Per-SKU limits */ 257 struct ips_mcp_limits { 258 int mcp_power_limit; /* mW units */ 259 int core_power_limit; 260 int mch_power_limit; 261 int core_temp_limit; /* degrees C */ 262 int mch_temp_limit; 263 }; 264 265 /* Max temps are -10 degrees C to avoid PROCHOT# */ 266 267 static struct ips_mcp_limits ips_sv_limits = { 268 .mcp_power_limit = 35000, 269 .core_power_limit = 29000, 270 .mch_power_limit = 20000, 271 .core_temp_limit = 95, 272 .mch_temp_limit = 90 273 }; 274 275 static struct ips_mcp_limits ips_lv_limits = { 276 .mcp_power_limit = 25000, 277 .core_power_limit = 21000, 278 .mch_power_limit = 13000, 279 .core_temp_limit = 95, 280 .mch_temp_limit = 90 281 }; 282 283 static struct ips_mcp_limits ips_ulv_limits = { 284 .mcp_power_limit = 18000, 285 .core_power_limit = 14000, 286 .mch_power_limit = 11000, 287 .core_temp_limit = 95, 288 .mch_temp_limit = 90 289 }; 290 291 struct ips_driver { 292 struct device *dev; 293 void __iomem *regmap; 294 int irq; 295 296 struct task_struct *monitor; 297 struct task_struct *adjust; 298 struct dentry *debug_root; 299 300 /* Average CPU core temps (all averages in .01 degrees C for precision) */ 301 u16 ctv1_avg_temp; 302 u16 ctv2_avg_temp; 303 /* GMCH average */ 304 u16 mch_avg_temp; 305 /* Average for the CPU (both cores?) */ 306 u16 mcp_avg_temp; 307 /* Average power consumption (in mW) */ 308 u32 cpu_avg_power; 309 u32 mch_avg_power; 310 311 /* Offset values */ 312 u16 cta_val; 313 u16 pta_val; 314 u16 mgta_val; 315 316 /* Maximums & prefs, protected by turbo status lock */ 317 spinlock_t turbo_status_lock; 318 u16 mcp_temp_limit; 319 u16 mcp_power_limit; 320 u16 core_power_limit; 321 u16 mch_power_limit; 322 bool cpu_turbo_enabled; 323 bool __cpu_turbo_on; 324 bool gpu_turbo_enabled; 325 bool __gpu_turbo_on; 326 bool gpu_preferred; 327 bool poll_turbo_status; 328 bool second_cpu; 329 bool turbo_toggle_allowed; 330 struct ips_mcp_limits *limits; 331 332 /* Optional MCH interfaces for if i915 is in use */ 333 unsigned long (*read_mch_val)(void); 334 bool (*gpu_raise)(void); 335 bool (*gpu_lower)(void); 336 bool (*gpu_busy)(void); 337 bool (*gpu_turbo_disable)(void); 338 339 /* For restoration at unload */ 340 u64 orig_turbo_limit; 341 u64 orig_turbo_ratios; 342 }; 343 344 static bool 345 ips_gpu_turbo_enabled(struct ips_driver *ips); 346 347 /** 348 * ips_cpu_busy - is CPU busy? 349 * @ips: IPS driver struct 350 * 351 * Check CPU for load to see whether we should increase its thermal budget. 352 * 353 * RETURNS: 354 * True if the CPU could use more power, false otherwise. 355 */ 356 static bool ips_cpu_busy(struct ips_driver *ips) 357 { 358 if ((avenrun[0] >> FSHIFT) > 1) 359 return true; 360 361 return false; 362 } 363 364 /** 365 * ips_cpu_raise - raise CPU power clamp 366 * @ips: IPS driver struct 367 * 368 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for 369 * this platform. 370 * 371 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as 372 * long as we haven't hit the TDP limit for the SKU). 373 */ 374 static void ips_cpu_raise(struct ips_driver *ips) 375 { 376 u64 turbo_override; 377 u16 cur_tdp_limit, new_tdp_limit; 378 379 if (!ips->cpu_turbo_enabled) 380 return; 381 382 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 383 384 cur_tdp_limit = turbo_override & TURBO_TDP_MASK; 385 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ 386 387 /* Clamp to SKU TDP limit */ 388 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit) 389 new_tdp_limit = cur_tdp_limit; 390 391 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); 392 393 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 394 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 395 396 turbo_override &= ~TURBO_TDP_MASK; 397 turbo_override |= new_tdp_limit; 398 399 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 400 } 401 402 /** 403 * ips_cpu_lower - lower CPU power clamp 404 * @ips: IPS driver struct 405 * 406 * Lower CPU power clamp b %IPS_CPU_STEP if possible. 407 * 408 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going 409 * as low as the platform limits will allow (though we could go lower there 410 * wouldn't be much point). 411 */ 412 static void ips_cpu_lower(struct ips_driver *ips) 413 { 414 u64 turbo_override; 415 u16 cur_limit, new_limit; 416 417 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 418 419 cur_limit = turbo_override & TURBO_TDP_MASK; 420 new_limit = cur_limit - 8; /* 1W decrease */ 421 422 /* Clamp to SKU TDP limit */ 423 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK)) 424 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK; 425 426 thm_writew(THM_MPCPC, (new_limit * 10) / 8); 427 428 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 429 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 430 431 turbo_override &= ~TURBO_TDP_MASK; 432 turbo_override |= new_limit; 433 434 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 435 } 436 437 /** 438 * do_enable_cpu_turbo - internal turbo enable function 439 * @data: unused 440 * 441 * Internal function for actually updating MSRs. When we enable/disable 442 * turbo, we need to do it on each CPU; this function is the one called 443 * by on_each_cpu() when needed. 444 */ 445 static void do_enable_cpu_turbo(void *data) 446 { 447 u64 perf_ctl; 448 449 rdmsrl(IA32_PERF_CTL, perf_ctl); 450 if (perf_ctl & IA32_PERF_TURBO_DIS) { 451 perf_ctl &= ~IA32_PERF_TURBO_DIS; 452 wrmsrl(IA32_PERF_CTL, perf_ctl); 453 } 454 } 455 456 /** 457 * ips_enable_cpu_turbo - enable turbo mode on all CPUs 458 * @ips: IPS driver struct 459 * 460 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on 461 * all logical threads. 462 */ 463 static void ips_enable_cpu_turbo(struct ips_driver *ips) 464 { 465 /* Already on, no need to mess with MSRs */ 466 if (ips->__cpu_turbo_on) 467 return; 468 469 if (ips->turbo_toggle_allowed) 470 on_each_cpu(do_enable_cpu_turbo, ips, 1); 471 472 ips->__cpu_turbo_on = true; 473 } 474 475 /** 476 * do_disable_cpu_turbo - internal turbo disable function 477 * @data: unused 478 * 479 * Internal function for actually updating MSRs. When we enable/disable 480 * turbo, we need to do it on each CPU; this function is the one called 481 * by on_each_cpu() when needed. 482 */ 483 static void do_disable_cpu_turbo(void *data) 484 { 485 u64 perf_ctl; 486 487 rdmsrl(IA32_PERF_CTL, perf_ctl); 488 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { 489 perf_ctl |= IA32_PERF_TURBO_DIS; 490 wrmsrl(IA32_PERF_CTL, perf_ctl); 491 } 492 } 493 494 /** 495 * ips_disable_cpu_turbo - disable turbo mode on all CPUs 496 * @ips: IPS driver struct 497 * 498 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on 499 * all logical threads. 500 */ 501 static void ips_disable_cpu_turbo(struct ips_driver *ips) 502 { 503 /* Already off, leave it */ 504 if (!ips->__cpu_turbo_on) 505 return; 506 507 if (ips->turbo_toggle_allowed) 508 on_each_cpu(do_disable_cpu_turbo, ips, 1); 509 510 ips->__cpu_turbo_on = false; 511 } 512 513 /** 514 * ips_gpu_busy - is GPU busy? 515 * @ips: IPS driver struct 516 * 517 * Check GPU for load to see whether we should increase its thermal budget. 518 * We need to call into the i915 driver in this case. 519 * 520 * RETURNS: 521 * True if the GPU could use more power, false otherwise. 522 */ 523 static bool ips_gpu_busy(struct ips_driver *ips) 524 { 525 if (!ips_gpu_turbo_enabled(ips)) 526 return false; 527 528 return ips->gpu_busy(); 529 } 530 531 /** 532 * ips_gpu_raise - raise GPU power clamp 533 * @ips: IPS driver struct 534 * 535 * Raise the GPU frequency/power if possible. We need to call into the 536 * i915 driver in this case. 537 */ 538 static void ips_gpu_raise(struct ips_driver *ips) 539 { 540 if (!ips_gpu_turbo_enabled(ips)) 541 return; 542 543 if (!ips->gpu_raise()) 544 ips->gpu_turbo_enabled = false; 545 546 return; 547 } 548 549 /** 550 * ips_gpu_lower - lower GPU power clamp 551 * @ips: IPS driver struct 552 * 553 * Lower GPU frequency/power if possible. Need to call i915. 554 */ 555 static void ips_gpu_lower(struct ips_driver *ips) 556 { 557 if (!ips_gpu_turbo_enabled(ips)) 558 return; 559 560 if (!ips->gpu_lower()) 561 ips->gpu_turbo_enabled = false; 562 563 return; 564 } 565 566 /** 567 * ips_enable_gpu_turbo - notify the gfx driver turbo is available 568 * @ips: IPS driver struct 569 * 570 * Call into the graphics driver indicating that it can safely use 571 * turbo mode. 572 */ 573 static void ips_enable_gpu_turbo(struct ips_driver *ips) 574 { 575 if (ips->__gpu_turbo_on) 576 return; 577 ips->__gpu_turbo_on = true; 578 } 579 580 /** 581 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode 582 * @ips: IPS driver struct 583 * 584 * Request that the graphics driver disable turbo mode. 585 */ 586 static void ips_disable_gpu_turbo(struct ips_driver *ips) 587 { 588 /* Avoid calling i915 if turbo is already disabled */ 589 if (!ips->__gpu_turbo_on) 590 return; 591 592 if (!ips->gpu_turbo_disable()) 593 dev_err(ips->dev, "failed to disable graphics turbo\n"); 594 else 595 ips->__gpu_turbo_on = false; 596 } 597 598 /** 599 * mcp_exceeded - check whether we're outside our thermal & power limits 600 * @ips: IPS driver struct 601 * 602 * Check whether the MCP is over its thermal or power budget. 603 */ 604 static bool mcp_exceeded(struct ips_driver *ips) 605 { 606 unsigned long flags; 607 bool ret = false; 608 u32 temp_limit; 609 u32 avg_power; 610 611 spin_lock_irqsave(&ips->turbo_status_lock, flags); 612 613 temp_limit = ips->mcp_temp_limit * 100; 614 if (ips->mcp_avg_temp > temp_limit) 615 ret = true; 616 617 avg_power = ips->cpu_avg_power + ips->mch_avg_power; 618 if (avg_power > ips->mcp_power_limit) 619 ret = true; 620 621 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 622 623 return ret; 624 } 625 626 /** 627 * cpu_exceeded - check whether a CPU core is outside its limits 628 * @ips: IPS driver struct 629 * @cpu: CPU number to check 630 * 631 * Check a given CPU's average temp or power is over its limit. 632 */ 633 static bool cpu_exceeded(struct ips_driver *ips, int cpu) 634 { 635 unsigned long flags; 636 int avg; 637 bool ret = false; 638 639 spin_lock_irqsave(&ips->turbo_status_lock, flags); 640 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp; 641 if (avg > (ips->limits->core_temp_limit * 100)) 642 ret = true; 643 if (ips->cpu_avg_power > ips->core_power_limit * 100) 644 ret = true; 645 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 646 647 if (ret) 648 dev_info(ips->dev, "CPU power or thermal limit exceeded\n"); 649 650 return ret; 651 } 652 653 /** 654 * mch_exceeded - check whether the GPU is over budget 655 * @ips: IPS driver struct 656 * 657 * Check the MCH temp & power against their maximums. 658 */ 659 static bool mch_exceeded(struct ips_driver *ips) 660 { 661 unsigned long flags; 662 bool ret = false; 663 664 spin_lock_irqsave(&ips->turbo_status_lock, flags); 665 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) 666 ret = true; 667 if (ips->mch_avg_power > ips->mch_power_limit) 668 ret = true; 669 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 670 671 return ret; 672 } 673 674 /** 675 * verify_limits - verify BIOS provided limits 676 * @ips: IPS structure 677 * 678 * BIOS can optionally provide non-default limits for power and temp. Check 679 * them here and use the defaults if the BIOS values are not provided or 680 * are otherwise unusable. 681 */ 682 static void verify_limits(struct ips_driver *ips) 683 { 684 if (ips->mcp_power_limit < ips->limits->mcp_power_limit || 685 ips->mcp_power_limit > 35000) 686 ips->mcp_power_limit = ips->limits->mcp_power_limit; 687 688 if (ips->mcp_temp_limit < ips->limits->core_temp_limit || 689 ips->mcp_temp_limit < ips->limits->mch_temp_limit || 690 ips->mcp_temp_limit > 150) 691 ips->mcp_temp_limit = min(ips->limits->core_temp_limit, 692 ips->limits->mch_temp_limit); 693 } 694 695 /** 696 * update_turbo_limits - get various limits & settings from regs 697 * @ips: IPS driver struct 698 * 699 * Update the IPS power & temp limits, along with turbo enable flags, 700 * based on latest register contents. 701 * 702 * Used at init time and for runtime BIOS support, which requires polling 703 * the regs for updates (as a result of AC->DC transition for example). 704 * 705 * LOCKING: 706 * Caller must hold turbo_status_lock (outside of init) 707 */ 708 static void update_turbo_limits(struct ips_driver *ips) 709 { 710 u32 hts = thm_readl(THM_HTS); 711 712 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS); 713 /* 714 * Disable turbo for now, until we can figure out why the power figures 715 * are wrong 716 */ 717 ips->cpu_turbo_enabled = false; 718 719 if (ips->gpu_busy) 720 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS); 721 722 ips->core_power_limit = thm_readw(THM_MPCPC); 723 ips->mch_power_limit = thm_readw(THM_MMGPC); 724 ips->mcp_temp_limit = thm_readw(THM_PTL); 725 ips->mcp_power_limit = thm_readw(THM_MPPC); 726 727 verify_limits(ips); 728 /* Ignore BIOS CPU vs GPU pref */ 729 } 730 731 /** 732 * ips_adjust - adjust power clamp based on thermal state 733 * @data: ips driver structure 734 * 735 * Wake up every 5s or so and check whether we should adjust the power clamp. 736 * Check CPU and GPU load to determine which needs adjustment. There are 737 * several things to consider here: 738 * - do we need to adjust up or down? 739 * - is CPU busy? 740 * - is GPU busy? 741 * - is CPU in turbo? 742 * - is GPU in turbo? 743 * - is CPU or GPU preferred? (CPU is default) 744 * 745 * So, given the above, we do the following: 746 * - up (TDP available) 747 * - CPU not busy, GPU not busy - nothing 748 * - CPU busy, GPU not busy - adjust CPU up 749 * - CPU not busy, GPU busy - adjust GPU up 750 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from 751 * non-preferred unit if necessary 752 * - down (at TDP limit) 753 * - adjust both CPU and GPU down if possible 754 * 755 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu- 756 cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing 757 cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu- 758 cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu- 759 cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu- 760 * 761 */ 762 static int ips_adjust(void *data) 763 { 764 struct ips_driver *ips = data; 765 unsigned long flags; 766 767 dev_dbg(ips->dev, "starting ips-adjust thread\n"); 768 769 /* 770 * Adjust CPU and GPU clamps every 5s if needed. Doing it more 771 * often isn't recommended due to ME interaction. 772 */ 773 do { 774 bool cpu_busy = ips_cpu_busy(ips); 775 bool gpu_busy = ips_gpu_busy(ips); 776 777 spin_lock_irqsave(&ips->turbo_status_lock, flags); 778 if (ips->poll_turbo_status) 779 update_turbo_limits(ips); 780 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 781 782 /* Update turbo status if necessary */ 783 if (ips->cpu_turbo_enabled) 784 ips_enable_cpu_turbo(ips); 785 else 786 ips_disable_cpu_turbo(ips); 787 788 if (ips->gpu_turbo_enabled) 789 ips_enable_gpu_turbo(ips); 790 else 791 ips_disable_gpu_turbo(ips); 792 793 /* We're outside our comfort zone, crank them down */ 794 if (mcp_exceeded(ips)) { 795 ips_cpu_lower(ips); 796 ips_gpu_lower(ips); 797 goto sleep; 798 } 799 800 if (!cpu_exceeded(ips, 0) && cpu_busy) 801 ips_cpu_raise(ips); 802 else 803 ips_cpu_lower(ips); 804 805 if (!mch_exceeded(ips) && gpu_busy) 806 ips_gpu_raise(ips); 807 else 808 ips_gpu_lower(ips); 809 810 sleep: 811 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD)); 812 } while (!kthread_should_stop()); 813 814 dev_dbg(ips->dev, "ips-adjust thread stopped\n"); 815 816 return 0; 817 } 818 819 /* 820 * Helpers for reading out temp/power values and calculating their 821 * averages for the decision making and monitoring functions. 822 */ 823 824 static u16 calc_avg_temp(struct ips_driver *ips, u16 *array) 825 { 826 u64 total = 0; 827 int i; 828 u16 avg; 829 830 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 831 total += (u64)(array[i] * 100); 832 833 do_div(total, IPS_SAMPLE_COUNT); 834 835 avg = (u16)total; 836 837 return avg; 838 } 839 840 static u16 read_mgtv(struct ips_driver *ips) 841 { 842 u16 ret; 843 u64 slope, offset; 844 u64 val; 845 846 val = thm_readq(THM_MGTV); 847 val = (val & TV_MASK) >> TV_SHIFT; 848 849 slope = offset = thm_readw(THM_MGTA); 850 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT; 851 offset = offset & MGTA_OFFSET_MASK; 852 853 ret = ((val * slope + 0x40) >> 7) + offset; 854 855 return 0; /* MCH temp reporting buggy */ 856 } 857 858 static u16 read_ptv(struct ips_driver *ips) 859 { 860 u16 val, slope, offset; 861 862 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT; 863 offset = ips->pta_val & PTA_OFFSET_MASK; 864 865 val = thm_readw(THM_PTV) & PTV_MASK; 866 867 return val; 868 } 869 870 static u16 read_ctv(struct ips_driver *ips, int cpu) 871 { 872 int reg = cpu ? THM_CTV2 : THM_CTV1; 873 u16 val; 874 875 val = thm_readw(reg); 876 if (!(val & CTV_TEMP_ERROR)) 877 val = (val) >> 6; /* discard fractional component */ 878 else 879 val = 0; 880 881 return val; 882 } 883 884 static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period) 885 { 886 u32 val; 887 u32 ret; 888 889 /* 890 * CEC is in joules/65535. Take difference over time to 891 * get watts. 892 */ 893 val = thm_readl(THM_CEC); 894 895 /* period is in ms and we want mW */ 896 ret = (((val - *last) * 1000) / period); 897 ret = (ret * 1000) / 65535; 898 *last = val; 899 900 return 0; 901 } 902 903 static const u16 temp_decay_factor = 2; 904 static u16 update_average_temp(u16 avg, u16 val) 905 { 906 u16 ret; 907 908 /* Multiply by 100 for extra precision */ 909 ret = (val * 100 / temp_decay_factor) + 910 (((temp_decay_factor - 1) * avg) / temp_decay_factor); 911 return ret; 912 } 913 914 static const u16 power_decay_factor = 2; 915 static u16 update_average_power(u32 avg, u32 val) 916 { 917 u32 ret; 918 919 ret = (val / power_decay_factor) + 920 (((power_decay_factor - 1) * avg) / power_decay_factor); 921 922 return ret; 923 } 924 925 static u32 calc_avg_power(struct ips_driver *ips, u32 *array) 926 { 927 u64 total = 0; 928 u32 avg; 929 int i; 930 931 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 932 total += array[i]; 933 934 do_div(total, IPS_SAMPLE_COUNT); 935 avg = (u32)total; 936 937 return avg; 938 } 939 940 static void monitor_timeout(unsigned long arg) 941 { 942 wake_up_process((struct task_struct *)arg); 943 } 944 945 /** 946 * ips_monitor - temp/power monitoring thread 947 * @data: ips driver structure 948 * 949 * This is the main function for the IPS driver. It monitors power and 950 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly. 951 * 952 * We keep a 5s moving average of power consumption and tempurature. Using 953 * that data, along with CPU vs GPU preference, we adjust the power clamps 954 * up or down. 955 */ 956 static int ips_monitor(void *data) 957 { 958 struct ips_driver *ips = data; 959 struct timer_list timer; 960 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period; 961 int i; 962 u32 *cpu_samples, *mchp_samples, old_cpu_power; 963 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples; 964 u8 cur_seqno, last_seqno; 965 966 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 967 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 968 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 969 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 970 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 971 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 972 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples || 973 !cpu_samples || !mchp_samples) { 974 dev_err(ips->dev, 975 "failed to allocate sample array, ips disabled\n"); 976 kfree(mcp_samples); 977 kfree(ctv1_samples); 978 kfree(ctv2_samples); 979 kfree(mch_samples); 980 kfree(cpu_samples); 981 kfree(mchp_samples); 982 return -ENOMEM; 983 } 984 985 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 986 ITV_ME_SEQNO_SHIFT; 987 seqno_timestamp = get_jiffies_64(); 988 989 old_cpu_power = thm_readl(THM_CEC); 990 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 991 992 /* Collect an initial average */ 993 for (i = 0; i < IPS_SAMPLE_COUNT; i++) { 994 u32 mchp, cpu_power; 995 u16 val; 996 997 mcp_samples[i] = read_ptv(ips); 998 999 val = read_ctv(ips, 0); 1000 ctv1_samples[i] = val; 1001 1002 val = read_ctv(ips, 1); 1003 ctv2_samples[i] = val; 1004 1005 val = read_mgtv(ips); 1006 mch_samples[i] = val; 1007 1008 cpu_power = get_cpu_power(ips, &old_cpu_power, 1009 IPS_SAMPLE_PERIOD); 1010 cpu_samples[i] = cpu_power; 1011 1012 if (ips->read_mch_val) { 1013 mchp = ips->read_mch_val(); 1014 mchp_samples[i] = mchp; 1015 } 1016 1017 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1018 if (kthread_should_stop()) 1019 break; 1020 } 1021 1022 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples); 1023 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples); 1024 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples); 1025 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples); 1026 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples); 1027 ips->mch_avg_power = calc_avg_power(ips, mchp_samples); 1028 kfree(mcp_samples); 1029 kfree(ctv1_samples); 1030 kfree(ctv2_samples); 1031 kfree(mch_samples); 1032 kfree(cpu_samples); 1033 kfree(mchp_samples); 1034 1035 /* Start the adjustment thread now that we have data */ 1036 wake_up_process(ips->adjust); 1037 1038 /* 1039 * Ok, now we have an initial avg. From here on out, we track the 1040 * running avg using a decaying average calculation. This allows 1041 * us to reduce the sample frequency if the CPU and GPU are idle. 1042 */ 1043 old_cpu_power = thm_readl(THM_CEC); 1044 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1045 last_sample_period = IPS_SAMPLE_PERIOD; 1046 1047 setup_deferrable_timer_on_stack(&timer, monitor_timeout, 1048 (unsigned long)current); 1049 do { 1050 u32 cpu_val, mch_val; 1051 u16 val; 1052 1053 /* MCP itself */ 1054 val = read_ptv(ips); 1055 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val); 1056 1057 /* Processor 0 */ 1058 val = read_ctv(ips, 0); 1059 ips->ctv1_avg_temp = 1060 update_average_temp(ips->ctv1_avg_temp, val); 1061 /* Power */ 1062 cpu_val = get_cpu_power(ips, &old_cpu_power, 1063 last_sample_period); 1064 ips->cpu_avg_power = 1065 update_average_power(ips->cpu_avg_power, cpu_val); 1066 1067 if (ips->second_cpu) { 1068 /* Processor 1 */ 1069 val = read_ctv(ips, 1); 1070 ips->ctv2_avg_temp = 1071 update_average_temp(ips->ctv2_avg_temp, val); 1072 } 1073 1074 /* MCH */ 1075 val = read_mgtv(ips); 1076 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val); 1077 /* Power */ 1078 if (ips->read_mch_val) { 1079 mch_val = ips->read_mch_val(); 1080 ips->mch_avg_power = 1081 update_average_power(ips->mch_avg_power, 1082 mch_val); 1083 } 1084 1085 /* 1086 * Make sure ME is updating thermal regs. 1087 * Note: 1088 * If it's been more than a second since the last update, 1089 * the ME is probably hung. 1090 */ 1091 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 1092 ITV_ME_SEQNO_SHIFT; 1093 if (cur_seqno == last_seqno && 1094 time_after(jiffies, seqno_timestamp + HZ)) { 1095 dev_warn(ips->dev, 1096 "ME failed to update for more than 1s, likely hung\n"); 1097 } else { 1098 seqno_timestamp = get_jiffies_64(); 1099 last_seqno = cur_seqno; 1100 } 1101 1102 last_msecs = jiffies_to_msecs(jiffies); 1103 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD); 1104 1105 __set_current_state(TASK_INTERRUPTIBLE); 1106 mod_timer(&timer, expire); 1107 schedule(); 1108 1109 /* Calculate actual sample period for power averaging */ 1110 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs; 1111 if (!last_sample_period) 1112 last_sample_period = 1; 1113 } while (!kthread_should_stop()); 1114 1115 del_timer_sync(&timer); 1116 destroy_timer_on_stack(&timer); 1117 1118 dev_dbg(ips->dev, "ips-monitor thread stopped\n"); 1119 1120 return 0; 1121 } 1122 1123 #if 0 1124 #define THM_DUMPW(reg) \ 1125 { \ 1126 u16 val = thm_readw(reg); \ 1127 dev_dbg(ips->dev, #reg ": 0x%04x\n", val); \ 1128 } 1129 #define THM_DUMPL(reg) \ 1130 { \ 1131 u32 val = thm_readl(reg); \ 1132 dev_dbg(ips->dev, #reg ": 0x%08x\n", val); \ 1133 } 1134 #define THM_DUMPQ(reg) \ 1135 { \ 1136 u64 val = thm_readq(reg); \ 1137 dev_dbg(ips->dev, #reg ": 0x%016x\n", val); \ 1138 } 1139 1140 static void dump_thermal_info(struct ips_driver *ips) 1141 { 1142 u16 ptl; 1143 1144 ptl = thm_readw(THM_PTL); 1145 dev_dbg(ips->dev, "Processor temp limit: %d\n", ptl); 1146 1147 THM_DUMPW(THM_CTA); 1148 THM_DUMPW(THM_TRC); 1149 THM_DUMPW(THM_CTV1); 1150 THM_DUMPL(THM_STS); 1151 THM_DUMPW(THM_PTV); 1152 THM_DUMPQ(THM_MGTV); 1153 } 1154 #endif 1155 1156 /** 1157 * ips_irq_handler - handle temperature triggers and other IPS events 1158 * @irq: irq number 1159 * @arg: unused 1160 * 1161 * Handle temperature limit trigger events, generally by lowering the clamps. 1162 * If we're at a critical limit, we clamp back to the lowest possible value 1163 * to prevent emergency shutdown. 1164 */ 1165 static irqreturn_t ips_irq_handler(int irq, void *arg) 1166 { 1167 struct ips_driver *ips = arg; 1168 u8 tses = thm_readb(THM_TSES); 1169 u8 tes = thm_readb(THM_TES); 1170 1171 if (!tses && !tes) 1172 return IRQ_NONE; 1173 1174 dev_info(ips->dev, "TSES: 0x%02x\n", tses); 1175 dev_info(ips->dev, "TES: 0x%02x\n", tes); 1176 1177 /* STS update from EC? */ 1178 if (tes & 1) { 1179 u32 sts, tc1; 1180 1181 sts = thm_readl(THM_STS); 1182 tc1 = thm_readl(THM_TC1); 1183 1184 if (sts & STS_NVV) { 1185 spin_lock(&ips->turbo_status_lock); 1186 ips->core_power_limit = (sts & STS_PCPL_MASK) >> 1187 STS_PCPL_SHIFT; 1188 ips->mch_power_limit = (sts & STS_GPL_MASK) >> 1189 STS_GPL_SHIFT; 1190 /* ignore EC CPU vs GPU pref */ 1191 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS); 1192 /* 1193 * Disable turbo for now, until we can figure 1194 * out why the power figures are wrong 1195 */ 1196 ips->cpu_turbo_enabled = false; 1197 if (ips->gpu_busy) 1198 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS); 1199 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >> 1200 STS_PTL_SHIFT; 1201 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >> 1202 STS_PPL_SHIFT; 1203 verify_limits(ips); 1204 spin_unlock(&ips->turbo_status_lock); 1205 1206 thm_writeb(THM_SEC, SEC_ACK); 1207 } 1208 thm_writeb(THM_TES, tes); 1209 } 1210 1211 /* Thermal trip */ 1212 if (tses) { 1213 dev_warn(ips->dev, "thermal trip occurred, tses: 0x%04x\n", 1214 tses); 1215 thm_writeb(THM_TSES, tses); 1216 } 1217 1218 return IRQ_HANDLED; 1219 } 1220 1221 #ifndef CONFIG_DEBUG_FS 1222 static void ips_debugfs_init(struct ips_driver *ips) { return; } 1223 static void ips_debugfs_cleanup(struct ips_driver *ips) { return; } 1224 #else 1225 1226 /* Expose current state and limits in debugfs if possible */ 1227 1228 struct ips_debugfs_node { 1229 struct ips_driver *ips; 1230 char *name; 1231 int (*show)(struct seq_file *m, void *data); 1232 }; 1233 1234 static int show_cpu_temp(struct seq_file *m, void *data) 1235 { 1236 struct ips_driver *ips = m->private; 1237 1238 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100, 1239 ips->ctv1_avg_temp % 100); 1240 1241 return 0; 1242 } 1243 1244 static int show_cpu_power(struct seq_file *m, void *data) 1245 { 1246 struct ips_driver *ips = m->private; 1247 1248 seq_printf(m, "%dmW\n", ips->cpu_avg_power); 1249 1250 return 0; 1251 } 1252 1253 static int show_cpu_clamp(struct seq_file *m, void *data) 1254 { 1255 u64 turbo_override; 1256 int tdp, tdc; 1257 1258 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1259 1260 tdp = (int)(turbo_override & TURBO_TDP_MASK); 1261 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); 1262 1263 /* Convert to .1W/A units */ 1264 tdp = tdp * 10 / 8; 1265 tdc = tdc * 10 / 8; 1266 1267 /* Watts Amperes */ 1268 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10, 1269 tdc / 10, tdc % 10); 1270 1271 return 0; 1272 } 1273 1274 static int show_mch_temp(struct seq_file *m, void *data) 1275 { 1276 struct ips_driver *ips = m->private; 1277 1278 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100, 1279 ips->mch_avg_temp % 100); 1280 1281 return 0; 1282 } 1283 1284 static int show_mch_power(struct seq_file *m, void *data) 1285 { 1286 struct ips_driver *ips = m->private; 1287 1288 seq_printf(m, "%dmW\n", ips->mch_avg_power); 1289 1290 return 0; 1291 } 1292 1293 static struct ips_debugfs_node ips_debug_files[] = { 1294 { NULL, "cpu_temp", show_cpu_temp }, 1295 { NULL, "cpu_power", show_cpu_power }, 1296 { NULL, "cpu_clamp", show_cpu_clamp }, 1297 { NULL, "mch_temp", show_mch_temp }, 1298 { NULL, "mch_power", show_mch_power }, 1299 }; 1300 1301 static int ips_debugfs_open(struct inode *inode, struct file *file) 1302 { 1303 struct ips_debugfs_node *node = inode->i_private; 1304 1305 return single_open(file, node->show, node->ips); 1306 } 1307 1308 static const struct file_operations ips_debugfs_ops = { 1309 .owner = THIS_MODULE, 1310 .open = ips_debugfs_open, 1311 .read = seq_read, 1312 .llseek = seq_lseek, 1313 .release = single_release, 1314 }; 1315 1316 static void ips_debugfs_cleanup(struct ips_driver *ips) 1317 { 1318 if (ips->debug_root) 1319 debugfs_remove_recursive(ips->debug_root); 1320 return; 1321 } 1322 1323 static void ips_debugfs_init(struct ips_driver *ips) 1324 { 1325 int i; 1326 1327 ips->debug_root = debugfs_create_dir("ips", NULL); 1328 if (!ips->debug_root) { 1329 dev_err(ips->dev, "failed to create debugfs entries: %ld\n", 1330 PTR_ERR(ips->debug_root)); 1331 return; 1332 } 1333 1334 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) { 1335 struct dentry *ent; 1336 struct ips_debugfs_node *node = &ips_debug_files[i]; 1337 1338 node->ips = ips; 1339 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO, 1340 ips->debug_root, node, 1341 &ips_debugfs_ops); 1342 if (!ent) { 1343 dev_err(ips->dev, "failed to create debug file: %ld\n", 1344 PTR_ERR(ent)); 1345 goto err_cleanup; 1346 } 1347 } 1348 1349 return; 1350 1351 err_cleanup: 1352 ips_debugfs_cleanup(ips); 1353 return; 1354 } 1355 #endif /* CONFIG_DEBUG_FS */ 1356 1357 /** 1358 * ips_detect_cpu - detect whether CPU supports IPS 1359 * 1360 * Walk our list and see if we're on a supported CPU. If we find one, 1361 * return the limits for it. 1362 */ 1363 static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips) 1364 { 1365 u64 turbo_power, misc_en; 1366 struct ips_mcp_limits *limits = NULL; 1367 u16 tdp; 1368 1369 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) { 1370 dev_info(ips->dev, "Non-IPS CPU detected.\n"); 1371 return NULL; 1372 } 1373 1374 rdmsrl(IA32_MISC_ENABLE, misc_en); 1375 /* 1376 * If the turbo enable bit isn't set, we shouldn't try to enable/disable 1377 * turbo manually or we'll get an illegal MSR access, even though 1378 * turbo will still be available. 1379 */ 1380 if (misc_en & IA32_MISC_TURBO_EN) 1381 ips->turbo_toggle_allowed = true; 1382 else 1383 ips->turbo_toggle_allowed = false; 1384 1385 if (strstr(boot_cpu_data.x86_model_id, "CPU M")) 1386 limits = &ips_sv_limits; 1387 else if (strstr(boot_cpu_data.x86_model_id, "CPU L")) 1388 limits = &ips_lv_limits; 1389 else if (strstr(boot_cpu_data.x86_model_id, "CPU U")) 1390 limits = &ips_ulv_limits; 1391 else { 1392 dev_info(ips->dev, "No CPUID match found.\n"); 1393 return NULL; 1394 } 1395 1396 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); 1397 tdp = turbo_power & TURBO_TDP_MASK; 1398 1399 /* Sanity check TDP against CPU */ 1400 if (limits->core_power_limit != (tdp / 8) * 1000) { 1401 dev_info(ips->dev, 1402 "CPU TDP doesn't match expected value (found %d, expected %d)\n", 1403 tdp / 8, limits->core_power_limit / 1000); 1404 limits->core_power_limit = (tdp / 8) * 1000; 1405 } 1406 1407 return limits; 1408 } 1409 1410 /** 1411 * ips_get_i915_syms - try to get GPU control methods from i915 driver 1412 * @ips: IPS driver 1413 * 1414 * The i915 driver exports several interfaces to allow the IPS driver to 1415 * monitor and control graphics turbo mode. If we can find them, we can 1416 * enable graphics turbo, otherwise we must disable it to avoid exceeding 1417 * thermal and power limits in the MCP. 1418 */ 1419 static bool ips_get_i915_syms(struct ips_driver *ips) 1420 { 1421 ips->read_mch_val = symbol_get(i915_read_mch_val); 1422 if (!ips->read_mch_val) 1423 goto out_err; 1424 ips->gpu_raise = symbol_get(i915_gpu_raise); 1425 if (!ips->gpu_raise) 1426 goto out_put_mch; 1427 ips->gpu_lower = symbol_get(i915_gpu_lower); 1428 if (!ips->gpu_lower) 1429 goto out_put_raise; 1430 ips->gpu_busy = symbol_get(i915_gpu_busy); 1431 if (!ips->gpu_busy) 1432 goto out_put_lower; 1433 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable); 1434 if (!ips->gpu_turbo_disable) 1435 goto out_put_busy; 1436 1437 return true; 1438 1439 out_put_busy: 1440 symbol_put(i915_gpu_busy); 1441 out_put_lower: 1442 symbol_put(i915_gpu_lower); 1443 out_put_raise: 1444 symbol_put(i915_gpu_raise); 1445 out_put_mch: 1446 symbol_put(i915_read_mch_val); 1447 out_err: 1448 return false; 1449 } 1450 1451 static bool 1452 ips_gpu_turbo_enabled(struct ips_driver *ips) 1453 { 1454 if (!ips->gpu_busy && late_i915_load) { 1455 if (ips_get_i915_syms(ips)) { 1456 dev_info(ips->dev, 1457 "i915 driver attached, reenabling gpu turbo\n"); 1458 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS); 1459 } 1460 } 1461 1462 return ips->gpu_turbo_enabled; 1463 } 1464 1465 void 1466 ips_link_to_i915_driver(void) 1467 { 1468 /* We can't cleanly get at the various ips_driver structs from 1469 * this caller (the i915 driver), so just set a flag saying 1470 * that it's time to try getting the symbols again. 1471 */ 1472 late_i915_load = true; 1473 } 1474 EXPORT_SYMBOL_GPL(ips_link_to_i915_driver); 1475 1476 static const struct pci_device_id ips_id_table[] = { 1477 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), }, 1478 { 0, } 1479 }; 1480 1481 MODULE_DEVICE_TABLE(pci, ips_id_table); 1482 1483 static int ips_blacklist_callback(const struct dmi_system_id *id) 1484 { 1485 pr_info("Blacklisted intel_ips for %s\n", id->ident); 1486 return 1; 1487 } 1488 1489 static const struct dmi_system_id ips_blacklist[] = { 1490 { 1491 .callback = ips_blacklist_callback, 1492 .ident = "HP ProBook", 1493 .matches = { 1494 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1495 DMI_MATCH(DMI_PRODUCT_NAME, "HP ProBook"), 1496 }, 1497 }, 1498 { } /* terminating entry */ 1499 }; 1500 1501 static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id) 1502 { 1503 u64 platform_info; 1504 struct ips_driver *ips; 1505 u32 hts; 1506 int ret = 0; 1507 u16 htshi, trc, trc_required_mask; 1508 u8 tse; 1509 1510 if (dmi_check_system(ips_blacklist)) 1511 return -ENODEV; 1512 1513 ips = devm_kzalloc(&dev->dev, sizeof(*ips), GFP_KERNEL); 1514 if (!ips) 1515 return -ENOMEM; 1516 1517 spin_lock_init(&ips->turbo_status_lock); 1518 ips->dev = &dev->dev; 1519 1520 ips->limits = ips_detect_cpu(ips); 1521 if (!ips->limits) { 1522 dev_info(&dev->dev, "IPS not supported on this CPU\n"); 1523 return -ENXIO; 1524 } 1525 1526 ret = pcim_enable_device(dev); 1527 if (ret) { 1528 dev_err(&dev->dev, "can't enable PCI device, aborting\n"); 1529 return ret; 1530 } 1531 1532 ret = pcim_iomap_regions(dev, 1 << 0, pci_name(dev)); 1533 if (ret) { 1534 dev_err(&dev->dev, "failed to map thermal regs, aborting\n"); 1535 return ret; 1536 } 1537 ips->regmap = pcim_iomap_table(dev)[0]; 1538 1539 pci_set_drvdata(dev, ips); 1540 1541 tse = thm_readb(THM_TSE); 1542 if (tse != TSE_EN) { 1543 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse); 1544 return -ENXIO; 1545 } 1546 1547 trc = thm_readw(THM_TRC); 1548 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN; 1549 if ((trc & trc_required_mask) != trc_required_mask) { 1550 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n"); 1551 return -ENXIO; 1552 } 1553 1554 if (trc & TRC_CORE2_EN) 1555 ips->second_cpu = true; 1556 1557 update_turbo_limits(ips); 1558 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n", 1559 ips->mcp_power_limit / 10); 1560 dev_dbg(&dev->dev, "max core power clamp: %dW\n", 1561 ips->core_power_limit / 10); 1562 /* BIOS may update limits at runtime */ 1563 if (thm_readl(THM_PSC) & PSP_PBRT) 1564 ips->poll_turbo_status = true; 1565 1566 if (!ips_get_i915_syms(ips)) { 1567 dev_info(&dev->dev, "failed to get i915 symbols, graphics turbo disabled until i915 loads\n"); 1568 ips->gpu_turbo_enabled = false; 1569 } else { 1570 dev_dbg(&dev->dev, "graphics turbo enabled\n"); 1571 ips->gpu_turbo_enabled = true; 1572 } 1573 1574 /* 1575 * Check PLATFORM_INFO MSR to make sure this chip is 1576 * turbo capable. 1577 */ 1578 rdmsrl(PLATFORM_INFO, platform_info); 1579 if (!(platform_info & PLATFORM_TDP)) { 1580 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n"); 1581 return -ENODEV; 1582 } 1583 1584 /* 1585 * IRQ handler for ME interaction 1586 * Note: don't use MSI here as the PCH has bugs. 1587 */ 1588 ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 1589 if (ret < 0) 1590 return ret; 1591 1592 ips->irq = pci_irq_vector(dev, 0); 1593 1594 ret = request_irq(ips->irq, ips_irq_handler, IRQF_SHARED, "ips", ips); 1595 if (ret) { 1596 dev_err(&dev->dev, "request irq failed, aborting\n"); 1597 return ret; 1598 } 1599 1600 /* Enable aux, hot & critical interrupts */ 1601 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI | 1602 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI); 1603 thm_writeb(THM_TEN, TEN_UPDATE_EN); 1604 1605 /* Collect adjustment values */ 1606 ips->cta_val = thm_readw(THM_CTA); 1607 ips->pta_val = thm_readw(THM_PTA); 1608 ips->mgta_val = thm_readw(THM_MGTA); 1609 1610 /* Save turbo limits & ratios */ 1611 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1612 1613 ips_disable_cpu_turbo(ips); 1614 ips->cpu_turbo_enabled = false; 1615 1616 /* Create thermal adjust thread */ 1617 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust"); 1618 if (IS_ERR(ips->adjust)) { 1619 dev_err(&dev->dev, 1620 "failed to create thermal adjust thread, aborting\n"); 1621 ret = -ENOMEM; 1622 goto error_free_irq; 1623 1624 } 1625 1626 /* 1627 * Set up the work queue and monitor thread. The monitor thread 1628 * will wake up ips_adjust thread. 1629 */ 1630 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor"); 1631 if (IS_ERR(ips->monitor)) { 1632 dev_err(&dev->dev, 1633 "failed to create thermal monitor thread, aborting\n"); 1634 ret = -ENOMEM; 1635 goto error_thread_cleanup; 1636 } 1637 1638 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) | 1639 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV; 1640 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT; 1641 1642 thm_writew(THM_HTSHI, htshi); 1643 thm_writel(THM_HTS, hts); 1644 1645 ips_debugfs_init(ips); 1646 1647 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n", 1648 ips->mcp_temp_limit); 1649 return ret; 1650 1651 error_thread_cleanup: 1652 kthread_stop(ips->adjust); 1653 error_free_irq: 1654 free_irq(ips->irq, ips); 1655 pci_free_irq_vectors(dev); 1656 return ret; 1657 } 1658 1659 static void ips_remove(struct pci_dev *dev) 1660 { 1661 struct ips_driver *ips = pci_get_drvdata(dev); 1662 u64 turbo_override; 1663 1664 if (!ips) 1665 return; 1666 1667 ips_debugfs_cleanup(ips); 1668 1669 /* Release i915 driver */ 1670 if (ips->read_mch_val) 1671 symbol_put(i915_read_mch_val); 1672 if (ips->gpu_raise) 1673 symbol_put(i915_gpu_raise); 1674 if (ips->gpu_lower) 1675 symbol_put(i915_gpu_lower); 1676 if (ips->gpu_busy) 1677 symbol_put(i915_gpu_busy); 1678 if (ips->gpu_turbo_disable) 1679 symbol_put(i915_gpu_turbo_disable); 1680 1681 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1682 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); 1683 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1684 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1685 1686 free_irq(ips->irq, ips); 1687 pci_free_irq_vectors(dev); 1688 if (ips->adjust) 1689 kthread_stop(ips->adjust); 1690 if (ips->monitor) 1691 kthread_stop(ips->monitor); 1692 dev_dbg(&dev->dev, "IPS driver removed\n"); 1693 } 1694 1695 static struct pci_driver ips_pci_driver = { 1696 .name = "intel ips", 1697 .id_table = ips_id_table, 1698 .probe = ips_probe, 1699 .remove = ips_remove, 1700 }; 1701 1702 module_pci_driver(ips_pci_driver); 1703 1704 MODULE_LICENSE("GPL"); 1705 MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>"); 1706 MODULE_DESCRIPTION("Intelligent Power Sharing Driver"); 1707