1 /* 2 * Copyright (c) 2009-2010 Intel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, write to the Free Software Foundation, Inc., 15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 17 * The full GNU General Public License is included in this distribution in 18 * the file called "COPYING". 19 * 20 * Authors: 21 * Jesse Barnes <jbarnes@virtuousgeek.org> 22 */ 23 24 /* 25 * Some Intel Ibex Peak based platforms support so-called "intelligent 26 * power sharing", which allows the CPU and GPU to cooperate to maximize 27 * performance within a given TDP (thermal design point). This driver 28 * performs the coordination between the CPU and GPU, monitors thermal and 29 * power statistics in the platform, and initializes power monitoring 30 * hardware. It also provides a few tunables to control behavior. Its 31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled 32 * by tracking power and thermal budget; secondarily it can boost turbo 33 * performance by allocating more power or thermal budget to the CPU or GPU 34 * based on available headroom and activity. 35 * 36 * The basic algorithm is driven by a 5s moving average of tempurature. If 37 * thermal headroom is available, the CPU and/or GPU power clamps may be 38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger, 39 * we scale back the clamp. Aside from trigger events (when we're critically 40 * close or over our TDP) we don't adjust the clamps more than once every 41 * five seconds. 42 * 43 * The thermal device (device 31, function 6) has a set of registers that 44 * are updated by the ME firmware. The ME should also take the clamp values 45 * written to those registers and write them to the CPU, but we currently 46 * bypass that functionality and write the CPU MSR directly. 47 * 48 * UNSUPPORTED: 49 * - dual MCP configs 50 * 51 * TODO: 52 * - handle CPU hotplug 53 * - provide turbo enable/disable api 54 * 55 * Related documents: 56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2 57 * - CDI 401376 - Ibex Peak EDS 58 * - ref 26037, 26641 - IPS BIOS spec 59 * - ref 26489 - Nehalem BIOS writer's guide 60 * - ref 26921 - Ibex Peak BIOS Specification 61 */ 62 63 #include <linux/debugfs.h> 64 #include <linux/delay.h> 65 #include <linux/interrupt.h> 66 #include <linux/kernel.h> 67 #include <linux/kthread.h> 68 #include <linux/module.h> 69 #include <linux/pci.h> 70 #include <linux/sched.h> 71 #include <linux/seq_file.h> 72 #include <linux/string.h> 73 #include <linux/tick.h> 74 #include <linux/timer.h> 75 #include <drm/i915_drm.h> 76 #include <asm/msr.h> 77 #include <asm/processor.h> 78 #include "intel_ips.h" 79 80 #include <asm-generic/io-64-nonatomic-lo-hi.h> 81 82 #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32 83 84 /* 85 * Package level MSRs for monitor/control 86 */ 87 #define PLATFORM_INFO 0xce 88 #define PLATFORM_TDP (1<<29) 89 #define PLATFORM_RATIO (1<<28) 90 91 #define IA32_MISC_ENABLE 0x1a0 92 #define IA32_MISC_TURBO_EN (1ULL<<38) 93 94 #define TURBO_POWER_CURRENT_LIMIT 0x1ac 95 #define TURBO_TDC_OVR_EN (1UL<<31) 96 #define TURBO_TDC_MASK (0x000000007fff0000UL) 97 #define TURBO_TDC_SHIFT (16) 98 #define TURBO_TDP_OVR_EN (1UL<<15) 99 #define TURBO_TDP_MASK (0x0000000000003fffUL) 100 101 /* 102 * Core/thread MSRs for monitoring 103 */ 104 #define IA32_PERF_CTL 0x199 105 #define IA32_PERF_TURBO_DIS (1ULL<<32) 106 107 /* 108 * Thermal PCI device regs 109 */ 110 #define THM_CFG_TBAR 0x10 111 #define THM_CFG_TBAR_HI 0x14 112 113 #define THM_TSIU 0x00 114 #define THM_TSE 0x01 115 #define TSE_EN 0xb8 116 #define THM_TSS 0x02 117 #define THM_TSTR 0x03 118 #define THM_TSTTP 0x04 119 #define THM_TSCO 0x08 120 #define THM_TSES 0x0c 121 #define THM_TSGPEN 0x0d 122 #define TSGPEN_HOT_LOHI (1<<1) 123 #define TSGPEN_CRIT_LOHI (1<<2) 124 #define THM_TSPC 0x0e 125 #define THM_PPEC 0x10 126 #define THM_CTA 0x12 127 #define THM_PTA 0x14 128 #define PTA_SLOPE_MASK (0xff00) 129 #define PTA_SLOPE_SHIFT 8 130 #define PTA_OFFSET_MASK (0x00ff) 131 #define THM_MGTA 0x16 132 #define MGTA_SLOPE_MASK (0xff00) 133 #define MGTA_SLOPE_SHIFT 8 134 #define MGTA_OFFSET_MASK (0x00ff) 135 #define THM_TRC 0x1a 136 #define TRC_CORE2_EN (1<<15) 137 #define TRC_THM_EN (1<<12) 138 #define TRC_C6_WAR (1<<8) 139 #define TRC_CORE1_EN (1<<7) 140 #define TRC_CORE_PWR (1<<6) 141 #define TRC_PCH_EN (1<<5) 142 #define TRC_MCH_EN (1<<4) 143 #define TRC_DIMM4 (1<<3) 144 #define TRC_DIMM3 (1<<2) 145 #define TRC_DIMM2 (1<<1) 146 #define TRC_DIMM1 (1<<0) 147 #define THM_TES 0x20 148 #define THM_TEN 0x21 149 #define TEN_UPDATE_EN 1 150 #define THM_PSC 0x24 151 #define PSC_NTG (1<<0) /* No GFX turbo support */ 152 #define PSC_NTPC (1<<1) /* No CPU turbo support */ 153 #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */ 154 #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */ 155 #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */ 156 #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */ 157 #define PSP_PBRT (1<<4) /* BIOS run time support */ 158 #define THM_CTV1 0x30 159 #define CTV_TEMP_ERROR (1<<15) 160 #define CTV_TEMP_MASK 0x3f 161 #define CTV_ 162 #define THM_CTV2 0x32 163 #define THM_CEC 0x34 /* undocumented power accumulator in joules */ 164 #define THM_AE 0x3f 165 #define THM_HTS 0x50 /* 32 bits */ 166 #define HTS_PCPL_MASK (0x7fe00000) 167 #define HTS_PCPL_SHIFT 21 168 #define HTS_GPL_MASK (0x001ff000) 169 #define HTS_GPL_SHIFT 12 170 #define HTS_PP_MASK (0x00000c00) 171 #define HTS_PP_SHIFT 10 172 #define HTS_PP_DEF 0 173 #define HTS_PP_PROC 1 174 #define HTS_PP_BAL 2 175 #define HTS_PP_GFX 3 176 #define HTS_PCTD_DIS (1<<9) 177 #define HTS_GTD_DIS (1<<8) 178 #define HTS_PTL_MASK (0x000000fe) 179 #define HTS_PTL_SHIFT 1 180 #define HTS_NVV (1<<0) 181 #define THM_HTSHI 0x54 /* 16 bits */ 182 #define HTS2_PPL_MASK (0x03ff) 183 #define HTS2_PRST_MASK (0x3c00) 184 #define HTS2_PRST_SHIFT 10 185 #define HTS2_PRST_UNLOADED 0 186 #define HTS2_PRST_RUNNING 1 187 #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */ 188 #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */ 189 #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */ 190 #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */ 191 #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */ 192 #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */ 193 #define THM_PTL 0x56 194 #define THM_MGTV 0x58 195 #define TV_MASK 0x000000000000ff00 196 #define TV_SHIFT 8 197 #define THM_PTV 0x60 198 #define PTV_MASK 0x00ff 199 #define THM_MMGPC 0x64 200 #define THM_MPPC 0x66 201 #define THM_MPCPC 0x68 202 #define THM_TSPIEN 0x82 203 #define TSPIEN_AUX_LOHI (1<<0) 204 #define TSPIEN_HOT_LOHI (1<<1) 205 #define TSPIEN_CRIT_LOHI (1<<2) 206 #define TSPIEN_AUX2_LOHI (1<<3) 207 #define THM_TSLOCK 0x83 208 #define THM_ATR 0x84 209 #define THM_TOF 0x87 210 #define THM_STS 0x98 211 #define STS_PCPL_MASK (0x7fe00000) 212 #define STS_PCPL_SHIFT 21 213 #define STS_GPL_MASK (0x001ff000) 214 #define STS_GPL_SHIFT 12 215 #define STS_PP_MASK (0x00000c00) 216 #define STS_PP_SHIFT 10 217 #define STS_PP_DEF 0 218 #define STS_PP_PROC 1 219 #define STS_PP_BAL 2 220 #define STS_PP_GFX 3 221 #define STS_PCTD_DIS (1<<9) 222 #define STS_GTD_DIS (1<<8) 223 #define STS_PTL_MASK (0x000000fe) 224 #define STS_PTL_SHIFT 1 225 #define STS_NVV (1<<0) 226 #define THM_SEC 0x9c 227 #define SEC_ACK (1<<0) 228 #define THM_TC3 0xa4 229 #define THM_TC1 0xa8 230 #define STS_PPL_MASK (0x0003ff00) 231 #define STS_PPL_SHIFT 16 232 #define THM_TC2 0xac 233 #define THM_DTV 0xb0 234 #define THM_ITV 0xd8 235 #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */ 236 #define ITV_ME_SEQNO_SHIFT (16) 237 #define ITV_MCH_TEMP_MASK 0x0000ff00 238 #define ITV_MCH_TEMP_SHIFT (8) 239 #define ITV_PCH_TEMP_MASK 0x000000ff 240 241 #define thm_readb(off) readb(ips->regmap + (off)) 242 #define thm_readw(off) readw(ips->regmap + (off)) 243 #define thm_readl(off) readl(ips->regmap + (off)) 244 #define thm_readq(off) readq(ips->regmap + (off)) 245 246 #define thm_writeb(off, val) writeb((val), ips->regmap + (off)) 247 #define thm_writew(off, val) writew((val), ips->regmap + (off)) 248 #define thm_writel(off, val) writel((val), ips->regmap + (off)) 249 250 static const int IPS_ADJUST_PERIOD = 5000; /* ms */ 251 static bool late_i915_load = false; 252 253 /* For initial average collection */ 254 static const int IPS_SAMPLE_PERIOD = 200; /* ms */ 255 static const int IPS_SAMPLE_WINDOW = 5000; /* 5s moving window of samples */ 256 #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD) 257 258 /* Per-SKU limits */ 259 struct ips_mcp_limits { 260 int cpu_family; 261 int cpu_model; /* includes extended model... */ 262 int mcp_power_limit; /* mW units */ 263 int core_power_limit; 264 int mch_power_limit; 265 int core_temp_limit; /* degrees C */ 266 int mch_temp_limit; 267 }; 268 269 /* Max temps are -10 degrees C to avoid PROCHOT# */ 270 271 struct ips_mcp_limits ips_sv_limits = { 272 .mcp_power_limit = 35000, 273 .core_power_limit = 29000, 274 .mch_power_limit = 20000, 275 .core_temp_limit = 95, 276 .mch_temp_limit = 90 277 }; 278 279 struct ips_mcp_limits ips_lv_limits = { 280 .mcp_power_limit = 25000, 281 .core_power_limit = 21000, 282 .mch_power_limit = 13000, 283 .core_temp_limit = 95, 284 .mch_temp_limit = 90 285 }; 286 287 struct ips_mcp_limits ips_ulv_limits = { 288 .mcp_power_limit = 18000, 289 .core_power_limit = 14000, 290 .mch_power_limit = 11000, 291 .core_temp_limit = 95, 292 .mch_temp_limit = 90 293 }; 294 295 struct ips_driver { 296 struct pci_dev *dev; 297 void *regmap; 298 struct task_struct *monitor; 299 struct task_struct *adjust; 300 struct dentry *debug_root; 301 302 /* Average CPU core temps (all averages in .01 degrees C for precision) */ 303 u16 ctv1_avg_temp; 304 u16 ctv2_avg_temp; 305 /* GMCH average */ 306 u16 mch_avg_temp; 307 /* Average for the CPU (both cores?) */ 308 u16 mcp_avg_temp; 309 /* Average power consumption (in mW) */ 310 u32 cpu_avg_power; 311 u32 mch_avg_power; 312 313 /* Offset values */ 314 u16 cta_val; 315 u16 pta_val; 316 u16 mgta_val; 317 318 /* Maximums & prefs, protected by turbo status lock */ 319 spinlock_t turbo_status_lock; 320 u16 mcp_temp_limit; 321 u16 mcp_power_limit; 322 u16 core_power_limit; 323 u16 mch_power_limit; 324 bool cpu_turbo_enabled; 325 bool __cpu_turbo_on; 326 bool gpu_turbo_enabled; 327 bool __gpu_turbo_on; 328 bool gpu_preferred; 329 bool poll_turbo_status; 330 bool second_cpu; 331 bool turbo_toggle_allowed; 332 struct ips_mcp_limits *limits; 333 334 /* Optional MCH interfaces for if i915 is in use */ 335 unsigned long (*read_mch_val)(void); 336 bool (*gpu_raise)(void); 337 bool (*gpu_lower)(void); 338 bool (*gpu_busy)(void); 339 bool (*gpu_turbo_disable)(void); 340 341 /* For restoration at unload */ 342 u64 orig_turbo_limit; 343 u64 orig_turbo_ratios; 344 }; 345 346 static bool 347 ips_gpu_turbo_enabled(struct ips_driver *ips); 348 349 /** 350 * ips_cpu_busy - is CPU busy? 351 * @ips: IPS driver struct 352 * 353 * Check CPU for load to see whether we should increase its thermal budget. 354 * 355 * RETURNS: 356 * True if the CPU could use more power, false otherwise. 357 */ 358 static bool ips_cpu_busy(struct ips_driver *ips) 359 { 360 if ((avenrun[0] >> FSHIFT) > 1) 361 return true; 362 363 return false; 364 } 365 366 /** 367 * ips_cpu_raise - raise CPU power clamp 368 * @ips: IPS driver struct 369 * 370 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for 371 * this platform. 372 * 373 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as 374 * long as we haven't hit the TDP limit for the SKU). 375 */ 376 static void ips_cpu_raise(struct ips_driver *ips) 377 { 378 u64 turbo_override; 379 u16 cur_tdp_limit, new_tdp_limit; 380 381 if (!ips->cpu_turbo_enabled) 382 return; 383 384 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 385 386 cur_tdp_limit = turbo_override & TURBO_TDP_MASK; 387 new_tdp_limit = cur_tdp_limit + 8; /* 1W increase */ 388 389 /* Clamp to SKU TDP limit */ 390 if (((new_tdp_limit * 10) / 8) > ips->core_power_limit) 391 new_tdp_limit = cur_tdp_limit; 392 393 thm_writew(THM_MPCPC, (new_tdp_limit * 10) / 8); 394 395 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 396 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 397 398 turbo_override &= ~TURBO_TDP_MASK; 399 turbo_override |= new_tdp_limit; 400 401 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 402 } 403 404 /** 405 * ips_cpu_lower - lower CPU power clamp 406 * @ips: IPS driver struct 407 * 408 * Lower CPU power clamp b %IPS_CPU_STEP if possible. 409 * 410 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going 411 * as low as the platform limits will allow (though we could go lower there 412 * wouldn't be much point). 413 */ 414 static void ips_cpu_lower(struct ips_driver *ips) 415 { 416 u64 turbo_override; 417 u16 cur_limit, new_limit; 418 419 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 420 421 cur_limit = turbo_override & TURBO_TDP_MASK; 422 new_limit = cur_limit - 8; /* 1W decrease */ 423 424 /* Clamp to SKU TDP limit */ 425 if (new_limit < (ips->orig_turbo_limit & TURBO_TDP_MASK)) 426 new_limit = ips->orig_turbo_limit & TURBO_TDP_MASK; 427 428 thm_writew(THM_MPCPC, (new_limit * 10) / 8); 429 430 turbo_override |= TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN; 431 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 432 433 turbo_override &= ~TURBO_TDP_MASK; 434 turbo_override |= new_limit; 435 436 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 437 } 438 439 /** 440 * do_enable_cpu_turbo - internal turbo enable function 441 * @data: unused 442 * 443 * Internal function for actually updating MSRs. When we enable/disable 444 * turbo, we need to do it on each CPU; this function is the one called 445 * by on_each_cpu() when needed. 446 */ 447 static void do_enable_cpu_turbo(void *data) 448 { 449 u64 perf_ctl; 450 451 rdmsrl(IA32_PERF_CTL, perf_ctl); 452 if (perf_ctl & IA32_PERF_TURBO_DIS) { 453 perf_ctl &= ~IA32_PERF_TURBO_DIS; 454 wrmsrl(IA32_PERF_CTL, perf_ctl); 455 } 456 } 457 458 /** 459 * ips_enable_cpu_turbo - enable turbo mode on all CPUs 460 * @ips: IPS driver struct 461 * 462 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on 463 * all logical threads. 464 */ 465 static void ips_enable_cpu_turbo(struct ips_driver *ips) 466 { 467 /* Already on, no need to mess with MSRs */ 468 if (ips->__cpu_turbo_on) 469 return; 470 471 if (ips->turbo_toggle_allowed) 472 on_each_cpu(do_enable_cpu_turbo, ips, 1); 473 474 ips->__cpu_turbo_on = true; 475 } 476 477 /** 478 * do_disable_cpu_turbo - internal turbo disable function 479 * @data: unused 480 * 481 * Internal function for actually updating MSRs. When we enable/disable 482 * turbo, we need to do it on each CPU; this function is the one called 483 * by on_each_cpu() when needed. 484 */ 485 static void do_disable_cpu_turbo(void *data) 486 { 487 u64 perf_ctl; 488 489 rdmsrl(IA32_PERF_CTL, perf_ctl); 490 if (!(perf_ctl & IA32_PERF_TURBO_DIS)) { 491 perf_ctl |= IA32_PERF_TURBO_DIS; 492 wrmsrl(IA32_PERF_CTL, perf_ctl); 493 } 494 } 495 496 /** 497 * ips_disable_cpu_turbo - disable turbo mode on all CPUs 498 * @ips: IPS driver struct 499 * 500 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on 501 * all logical threads. 502 */ 503 static void ips_disable_cpu_turbo(struct ips_driver *ips) 504 { 505 /* Already off, leave it */ 506 if (!ips->__cpu_turbo_on) 507 return; 508 509 if (ips->turbo_toggle_allowed) 510 on_each_cpu(do_disable_cpu_turbo, ips, 1); 511 512 ips->__cpu_turbo_on = false; 513 } 514 515 /** 516 * ips_gpu_busy - is GPU busy? 517 * @ips: IPS driver struct 518 * 519 * Check GPU for load to see whether we should increase its thermal budget. 520 * We need to call into the i915 driver in this case. 521 * 522 * RETURNS: 523 * True if the GPU could use more power, false otherwise. 524 */ 525 static bool ips_gpu_busy(struct ips_driver *ips) 526 { 527 if (!ips_gpu_turbo_enabled(ips)) 528 return false; 529 530 return ips->gpu_busy(); 531 } 532 533 /** 534 * ips_gpu_raise - raise GPU power clamp 535 * @ips: IPS driver struct 536 * 537 * Raise the GPU frequency/power if possible. We need to call into the 538 * i915 driver in this case. 539 */ 540 static void ips_gpu_raise(struct ips_driver *ips) 541 { 542 if (!ips_gpu_turbo_enabled(ips)) 543 return; 544 545 if (!ips->gpu_raise()) 546 ips->gpu_turbo_enabled = false; 547 548 return; 549 } 550 551 /** 552 * ips_gpu_lower - lower GPU power clamp 553 * @ips: IPS driver struct 554 * 555 * Lower GPU frequency/power if possible. Need to call i915. 556 */ 557 static void ips_gpu_lower(struct ips_driver *ips) 558 { 559 if (!ips_gpu_turbo_enabled(ips)) 560 return; 561 562 if (!ips->gpu_lower()) 563 ips->gpu_turbo_enabled = false; 564 565 return; 566 } 567 568 /** 569 * ips_enable_gpu_turbo - notify the gfx driver turbo is available 570 * @ips: IPS driver struct 571 * 572 * Call into the graphics driver indicating that it can safely use 573 * turbo mode. 574 */ 575 static void ips_enable_gpu_turbo(struct ips_driver *ips) 576 { 577 if (ips->__gpu_turbo_on) 578 return; 579 ips->__gpu_turbo_on = true; 580 } 581 582 /** 583 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode 584 * @ips: IPS driver struct 585 * 586 * Request that the graphics driver disable turbo mode. 587 */ 588 static void ips_disable_gpu_turbo(struct ips_driver *ips) 589 { 590 /* Avoid calling i915 if turbo is already disabled */ 591 if (!ips->__gpu_turbo_on) 592 return; 593 594 if (!ips->gpu_turbo_disable()) 595 dev_err(&ips->dev->dev, "failed to disable graphis turbo\n"); 596 else 597 ips->__gpu_turbo_on = false; 598 } 599 600 /** 601 * mcp_exceeded - check whether we're outside our thermal & power limits 602 * @ips: IPS driver struct 603 * 604 * Check whether the MCP is over its thermal or power budget. 605 */ 606 static bool mcp_exceeded(struct ips_driver *ips) 607 { 608 unsigned long flags; 609 bool ret = false; 610 u32 temp_limit; 611 u32 avg_power; 612 const char *msg = "MCP limit exceeded: "; 613 614 spin_lock_irqsave(&ips->turbo_status_lock, flags); 615 616 temp_limit = ips->mcp_temp_limit * 100; 617 if (ips->mcp_avg_temp > temp_limit) { 618 dev_info(&ips->dev->dev, 619 "%sAvg temp %u, limit %u\n", msg, ips->mcp_avg_temp, 620 temp_limit); 621 ret = true; 622 } 623 624 avg_power = ips->cpu_avg_power + ips->mch_avg_power; 625 if (avg_power > ips->mcp_power_limit) { 626 dev_info(&ips->dev->dev, 627 "%sAvg power %u, limit %u\n", msg, avg_power, 628 ips->mcp_power_limit); 629 ret = true; 630 } 631 632 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 633 634 return ret; 635 } 636 637 /** 638 * cpu_exceeded - check whether a CPU core is outside its limits 639 * @ips: IPS driver struct 640 * @cpu: CPU number to check 641 * 642 * Check a given CPU's average temp or power is over its limit. 643 */ 644 static bool cpu_exceeded(struct ips_driver *ips, int cpu) 645 { 646 unsigned long flags; 647 int avg; 648 bool ret = false; 649 650 spin_lock_irqsave(&ips->turbo_status_lock, flags); 651 avg = cpu ? ips->ctv2_avg_temp : ips->ctv1_avg_temp; 652 if (avg > (ips->limits->core_temp_limit * 100)) 653 ret = true; 654 if (ips->cpu_avg_power > ips->core_power_limit * 100) 655 ret = true; 656 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 657 658 if (ret) 659 dev_info(&ips->dev->dev, 660 "CPU power or thermal limit exceeded\n"); 661 662 return ret; 663 } 664 665 /** 666 * mch_exceeded - check whether the GPU is over budget 667 * @ips: IPS driver struct 668 * 669 * Check the MCH temp & power against their maximums. 670 */ 671 static bool mch_exceeded(struct ips_driver *ips) 672 { 673 unsigned long flags; 674 bool ret = false; 675 676 spin_lock_irqsave(&ips->turbo_status_lock, flags); 677 if (ips->mch_avg_temp > (ips->limits->mch_temp_limit * 100)) 678 ret = true; 679 if (ips->mch_avg_power > ips->mch_power_limit) 680 ret = true; 681 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 682 683 return ret; 684 } 685 686 /** 687 * verify_limits - verify BIOS provided limits 688 * @ips: IPS structure 689 * 690 * BIOS can optionally provide non-default limits for power and temp. Check 691 * them here and use the defaults if the BIOS values are not provided or 692 * are otherwise unusable. 693 */ 694 static void verify_limits(struct ips_driver *ips) 695 { 696 if (ips->mcp_power_limit < ips->limits->mcp_power_limit || 697 ips->mcp_power_limit > 35000) 698 ips->mcp_power_limit = ips->limits->mcp_power_limit; 699 700 if (ips->mcp_temp_limit < ips->limits->core_temp_limit || 701 ips->mcp_temp_limit < ips->limits->mch_temp_limit || 702 ips->mcp_temp_limit > 150) 703 ips->mcp_temp_limit = min(ips->limits->core_temp_limit, 704 ips->limits->mch_temp_limit); 705 } 706 707 /** 708 * update_turbo_limits - get various limits & settings from regs 709 * @ips: IPS driver struct 710 * 711 * Update the IPS power & temp limits, along with turbo enable flags, 712 * based on latest register contents. 713 * 714 * Used at init time and for runtime BIOS support, which requires polling 715 * the regs for updates (as a result of AC->DC transition for example). 716 * 717 * LOCKING: 718 * Caller must hold turbo_status_lock (outside of init) 719 */ 720 static void update_turbo_limits(struct ips_driver *ips) 721 { 722 u32 hts = thm_readl(THM_HTS); 723 724 ips->cpu_turbo_enabled = !(hts & HTS_PCTD_DIS); 725 /* 726 * Disable turbo for now, until we can figure out why the power figures 727 * are wrong 728 */ 729 ips->cpu_turbo_enabled = false; 730 731 if (ips->gpu_busy) 732 ips->gpu_turbo_enabled = !(hts & HTS_GTD_DIS); 733 734 ips->core_power_limit = thm_readw(THM_MPCPC); 735 ips->mch_power_limit = thm_readw(THM_MMGPC); 736 ips->mcp_temp_limit = thm_readw(THM_PTL); 737 ips->mcp_power_limit = thm_readw(THM_MPPC); 738 739 verify_limits(ips); 740 /* Ignore BIOS CPU vs GPU pref */ 741 } 742 743 /** 744 * ips_adjust - adjust power clamp based on thermal state 745 * @data: ips driver structure 746 * 747 * Wake up every 5s or so and check whether we should adjust the power clamp. 748 * Check CPU and GPU load to determine which needs adjustment. There are 749 * several things to consider here: 750 * - do we need to adjust up or down? 751 * - is CPU busy? 752 * - is GPU busy? 753 * - is CPU in turbo? 754 * - is GPU in turbo? 755 * - is CPU or GPU preferred? (CPU is default) 756 * 757 * So, given the above, we do the following: 758 * - up (TDP available) 759 * - CPU not busy, GPU not busy - nothing 760 * - CPU busy, GPU not busy - adjust CPU up 761 * - CPU not busy, GPU busy - adjust GPU up 762 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from 763 * non-preferred unit if necessary 764 * - down (at TDP limit) 765 * - adjust both CPU and GPU down if possible 766 * 767 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu- 768 cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing 769 cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu- 770 cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu- 771 cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu- 772 * 773 */ 774 static int ips_adjust(void *data) 775 { 776 struct ips_driver *ips = data; 777 unsigned long flags; 778 779 dev_dbg(&ips->dev->dev, "starting ips-adjust thread\n"); 780 781 /* 782 * Adjust CPU and GPU clamps every 5s if needed. Doing it more 783 * often isn't recommended due to ME interaction. 784 */ 785 do { 786 bool cpu_busy = ips_cpu_busy(ips); 787 bool gpu_busy = ips_gpu_busy(ips); 788 789 spin_lock_irqsave(&ips->turbo_status_lock, flags); 790 if (ips->poll_turbo_status) 791 update_turbo_limits(ips); 792 spin_unlock_irqrestore(&ips->turbo_status_lock, flags); 793 794 /* Update turbo status if necessary */ 795 if (ips->cpu_turbo_enabled) 796 ips_enable_cpu_turbo(ips); 797 else 798 ips_disable_cpu_turbo(ips); 799 800 if (ips->gpu_turbo_enabled) 801 ips_enable_gpu_turbo(ips); 802 else 803 ips_disable_gpu_turbo(ips); 804 805 /* We're outside our comfort zone, crank them down */ 806 if (mcp_exceeded(ips)) { 807 ips_cpu_lower(ips); 808 ips_gpu_lower(ips); 809 goto sleep; 810 } 811 812 if (!cpu_exceeded(ips, 0) && cpu_busy) 813 ips_cpu_raise(ips); 814 else 815 ips_cpu_lower(ips); 816 817 if (!mch_exceeded(ips) && gpu_busy) 818 ips_gpu_raise(ips); 819 else 820 ips_gpu_lower(ips); 821 822 sleep: 823 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD)); 824 } while (!kthread_should_stop()); 825 826 dev_dbg(&ips->dev->dev, "ips-adjust thread stopped\n"); 827 828 return 0; 829 } 830 831 /* 832 * Helpers for reading out temp/power values and calculating their 833 * averages for the decision making and monitoring functions. 834 */ 835 836 static u16 calc_avg_temp(struct ips_driver *ips, u16 *array) 837 { 838 u64 total = 0; 839 int i; 840 u16 avg; 841 842 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 843 total += (u64)(array[i] * 100); 844 845 do_div(total, IPS_SAMPLE_COUNT); 846 847 avg = (u16)total; 848 849 return avg; 850 } 851 852 static u16 read_mgtv(struct ips_driver *ips) 853 { 854 u16 ret; 855 u64 slope, offset; 856 u64 val; 857 858 val = thm_readq(THM_MGTV); 859 val = (val & TV_MASK) >> TV_SHIFT; 860 861 slope = offset = thm_readw(THM_MGTA); 862 slope = (slope & MGTA_SLOPE_MASK) >> MGTA_SLOPE_SHIFT; 863 offset = offset & MGTA_OFFSET_MASK; 864 865 ret = ((val * slope + 0x40) >> 7) + offset; 866 867 return 0; /* MCH temp reporting buggy */ 868 } 869 870 static u16 read_ptv(struct ips_driver *ips) 871 { 872 u16 val, slope, offset; 873 874 slope = (ips->pta_val & PTA_SLOPE_MASK) >> PTA_SLOPE_SHIFT; 875 offset = ips->pta_val & PTA_OFFSET_MASK; 876 877 val = thm_readw(THM_PTV) & PTV_MASK; 878 879 return val; 880 } 881 882 static u16 read_ctv(struct ips_driver *ips, int cpu) 883 { 884 int reg = cpu ? THM_CTV2 : THM_CTV1; 885 u16 val; 886 887 val = thm_readw(reg); 888 if (!(val & CTV_TEMP_ERROR)) 889 val = (val) >> 6; /* discard fractional component */ 890 else 891 val = 0; 892 893 return val; 894 } 895 896 static u32 get_cpu_power(struct ips_driver *ips, u32 *last, int period) 897 { 898 u32 val; 899 u32 ret; 900 901 /* 902 * CEC is in joules/65535. Take difference over time to 903 * get watts. 904 */ 905 val = thm_readl(THM_CEC); 906 907 /* period is in ms and we want mW */ 908 ret = (((val - *last) * 1000) / period); 909 ret = (ret * 1000) / 65535; 910 *last = val; 911 912 return 0; 913 } 914 915 static const u16 temp_decay_factor = 2; 916 static u16 update_average_temp(u16 avg, u16 val) 917 { 918 u16 ret; 919 920 /* Multiply by 100 for extra precision */ 921 ret = (val * 100 / temp_decay_factor) + 922 (((temp_decay_factor - 1) * avg) / temp_decay_factor); 923 return ret; 924 } 925 926 static const u16 power_decay_factor = 2; 927 static u16 update_average_power(u32 avg, u32 val) 928 { 929 u32 ret; 930 931 ret = (val / power_decay_factor) + 932 (((power_decay_factor - 1) * avg) / power_decay_factor); 933 934 return ret; 935 } 936 937 static u32 calc_avg_power(struct ips_driver *ips, u32 *array) 938 { 939 u64 total = 0; 940 u32 avg; 941 int i; 942 943 for (i = 0; i < IPS_SAMPLE_COUNT; i++) 944 total += array[i]; 945 946 do_div(total, IPS_SAMPLE_COUNT); 947 avg = (u32)total; 948 949 return avg; 950 } 951 952 static void monitor_timeout(unsigned long arg) 953 { 954 wake_up_process((struct task_struct *)arg); 955 } 956 957 /** 958 * ips_monitor - temp/power monitoring thread 959 * @data: ips driver structure 960 * 961 * This is the main function for the IPS driver. It monitors power and 962 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly. 963 * 964 * We keep a 5s moving average of power consumption and tempurature. Using 965 * that data, along with CPU vs GPU preference, we adjust the power clamps 966 * up or down. 967 */ 968 static int ips_monitor(void *data) 969 { 970 struct ips_driver *ips = data; 971 struct timer_list timer; 972 unsigned long seqno_timestamp, expire, last_msecs, last_sample_period; 973 int i; 974 u32 *cpu_samples, *mchp_samples, old_cpu_power; 975 u16 *mcp_samples, *ctv1_samples, *ctv2_samples, *mch_samples; 976 u8 cur_seqno, last_seqno; 977 978 mcp_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 979 ctv1_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 980 ctv2_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 981 mch_samples = kzalloc(sizeof(u16) * IPS_SAMPLE_COUNT, GFP_KERNEL); 982 cpu_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 983 mchp_samples = kzalloc(sizeof(u32) * IPS_SAMPLE_COUNT, GFP_KERNEL); 984 if (!mcp_samples || !ctv1_samples || !ctv2_samples || !mch_samples || 985 !cpu_samples || !mchp_samples) { 986 dev_err(&ips->dev->dev, 987 "failed to allocate sample array, ips disabled\n"); 988 kfree(mcp_samples); 989 kfree(ctv1_samples); 990 kfree(ctv2_samples); 991 kfree(mch_samples); 992 kfree(cpu_samples); 993 kfree(mchp_samples); 994 return -ENOMEM; 995 } 996 997 last_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 998 ITV_ME_SEQNO_SHIFT; 999 seqno_timestamp = get_jiffies_64(); 1000 1001 old_cpu_power = thm_readl(THM_CEC); 1002 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1003 1004 /* Collect an initial average */ 1005 for (i = 0; i < IPS_SAMPLE_COUNT; i++) { 1006 u32 mchp, cpu_power; 1007 u16 val; 1008 1009 mcp_samples[i] = read_ptv(ips); 1010 1011 val = read_ctv(ips, 0); 1012 ctv1_samples[i] = val; 1013 1014 val = read_ctv(ips, 1); 1015 ctv2_samples[i] = val; 1016 1017 val = read_mgtv(ips); 1018 mch_samples[i] = val; 1019 1020 cpu_power = get_cpu_power(ips, &old_cpu_power, 1021 IPS_SAMPLE_PERIOD); 1022 cpu_samples[i] = cpu_power; 1023 1024 if (ips->read_mch_val) { 1025 mchp = ips->read_mch_val(); 1026 mchp_samples[i] = mchp; 1027 } 1028 1029 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1030 if (kthread_should_stop()) 1031 break; 1032 } 1033 1034 ips->mcp_avg_temp = calc_avg_temp(ips, mcp_samples); 1035 ips->ctv1_avg_temp = calc_avg_temp(ips, ctv1_samples); 1036 ips->ctv2_avg_temp = calc_avg_temp(ips, ctv2_samples); 1037 ips->mch_avg_temp = calc_avg_temp(ips, mch_samples); 1038 ips->cpu_avg_power = calc_avg_power(ips, cpu_samples); 1039 ips->mch_avg_power = calc_avg_power(ips, mchp_samples); 1040 kfree(mcp_samples); 1041 kfree(ctv1_samples); 1042 kfree(ctv2_samples); 1043 kfree(mch_samples); 1044 kfree(cpu_samples); 1045 kfree(mchp_samples); 1046 1047 /* Start the adjustment thread now that we have data */ 1048 wake_up_process(ips->adjust); 1049 1050 /* 1051 * Ok, now we have an initial avg. From here on out, we track the 1052 * running avg using a decaying average calculation. This allows 1053 * us to reduce the sample frequency if the CPU and GPU are idle. 1054 */ 1055 old_cpu_power = thm_readl(THM_CEC); 1056 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD)); 1057 last_sample_period = IPS_SAMPLE_PERIOD; 1058 1059 setup_deferrable_timer_on_stack(&timer, monitor_timeout, 1060 (unsigned long)current); 1061 do { 1062 u32 cpu_val, mch_val; 1063 u16 val; 1064 1065 /* MCP itself */ 1066 val = read_ptv(ips); 1067 ips->mcp_avg_temp = update_average_temp(ips->mcp_avg_temp, val); 1068 1069 /* Processor 0 */ 1070 val = read_ctv(ips, 0); 1071 ips->ctv1_avg_temp = 1072 update_average_temp(ips->ctv1_avg_temp, val); 1073 /* Power */ 1074 cpu_val = get_cpu_power(ips, &old_cpu_power, 1075 last_sample_period); 1076 ips->cpu_avg_power = 1077 update_average_power(ips->cpu_avg_power, cpu_val); 1078 1079 if (ips->second_cpu) { 1080 /* Processor 1 */ 1081 val = read_ctv(ips, 1); 1082 ips->ctv2_avg_temp = 1083 update_average_temp(ips->ctv2_avg_temp, val); 1084 } 1085 1086 /* MCH */ 1087 val = read_mgtv(ips); 1088 ips->mch_avg_temp = update_average_temp(ips->mch_avg_temp, val); 1089 /* Power */ 1090 if (ips->read_mch_val) { 1091 mch_val = ips->read_mch_val(); 1092 ips->mch_avg_power = 1093 update_average_power(ips->mch_avg_power, 1094 mch_val); 1095 } 1096 1097 /* 1098 * Make sure ME is updating thermal regs. 1099 * Note: 1100 * If it's been more than a second since the last update, 1101 * the ME is probably hung. 1102 */ 1103 cur_seqno = (thm_readl(THM_ITV) & ITV_ME_SEQNO_MASK) >> 1104 ITV_ME_SEQNO_SHIFT; 1105 if (cur_seqno == last_seqno && 1106 time_after(jiffies, seqno_timestamp + HZ)) { 1107 dev_warn(&ips->dev->dev, "ME failed to update for more than 1s, likely hung\n"); 1108 } else { 1109 seqno_timestamp = get_jiffies_64(); 1110 last_seqno = cur_seqno; 1111 } 1112 1113 last_msecs = jiffies_to_msecs(jiffies); 1114 expire = jiffies + msecs_to_jiffies(IPS_SAMPLE_PERIOD); 1115 1116 __set_current_state(TASK_INTERRUPTIBLE); 1117 mod_timer(&timer, expire); 1118 schedule(); 1119 1120 /* Calculate actual sample period for power averaging */ 1121 last_sample_period = jiffies_to_msecs(jiffies) - last_msecs; 1122 if (!last_sample_period) 1123 last_sample_period = 1; 1124 } while (!kthread_should_stop()); 1125 1126 del_timer_sync(&timer); 1127 destroy_timer_on_stack(&timer); 1128 1129 dev_dbg(&ips->dev->dev, "ips-monitor thread stopped\n"); 1130 1131 return 0; 1132 } 1133 1134 #if 0 1135 #define THM_DUMPW(reg) \ 1136 { \ 1137 u16 val = thm_readw(reg); \ 1138 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \ 1139 } 1140 #define THM_DUMPL(reg) \ 1141 { \ 1142 u32 val = thm_readl(reg); \ 1143 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \ 1144 } 1145 #define THM_DUMPQ(reg) \ 1146 { \ 1147 u64 val = thm_readq(reg); \ 1148 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \ 1149 } 1150 1151 static void dump_thermal_info(struct ips_driver *ips) 1152 { 1153 u16 ptl; 1154 1155 ptl = thm_readw(THM_PTL); 1156 dev_dbg(&ips->dev->dev, "Processor temp limit: %d\n", ptl); 1157 1158 THM_DUMPW(THM_CTA); 1159 THM_DUMPW(THM_TRC); 1160 THM_DUMPW(THM_CTV1); 1161 THM_DUMPL(THM_STS); 1162 THM_DUMPW(THM_PTV); 1163 THM_DUMPQ(THM_MGTV); 1164 } 1165 #endif 1166 1167 /** 1168 * ips_irq_handler - handle temperature triggers and other IPS events 1169 * @irq: irq number 1170 * @arg: unused 1171 * 1172 * Handle temperature limit trigger events, generally by lowering the clamps. 1173 * If we're at a critical limit, we clamp back to the lowest possible value 1174 * to prevent emergency shutdown. 1175 */ 1176 static irqreturn_t ips_irq_handler(int irq, void *arg) 1177 { 1178 struct ips_driver *ips = arg; 1179 u8 tses = thm_readb(THM_TSES); 1180 u8 tes = thm_readb(THM_TES); 1181 1182 if (!tses && !tes) 1183 return IRQ_NONE; 1184 1185 dev_info(&ips->dev->dev, "TSES: 0x%02x\n", tses); 1186 dev_info(&ips->dev->dev, "TES: 0x%02x\n", tes); 1187 1188 /* STS update from EC? */ 1189 if (tes & 1) { 1190 u32 sts, tc1; 1191 1192 sts = thm_readl(THM_STS); 1193 tc1 = thm_readl(THM_TC1); 1194 1195 if (sts & STS_NVV) { 1196 spin_lock(&ips->turbo_status_lock); 1197 ips->core_power_limit = (sts & STS_PCPL_MASK) >> 1198 STS_PCPL_SHIFT; 1199 ips->mch_power_limit = (sts & STS_GPL_MASK) >> 1200 STS_GPL_SHIFT; 1201 /* ignore EC CPU vs GPU pref */ 1202 ips->cpu_turbo_enabled = !(sts & STS_PCTD_DIS); 1203 /* 1204 * Disable turbo for now, until we can figure 1205 * out why the power figures are wrong 1206 */ 1207 ips->cpu_turbo_enabled = false; 1208 if (ips->gpu_busy) 1209 ips->gpu_turbo_enabled = !(sts & STS_GTD_DIS); 1210 ips->mcp_temp_limit = (sts & STS_PTL_MASK) >> 1211 STS_PTL_SHIFT; 1212 ips->mcp_power_limit = (tc1 & STS_PPL_MASK) >> 1213 STS_PPL_SHIFT; 1214 verify_limits(ips); 1215 spin_unlock(&ips->turbo_status_lock); 1216 1217 thm_writeb(THM_SEC, SEC_ACK); 1218 } 1219 thm_writeb(THM_TES, tes); 1220 } 1221 1222 /* Thermal trip */ 1223 if (tses) { 1224 dev_warn(&ips->dev->dev, 1225 "thermal trip occurred, tses: 0x%04x\n", tses); 1226 thm_writeb(THM_TSES, tses); 1227 } 1228 1229 return IRQ_HANDLED; 1230 } 1231 1232 #ifndef CONFIG_DEBUG_FS 1233 static void ips_debugfs_init(struct ips_driver *ips) { return; } 1234 static void ips_debugfs_cleanup(struct ips_driver *ips) { return; } 1235 #else 1236 1237 /* Expose current state and limits in debugfs if possible */ 1238 1239 struct ips_debugfs_node { 1240 struct ips_driver *ips; 1241 char *name; 1242 int (*show)(struct seq_file *m, void *data); 1243 }; 1244 1245 static int show_cpu_temp(struct seq_file *m, void *data) 1246 { 1247 struct ips_driver *ips = m->private; 1248 1249 seq_printf(m, "%d.%02d\n", ips->ctv1_avg_temp / 100, 1250 ips->ctv1_avg_temp % 100); 1251 1252 return 0; 1253 } 1254 1255 static int show_cpu_power(struct seq_file *m, void *data) 1256 { 1257 struct ips_driver *ips = m->private; 1258 1259 seq_printf(m, "%dmW\n", ips->cpu_avg_power); 1260 1261 return 0; 1262 } 1263 1264 static int show_cpu_clamp(struct seq_file *m, void *data) 1265 { 1266 u64 turbo_override; 1267 int tdp, tdc; 1268 1269 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1270 1271 tdp = (int)(turbo_override & TURBO_TDP_MASK); 1272 tdc = (int)((turbo_override & TURBO_TDC_MASK) >> TURBO_TDC_SHIFT); 1273 1274 /* Convert to .1W/A units */ 1275 tdp = tdp * 10 / 8; 1276 tdc = tdc * 10 / 8; 1277 1278 /* Watts Amperes */ 1279 seq_printf(m, "%d.%dW %d.%dA\n", tdp / 10, tdp % 10, 1280 tdc / 10, tdc % 10); 1281 1282 return 0; 1283 } 1284 1285 static int show_mch_temp(struct seq_file *m, void *data) 1286 { 1287 struct ips_driver *ips = m->private; 1288 1289 seq_printf(m, "%d.%02d\n", ips->mch_avg_temp / 100, 1290 ips->mch_avg_temp % 100); 1291 1292 return 0; 1293 } 1294 1295 static int show_mch_power(struct seq_file *m, void *data) 1296 { 1297 struct ips_driver *ips = m->private; 1298 1299 seq_printf(m, "%dmW\n", ips->mch_avg_power); 1300 1301 return 0; 1302 } 1303 1304 static struct ips_debugfs_node ips_debug_files[] = { 1305 { NULL, "cpu_temp", show_cpu_temp }, 1306 { NULL, "cpu_power", show_cpu_power }, 1307 { NULL, "cpu_clamp", show_cpu_clamp }, 1308 { NULL, "mch_temp", show_mch_temp }, 1309 { NULL, "mch_power", show_mch_power }, 1310 }; 1311 1312 static int ips_debugfs_open(struct inode *inode, struct file *file) 1313 { 1314 struct ips_debugfs_node *node = inode->i_private; 1315 1316 return single_open(file, node->show, node->ips); 1317 } 1318 1319 static const struct file_operations ips_debugfs_ops = { 1320 .owner = THIS_MODULE, 1321 .open = ips_debugfs_open, 1322 .read = seq_read, 1323 .llseek = seq_lseek, 1324 .release = single_release, 1325 }; 1326 1327 static void ips_debugfs_cleanup(struct ips_driver *ips) 1328 { 1329 if (ips->debug_root) 1330 debugfs_remove_recursive(ips->debug_root); 1331 return; 1332 } 1333 1334 static void ips_debugfs_init(struct ips_driver *ips) 1335 { 1336 int i; 1337 1338 ips->debug_root = debugfs_create_dir("ips", NULL); 1339 if (!ips->debug_root) { 1340 dev_err(&ips->dev->dev, 1341 "failed to create debugfs entries: %ld\n", 1342 PTR_ERR(ips->debug_root)); 1343 return; 1344 } 1345 1346 for (i = 0; i < ARRAY_SIZE(ips_debug_files); i++) { 1347 struct dentry *ent; 1348 struct ips_debugfs_node *node = &ips_debug_files[i]; 1349 1350 node->ips = ips; 1351 ent = debugfs_create_file(node->name, S_IFREG | S_IRUGO, 1352 ips->debug_root, node, 1353 &ips_debugfs_ops); 1354 if (!ent) { 1355 dev_err(&ips->dev->dev, 1356 "failed to create debug file: %ld\n", 1357 PTR_ERR(ent)); 1358 goto err_cleanup; 1359 } 1360 } 1361 1362 return; 1363 1364 err_cleanup: 1365 ips_debugfs_cleanup(ips); 1366 return; 1367 } 1368 #endif /* CONFIG_DEBUG_FS */ 1369 1370 /** 1371 * ips_detect_cpu - detect whether CPU supports IPS 1372 * 1373 * Walk our list and see if we're on a supported CPU. If we find one, 1374 * return the limits for it. 1375 */ 1376 static struct ips_mcp_limits *ips_detect_cpu(struct ips_driver *ips) 1377 { 1378 u64 turbo_power, misc_en; 1379 struct ips_mcp_limits *limits = NULL; 1380 u16 tdp; 1381 1382 if (!(boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 37)) { 1383 dev_info(&ips->dev->dev, "Non-IPS CPU detected.\n"); 1384 goto out; 1385 } 1386 1387 rdmsrl(IA32_MISC_ENABLE, misc_en); 1388 /* 1389 * If the turbo enable bit isn't set, we shouldn't try to enable/disable 1390 * turbo manually or we'll get an illegal MSR access, even though 1391 * turbo will still be available. 1392 */ 1393 if (misc_en & IA32_MISC_TURBO_EN) 1394 ips->turbo_toggle_allowed = true; 1395 else 1396 ips->turbo_toggle_allowed = false; 1397 1398 if (strstr(boot_cpu_data.x86_model_id, "CPU M")) 1399 limits = &ips_sv_limits; 1400 else if (strstr(boot_cpu_data.x86_model_id, "CPU L")) 1401 limits = &ips_lv_limits; 1402 else if (strstr(boot_cpu_data.x86_model_id, "CPU U")) 1403 limits = &ips_ulv_limits; 1404 else { 1405 dev_info(&ips->dev->dev, "No CPUID match found.\n"); 1406 goto out; 1407 } 1408 1409 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_power); 1410 tdp = turbo_power & TURBO_TDP_MASK; 1411 1412 /* Sanity check TDP against CPU */ 1413 if (limits->core_power_limit != (tdp / 8) * 1000) { 1414 dev_info(&ips->dev->dev, "CPU TDP doesn't match expected value (found %d, expected %d)\n", 1415 tdp / 8, limits->core_power_limit / 1000); 1416 limits->core_power_limit = (tdp / 8) * 1000; 1417 } 1418 1419 out: 1420 return limits; 1421 } 1422 1423 /** 1424 * ips_get_i915_syms - try to get GPU control methods from i915 driver 1425 * @ips: IPS driver 1426 * 1427 * The i915 driver exports several interfaces to allow the IPS driver to 1428 * monitor and control graphics turbo mode. If we can find them, we can 1429 * enable graphics turbo, otherwise we must disable it to avoid exceeding 1430 * thermal and power limits in the MCP. 1431 */ 1432 static bool ips_get_i915_syms(struct ips_driver *ips) 1433 { 1434 ips->read_mch_val = symbol_get(i915_read_mch_val); 1435 if (!ips->read_mch_val) 1436 goto out_err; 1437 ips->gpu_raise = symbol_get(i915_gpu_raise); 1438 if (!ips->gpu_raise) 1439 goto out_put_mch; 1440 ips->gpu_lower = symbol_get(i915_gpu_lower); 1441 if (!ips->gpu_lower) 1442 goto out_put_raise; 1443 ips->gpu_busy = symbol_get(i915_gpu_busy); 1444 if (!ips->gpu_busy) 1445 goto out_put_lower; 1446 ips->gpu_turbo_disable = symbol_get(i915_gpu_turbo_disable); 1447 if (!ips->gpu_turbo_disable) 1448 goto out_put_busy; 1449 1450 return true; 1451 1452 out_put_busy: 1453 symbol_put(i915_gpu_busy); 1454 out_put_lower: 1455 symbol_put(i915_gpu_lower); 1456 out_put_raise: 1457 symbol_put(i915_gpu_raise); 1458 out_put_mch: 1459 symbol_put(i915_read_mch_val); 1460 out_err: 1461 return false; 1462 } 1463 1464 static bool 1465 ips_gpu_turbo_enabled(struct ips_driver *ips) 1466 { 1467 if (!ips->gpu_busy && late_i915_load) { 1468 if (ips_get_i915_syms(ips)) { 1469 dev_info(&ips->dev->dev, 1470 "i915 driver attached, reenabling gpu turbo\n"); 1471 ips->gpu_turbo_enabled = !(thm_readl(THM_HTS) & HTS_GTD_DIS); 1472 } 1473 } 1474 1475 return ips->gpu_turbo_enabled; 1476 } 1477 1478 void 1479 ips_link_to_i915_driver(void) 1480 { 1481 /* We can't cleanly get at the various ips_driver structs from 1482 * this caller (the i915 driver), so just set a flag saying 1483 * that it's time to try getting the symbols again. 1484 */ 1485 late_i915_load = true; 1486 } 1487 EXPORT_SYMBOL_GPL(ips_link_to_i915_driver); 1488 1489 static DEFINE_PCI_DEVICE_TABLE(ips_id_table) = { 1490 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 1491 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR), }, 1492 { 0, } 1493 }; 1494 1495 MODULE_DEVICE_TABLE(pci, ips_id_table); 1496 1497 static int ips_probe(struct pci_dev *dev, const struct pci_device_id *id) 1498 { 1499 u64 platform_info; 1500 struct ips_driver *ips; 1501 u32 hts; 1502 int ret = 0; 1503 u16 htshi, trc, trc_required_mask; 1504 u8 tse; 1505 1506 ips = kzalloc(sizeof(struct ips_driver), GFP_KERNEL); 1507 if (!ips) 1508 return -ENOMEM; 1509 1510 pci_set_drvdata(dev, ips); 1511 ips->dev = dev; 1512 1513 ips->limits = ips_detect_cpu(ips); 1514 if (!ips->limits) { 1515 dev_info(&dev->dev, "IPS not supported on this CPU\n"); 1516 ret = -ENXIO; 1517 goto error_free; 1518 } 1519 1520 spin_lock_init(&ips->turbo_status_lock); 1521 1522 ret = pci_enable_device(dev); 1523 if (ret) { 1524 dev_err(&dev->dev, "can't enable PCI device, aborting\n"); 1525 goto error_free; 1526 } 1527 1528 if (!pci_resource_start(dev, 0)) { 1529 dev_err(&dev->dev, "TBAR not assigned, aborting\n"); 1530 ret = -ENXIO; 1531 goto error_free; 1532 } 1533 1534 ret = pci_request_regions(dev, "ips thermal sensor"); 1535 if (ret) { 1536 dev_err(&dev->dev, "thermal resource busy, aborting\n"); 1537 goto error_free; 1538 } 1539 1540 1541 ips->regmap = ioremap(pci_resource_start(dev, 0), 1542 pci_resource_len(dev, 0)); 1543 if (!ips->regmap) { 1544 dev_err(&dev->dev, "failed to map thermal regs, aborting\n"); 1545 ret = -EBUSY; 1546 goto error_release; 1547 } 1548 1549 tse = thm_readb(THM_TSE); 1550 if (tse != TSE_EN) { 1551 dev_err(&dev->dev, "thermal device not enabled (0x%02x), aborting\n", tse); 1552 ret = -ENXIO; 1553 goto error_unmap; 1554 } 1555 1556 trc = thm_readw(THM_TRC); 1557 trc_required_mask = TRC_CORE1_EN | TRC_CORE_PWR | TRC_MCH_EN; 1558 if ((trc & trc_required_mask) != trc_required_mask) { 1559 dev_err(&dev->dev, "thermal reporting for required devices not enabled, aborting\n"); 1560 ret = -ENXIO; 1561 goto error_unmap; 1562 } 1563 1564 if (trc & TRC_CORE2_EN) 1565 ips->second_cpu = true; 1566 1567 update_turbo_limits(ips); 1568 dev_dbg(&dev->dev, "max cpu power clamp: %dW\n", 1569 ips->mcp_power_limit / 10); 1570 dev_dbg(&dev->dev, "max core power clamp: %dW\n", 1571 ips->core_power_limit / 10); 1572 /* BIOS may update limits at runtime */ 1573 if (thm_readl(THM_PSC) & PSP_PBRT) 1574 ips->poll_turbo_status = true; 1575 1576 if (!ips_get_i915_syms(ips)) { 1577 dev_err(&dev->dev, "failed to get i915 symbols, graphics turbo disabled\n"); 1578 ips->gpu_turbo_enabled = false; 1579 } else { 1580 dev_dbg(&dev->dev, "graphics turbo enabled\n"); 1581 ips->gpu_turbo_enabled = true; 1582 } 1583 1584 /* 1585 * Check PLATFORM_INFO MSR to make sure this chip is 1586 * turbo capable. 1587 */ 1588 rdmsrl(PLATFORM_INFO, platform_info); 1589 if (!(platform_info & PLATFORM_TDP)) { 1590 dev_err(&dev->dev, "platform indicates TDP override unavailable, aborting\n"); 1591 ret = -ENODEV; 1592 goto error_unmap; 1593 } 1594 1595 /* 1596 * IRQ handler for ME interaction 1597 * Note: don't use MSI here as the PCH has bugs. 1598 */ 1599 pci_disable_msi(dev); 1600 ret = request_irq(dev->irq, ips_irq_handler, IRQF_SHARED, "ips", 1601 ips); 1602 if (ret) { 1603 dev_err(&dev->dev, "request irq failed, aborting\n"); 1604 goto error_unmap; 1605 } 1606 1607 /* Enable aux, hot & critical interrupts */ 1608 thm_writeb(THM_TSPIEN, TSPIEN_AUX2_LOHI | TSPIEN_CRIT_LOHI | 1609 TSPIEN_HOT_LOHI | TSPIEN_AUX_LOHI); 1610 thm_writeb(THM_TEN, TEN_UPDATE_EN); 1611 1612 /* Collect adjustment values */ 1613 ips->cta_val = thm_readw(THM_CTA); 1614 ips->pta_val = thm_readw(THM_PTA); 1615 ips->mgta_val = thm_readw(THM_MGTA); 1616 1617 /* Save turbo limits & ratios */ 1618 rdmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1619 1620 ips_disable_cpu_turbo(ips); 1621 ips->cpu_turbo_enabled = false; 1622 1623 /* Create thermal adjust thread */ 1624 ips->adjust = kthread_create(ips_adjust, ips, "ips-adjust"); 1625 if (IS_ERR(ips->adjust)) { 1626 dev_err(&dev->dev, 1627 "failed to create thermal adjust thread, aborting\n"); 1628 ret = -ENOMEM; 1629 goto error_free_irq; 1630 1631 } 1632 1633 /* 1634 * Set up the work queue and monitor thread. The monitor thread 1635 * will wake up ips_adjust thread. 1636 */ 1637 ips->monitor = kthread_run(ips_monitor, ips, "ips-monitor"); 1638 if (IS_ERR(ips->monitor)) { 1639 dev_err(&dev->dev, 1640 "failed to create thermal monitor thread, aborting\n"); 1641 ret = -ENOMEM; 1642 goto error_thread_cleanup; 1643 } 1644 1645 hts = (ips->core_power_limit << HTS_PCPL_SHIFT) | 1646 (ips->mcp_temp_limit << HTS_PTL_SHIFT) | HTS_NVV; 1647 htshi = HTS2_PRST_RUNNING << HTS2_PRST_SHIFT; 1648 1649 thm_writew(THM_HTSHI, htshi); 1650 thm_writel(THM_HTS, hts); 1651 1652 ips_debugfs_init(ips); 1653 1654 dev_info(&dev->dev, "IPS driver initialized, MCP temp limit %d\n", 1655 ips->mcp_temp_limit); 1656 return ret; 1657 1658 error_thread_cleanup: 1659 kthread_stop(ips->adjust); 1660 error_free_irq: 1661 free_irq(ips->dev->irq, ips); 1662 error_unmap: 1663 iounmap(ips->regmap); 1664 error_release: 1665 pci_release_regions(dev); 1666 error_free: 1667 kfree(ips); 1668 return ret; 1669 } 1670 1671 static void ips_remove(struct pci_dev *dev) 1672 { 1673 struct ips_driver *ips = pci_get_drvdata(dev); 1674 u64 turbo_override; 1675 1676 if (!ips) 1677 return; 1678 1679 ips_debugfs_cleanup(ips); 1680 1681 /* Release i915 driver */ 1682 if (ips->read_mch_val) 1683 symbol_put(i915_read_mch_val); 1684 if (ips->gpu_raise) 1685 symbol_put(i915_gpu_raise); 1686 if (ips->gpu_lower) 1687 symbol_put(i915_gpu_lower); 1688 if (ips->gpu_busy) 1689 symbol_put(i915_gpu_busy); 1690 if (ips->gpu_turbo_disable) 1691 symbol_put(i915_gpu_turbo_disable); 1692 1693 rdmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1694 turbo_override &= ~(TURBO_TDC_OVR_EN | TURBO_TDP_OVR_EN); 1695 wrmsrl(TURBO_POWER_CURRENT_LIMIT, turbo_override); 1696 wrmsrl(TURBO_POWER_CURRENT_LIMIT, ips->orig_turbo_limit); 1697 1698 free_irq(ips->dev->irq, ips); 1699 if (ips->adjust) 1700 kthread_stop(ips->adjust); 1701 if (ips->monitor) 1702 kthread_stop(ips->monitor); 1703 iounmap(ips->regmap); 1704 pci_release_regions(dev); 1705 kfree(ips); 1706 dev_dbg(&dev->dev, "IPS driver removed\n"); 1707 } 1708 1709 #ifdef CONFIG_PM 1710 static int ips_suspend(struct pci_dev *dev, pm_message_t state) 1711 { 1712 return 0; 1713 } 1714 1715 static int ips_resume(struct pci_dev *dev) 1716 { 1717 return 0; 1718 } 1719 #else 1720 #define ips_suspend NULL 1721 #define ips_resume NULL 1722 #endif /* CONFIG_PM */ 1723 1724 static void ips_shutdown(struct pci_dev *dev) 1725 { 1726 } 1727 1728 static struct pci_driver ips_pci_driver = { 1729 .name = "intel ips", 1730 .id_table = ips_id_table, 1731 .probe = ips_probe, 1732 .remove = ips_remove, 1733 .suspend = ips_suspend, 1734 .resume = ips_resume, 1735 .shutdown = ips_shutdown, 1736 }; 1737 1738 static int __init ips_init(void) 1739 { 1740 return pci_register_driver(&ips_pci_driver); 1741 } 1742 module_init(ips_init); 1743 1744 static void ips_exit(void) 1745 { 1746 pci_unregister_driver(&ips_pci_driver); 1747 return; 1748 } 1749 module_exit(ips_exit); 1750 1751 MODULE_LICENSE("GPL"); 1752 MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>"); 1753 MODULE_DESCRIPTION("Intelligent Power Sharing Driver"); 1754