1386d17b2SKate Hsuan // SPDX-License-Identifier: GPL-2.0
2386d17b2SKate Hsuan /*
3386d17b2SKate Hsuan * Driver for the Intel P-Unit Mailbox IPC mechanism
4386d17b2SKate Hsuan *
5386d17b2SKate Hsuan * (C) Copyright 2015 Intel Corporation
6386d17b2SKate Hsuan *
7386d17b2SKate Hsuan * The heart of the P-Unit is the Foxton microcontroller and its firmware,
8386d17b2SKate Hsuan * which provide mailbox interface for power management usage.
9386d17b2SKate Hsuan */
10386d17b2SKate Hsuan
11386d17b2SKate Hsuan #include <linux/bitops.h>
12386d17b2SKate Hsuan #include <linux/delay.h>
13386d17b2SKate Hsuan #include <linux/device.h>
14386d17b2SKate Hsuan #include <linux/interrupt.h>
15386d17b2SKate Hsuan #include <linux/io.h>
16386d17b2SKate Hsuan #include <linux/mod_devicetable.h>
17386d17b2SKate Hsuan #include <linux/module.h>
18386d17b2SKate Hsuan #include <linux/platform_device.h>
19386d17b2SKate Hsuan
20386d17b2SKate Hsuan #include <asm/intel_punit_ipc.h>
21386d17b2SKate Hsuan
22386d17b2SKate Hsuan /* IPC Mailbox registers */
23386d17b2SKate Hsuan #define OFFSET_DATA_LOW 0x0
24386d17b2SKate Hsuan #define OFFSET_DATA_HIGH 0x4
25386d17b2SKate Hsuan /* bit field of interface register */
26386d17b2SKate Hsuan #define CMD_RUN BIT(31)
27386d17b2SKate Hsuan #define CMD_ERRCODE_MASK GENMASK(7, 0)
28386d17b2SKate Hsuan #define CMD_PARA1_SHIFT 8
29386d17b2SKate Hsuan #define CMD_PARA2_SHIFT 16
30386d17b2SKate Hsuan
31386d17b2SKate Hsuan #define CMD_TIMEOUT_SECONDS 1
32386d17b2SKate Hsuan
33386d17b2SKate Hsuan enum {
34386d17b2SKate Hsuan BASE_DATA = 0,
35386d17b2SKate Hsuan BASE_IFACE,
36386d17b2SKate Hsuan BASE_MAX,
37386d17b2SKate Hsuan };
38386d17b2SKate Hsuan
39386d17b2SKate Hsuan typedef struct {
40386d17b2SKate Hsuan struct device *dev;
41386d17b2SKate Hsuan struct mutex lock;
42386d17b2SKate Hsuan int irq;
43386d17b2SKate Hsuan struct completion cmd_complete;
44386d17b2SKate Hsuan /* base of interface and data registers */
45386d17b2SKate Hsuan void __iomem *base[RESERVED_IPC][BASE_MAX];
46386d17b2SKate Hsuan IPC_TYPE type;
47386d17b2SKate Hsuan } IPC_DEV;
48386d17b2SKate Hsuan
49386d17b2SKate Hsuan static IPC_DEV *punit_ipcdev;
50386d17b2SKate Hsuan
ipc_read_status(IPC_DEV * ipcdev,IPC_TYPE type)51386d17b2SKate Hsuan static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type)
52386d17b2SKate Hsuan {
53386d17b2SKate Hsuan return readl(ipcdev->base[type][BASE_IFACE]);
54386d17b2SKate Hsuan }
55386d17b2SKate Hsuan
ipc_write_cmd(IPC_DEV * ipcdev,IPC_TYPE type,u32 cmd)56386d17b2SKate Hsuan static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd)
57386d17b2SKate Hsuan {
58386d17b2SKate Hsuan writel(cmd, ipcdev->base[type][BASE_IFACE]);
59386d17b2SKate Hsuan }
60386d17b2SKate Hsuan
ipc_read_data_low(IPC_DEV * ipcdev,IPC_TYPE type)61386d17b2SKate Hsuan static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type)
62386d17b2SKate Hsuan {
63386d17b2SKate Hsuan return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
64386d17b2SKate Hsuan }
65386d17b2SKate Hsuan
ipc_read_data_high(IPC_DEV * ipcdev,IPC_TYPE type)66386d17b2SKate Hsuan static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type)
67386d17b2SKate Hsuan {
68386d17b2SKate Hsuan return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
69386d17b2SKate Hsuan }
70386d17b2SKate Hsuan
ipc_write_data_low(IPC_DEV * ipcdev,IPC_TYPE type,u32 data)71386d17b2SKate Hsuan static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
72386d17b2SKate Hsuan {
73386d17b2SKate Hsuan writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
74386d17b2SKate Hsuan }
75386d17b2SKate Hsuan
ipc_write_data_high(IPC_DEV * ipcdev,IPC_TYPE type,u32 data)76386d17b2SKate Hsuan static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
77386d17b2SKate Hsuan {
78386d17b2SKate Hsuan writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
79386d17b2SKate Hsuan }
80386d17b2SKate Hsuan
ipc_err_string(int error)81386d17b2SKate Hsuan static const char *ipc_err_string(int error)
82386d17b2SKate Hsuan {
83386d17b2SKate Hsuan if (error == IPC_PUNIT_ERR_SUCCESS)
84386d17b2SKate Hsuan return "no error";
85386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_INVALID_CMD)
86386d17b2SKate Hsuan return "invalid command";
87386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER)
88386d17b2SKate Hsuan return "invalid parameter";
89386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT)
90386d17b2SKate Hsuan return "command timeout";
91386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_CMD_LOCKED)
92386d17b2SKate Hsuan return "command locked";
93386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_INVALID_VR_ID)
94386d17b2SKate Hsuan return "invalid vr id";
95386d17b2SKate Hsuan else if (error == IPC_PUNIT_ERR_VR_ERR)
96386d17b2SKate Hsuan return "vr error";
97386d17b2SKate Hsuan else
98386d17b2SKate Hsuan return "unknown error";
99386d17b2SKate Hsuan }
100386d17b2SKate Hsuan
intel_punit_ipc_check_status(IPC_DEV * ipcdev,IPC_TYPE type)101386d17b2SKate Hsuan static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type)
102386d17b2SKate Hsuan {
103386d17b2SKate Hsuan int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC;
104386d17b2SKate Hsuan int errcode;
105386d17b2SKate Hsuan int status;
106386d17b2SKate Hsuan
107386d17b2SKate Hsuan if (ipcdev->irq) {
108386d17b2SKate Hsuan if (!wait_for_completion_timeout(&ipcdev->cmd_complete,
109386d17b2SKate Hsuan CMD_TIMEOUT_SECONDS * HZ)) {
110386d17b2SKate Hsuan dev_err(ipcdev->dev, "IPC timed out\n");
111386d17b2SKate Hsuan return -ETIMEDOUT;
112386d17b2SKate Hsuan }
113386d17b2SKate Hsuan } else {
114386d17b2SKate Hsuan while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops)
115386d17b2SKate Hsuan udelay(1);
116386d17b2SKate Hsuan if (!loops) {
117386d17b2SKate Hsuan dev_err(ipcdev->dev, "IPC timed out\n");
118386d17b2SKate Hsuan return -ETIMEDOUT;
119386d17b2SKate Hsuan }
120386d17b2SKate Hsuan }
121386d17b2SKate Hsuan
122386d17b2SKate Hsuan status = ipc_read_status(ipcdev, type);
123386d17b2SKate Hsuan errcode = status & CMD_ERRCODE_MASK;
124386d17b2SKate Hsuan if (errcode) {
125386d17b2SKate Hsuan dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n",
126386d17b2SKate Hsuan ipc_err_string(errcode), status);
127386d17b2SKate Hsuan return -EIO;
128386d17b2SKate Hsuan }
129386d17b2SKate Hsuan
130386d17b2SKate Hsuan return 0;
131386d17b2SKate Hsuan }
132386d17b2SKate Hsuan
133386d17b2SKate Hsuan /**
134386d17b2SKate Hsuan * intel_punit_ipc_simple_command() - Simple IPC command
135386d17b2SKate Hsuan * @cmd: IPC command code.
136386d17b2SKate Hsuan * @para1: First 8bit parameter, set 0 if not used.
137386d17b2SKate Hsuan * @para2: Second 8bit parameter, set 0 if not used.
138386d17b2SKate Hsuan *
139386d17b2SKate Hsuan * Send a IPC command to P-Unit when there is no data transaction
140386d17b2SKate Hsuan *
141386d17b2SKate Hsuan * Return: IPC error code or 0 on success.
142386d17b2SKate Hsuan */
intel_punit_ipc_simple_command(int cmd,int para1,int para2)143386d17b2SKate Hsuan int intel_punit_ipc_simple_command(int cmd, int para1, int para2)
144386d17b2SKate Hsuan {
145386d17b2SKate Hsuan IPC_DEV *ipcdev = punit_ipcdev;
146386d17b2SKate Hsuan IPC_TYPE type;
147386d17b2SKate Hsuan u32 val;
148386d17b2SKate Hsuan int ret;
149386d17b2SKate Hsuan
150386d17b2SKate Hsuan mutex_lock(&ipcdev->lock);
151386d17b2SKate Hsuan
152386d17b2SKate Hsuan reinit_completion(&ipcdev->cmd_complete);
153386d17b2SKate Hsuan type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
154386d17b2SKate Hsuan
155386d17b2SKate Hsuan val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
156386d17b2SKate Hsuan val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
157386d17b2SKate Hsuan ipc_write_cmd(ipcdev, type, val);
158386d17b2SKate Hsuan ret = intel_punit_ipc_check_status(ipcdev, type);
159386d17b2SKate Hsuan
160386d17b2SKate Hsuan mutex_unlock(&ipcdev->lock);
161386d17b2SKate Hsuan
162386d17b2SKate Hsuan return ret;
163386d17b2SKate Hsuan }
164386d17b2SKate Hsuan EXPORT_SYMBOL(intel_punit_ipc_simple_command);
165386d17b2SKate Hsuan
166386d17b2SKate Hsuan /**
167386d17b2SKate Hsuan * intel_punit_ipc_command() - IPC command with data and pointers
168386d17b2SKate Hsuan * @cmd: IPC command code.
169386d17b2SKate Hsuan * @para1: First 8bit parameter, set 0 if not used.
170386d17b2SKate Hsuan * @para2: Second 8bit parameter, set 0 if not used.
171386d17b2SKate Hsuan * @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD.
172386d17b2SKate Hsuan * @out: Output data.
173386d17b2SKate Hsuan *
174386d17b2SKate Hsuan * Send a IPC command to P-Unit with data transaction
175386d17b2SKate Hsuan *
176386d17b2SKate Hsuan * Return: IPC error code or 0 on success.
177386d17b2SKate Hsuan */
intel_punit_ipc_command(u32 cmd,u32 para1,u32 para2,u32 * in,u32 * out)178386d17b2SKate Hsuan int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out)
179386d17b2SKate Hsuan {
180386d17b2SKate Hsuan IPC_DEV *ipcdev = punit_ipcdev;
181386d17b2SKate Hsuan IPC_TYPE type;
182386d17b2SKate Hsuan u32 val;
183386d17b2SKate Hsuan int ret;
184386d17b2SKate Hsuan
185386d17b2SKate Hsuan mutex_lock(&ipcdev->lock);
186386d17b2SKate Hsuan
187386d17b2SKate Hsuan reinit_completion(&ipcdev->cmd_complete);
188386d17b2SKate Hsuan type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
189386d17b2SKate Hsuan
190386d17b2SKate Hsuan if (in) {
191386d17b2SKate Hsuan ipc_write_data_low(ipcdev, type, *in);
192386d17b2SKate Hsuan if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
193386d17b2SKate Hsuan ipc_write_data_high(ipcdev, type, *++in);
194386d17b2SKate Hsuan }
195386d17b2SKate Hsuan
196386d17b2SKate Hsuan val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
197386d17b2SKate Hsuan val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
198386d17b2SKate Hsuan ipc_write_cmd(ipcdev, type, val);
199386d17b2SKate Hsuan
200386d17b2SKate Hsuan ret = intel_punit_ipc_check_status(ipcdev, type);
201386d17b2SKate Hsuan if (ret)
202386d17b2SKate Hsuan goto out;
203386d17b2SKate Hsuan
204386d17b2SKate Hsuan if (out) {
205386d17b2SKate Hsuan *out = ipc_read_data_low(ipcdev, type);
206386d17b2SKate Hsuan if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
207386d17b2SKate Hsuan *++out = ipc_read_data_high(ipcdev, type);
208386d17b2SKate Hsuan }
209386d17b2SKate Hsuan
210386d17b2SKate Hsuan out:
211386d17b2SKate Hsuan mutex_unlock(&ipcdev->lock);
212386d17b2SKate Hsuan return ret;
213386d17b2SKate Hsuan }
214386d17b2SKate Hsuan EXPORT_SYMBOL_GPL(intel_punit_ipc_command);
215386d17b2SKate Hsuan
intel_punit_ioc(int irq,void * dev_id)216386d17b2SKate Hsuan static irqreturn_t intel_punit_ioc(int irq, void *dev_id)
217386d17b2SKate Hsuan {
218386d17b2SKate Hsuan IPC_DEV *ipcdev = dev_id;
219386d17b2SKate Hsuan
220386d17b2SKate Hsuan complete(&ipcdev->cmd_complete);
221386d17b2SKate Hsuan return IRQ_HANDLED;
222386d17b2SKate Hsuan }
223386d17b2SKate Hsuan
intel_punit_get_bars(struct platform_device * pdev)224386d17b2SKate Hsuan static int intel_punit_get_bars(struct platform_device *pdev)
225386d17b2SKate Hsuan {
226386d17b2SKate Hsuan void __iomem *addr;
227386d17b2SKate Hsuan
228386d17b2SKate Hsuan /*
229386d17b2SKate Hsuan * The following resources are required
230386d17b2SKate Hsuan * - BIOS_IPC BASE_DATA
231386d17b2SKate Hsuan * - BIOS_IPC BASE_IFACE
232386d17b2SKate Hsuan */
233386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 0);
234386d17b2SKate Hsuan if (IS_ERR(addr))
235386d17b2SKate Hsuan return PTR_ERR(addr);
236386d17b2SKate Hsuan punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr;
237386d17b2SKate Hsuan
238386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 1);
239386d17b2SKate Hsuan if (IS_ERR(addr))
240386d17b2SKate Hsuan return PTR_ERR(addr);
241386d17b2SKate Hsuan punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr;
242386d17b2SKate Hsuan
243386d17b2SKate Hsuan /*
244386d17b2SKate Hsuan * The following resources are optional
245386d17b2SKate Hsuan * - ISPDRIVER_IPC BASE_DATA
246386d17b2SKate Hsuan * - ISPDRIVER_IPC BASE_IFACE
247386d17b2SKate Hsuan * - GTDRIVER_IPC BASE_DATA
248386d17b2SKate Hsuan * - GTDRIVER_IPC BASE_IFACE
249386d17b2SKate Hsuan */
250386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 2);
251386d17b2SKate Hsuan if (!IS_ERR(addr))
252386d17b2SKate Hsuan punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr;
253386d17b2SKate Hsuan
254386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 3);
255386d17b2SKate Hsuan if (!IS_ERR(addr))
256386d17b2SKate Hsuan punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr;
257386d17b2SKate Hsuan
258386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 4);
259386d17b2SKate Hsuan if (!IS_ERR(addr))
260386d17b2SKate Hsuan punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr;
261386d17b2SKate Hsuan
262386d17b2SKate Hsuan addr = devm_platform_ioremap_resource(pdev, 5);
263386d17b2SKate Hsuan if (!IS_ERR(addr))
264386d17b2SKate Hsuan punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr;
265386d17b2SKate Hsuan
266386d17b2SKate Hsuan return 0;
267386d17b2SKate Hsuan }
268386d17b2SKate Hsuan
intel_punit_ipc_probe(struct platform_device * pdev)269386d17b2SKate Hsuan static int intel_punit_ipc_probe(struct platform_device *pdev)
270386d17b2SKate Hsuan {
271386d17b2SKate Hsuan int irq, ret;
272386d17b2SKate Hsuan
273386d17b2SKate Hsuan punit_ipcdev = devm_kzalloc(&pdev->dev,
274386d17b2SKate Hsuan sizeof(*punit_ipcdev), GFP_KERNEL);
275386d17b2SKate Hsuan if (!punit_ipcdev)
276386d17b2SKate Hsuan return -ENOMEM;
277386d17b2SKate Hsuan
278386d17b2SKate Hsuan platform_set_drvdata(pdev, punit_ipcdev);
279386d17b2SKate Hsuan
280386d17b2SKate Hsuan irq = platform_get_irq_optional(pdev, 0);
281386d17b2SKate Hsuan if (irq < 0) {
282386d17b2SKate Hsuan dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n");
283386d17b2SKate Hsuan } else {
284386d17b2SKate Hsuan ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
285386d17b2SKate Hsuan IRQF_NO_SUSPEND, "intel_punit_ipc",
286386d17b2SKate Hsuan &punit_ipcdev);
287386d17b2SKate Hsuan if (ret) {
288386d17b2SKate Hsuan dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
289386d17b2SKate Hsuan return ret;
290386d17b2SKate Hsuan }
291386d17b2SKate Hsuan punit_ipcdev->irq = irq;
292386d17b2SKate Hsuan }
293386d17b2SKate Hsuan
294386d17b2SKate Hsuan ret = intel_punit_get_bars(pdev);
295386d17b2SKate Hsuan if (ret)
296386d17b2SKate Hsuan return ret;
297386d17b2SKate Hsuan
298386d17b2SKate Hsuan punit_ipcdev->dev = &pdev->dev;
299386d17b2SKate Hsuan mutex_init(&punit_ipcdev->lock);
300386d17b2SKate Hsuan init_completion(&punit_ipcdev->cmd_complete);
301386d17b2SKate Hsuan
302386d17b2SKate Hsuan return 0;
303386d17b2SKate Hsuan }
304386d17b2SKate Hsuan
305386d17b2SKate Hsuan static const struct acpi_device_id punit_ipc_acpi_ids[] = {
306386d17b2SKate Hsuan { "INT34D4", 0 },
307386d17b2SKate Hsuan { }
308386d17b2SKate Hsuan };
309386d17b2SKate Hsuan MODULE_DEVICE_TABLE(acpi, punit_ipc_acpi_ids);
310386d17b2SKate Hsuan
311386d17b2SKate Hsuan static struct platform_driver intel_punit_ipc_driver = {
312386d17b2SKate Hsuan .probe = intel_punit_ipc_probe,
313386d17b2SKate Hsuan .driver = {
314386d17b2SKate Hsuan .name = "intel_punit_ipc",
315*349bff48SAndy Shevchenko .acpi_match_table = punit_ipc_acpi_ids,
316386d17b2SKate Hsuan },
317386d17b2SKate Hsuan };
318386d17b2SKate Hsuan
intel_punit_ipc_init(void)319386d17b2SKate Hsuan static int __init intel_punit_ipc_init(void)
320386d17b2SKate Hsuan {
321386d17b2SKate Hsuan return platform_driver_register(&intel_punit_ipc_driver);
322386d17b2SKate Hsuan }
323386d17b2SKate Hsuan
intel_punit_ipc_exit(void)324386d17b2SKate Hsuan static void __exit intel_punit_ipc_exit(void)
325386d17b2SKate Hsuan {
326386d17b2SKate Hsuan platform_driver_unregister(&intel_punit_ipc_driver);
327386d17b2SKate Hsuan }
328386d17b2SKate Hsuan
329386d17b2SKate Hsuan MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
330386d17b2SKate Hsuan MODULE_DESCRIPTION("Intel P-Unit IPC driver");
331386d17b2SKate Hsuan MODULE_LICENSE("GPL v2");
332386d17b2SKate Hsuan
333386d17b2SKate Hsuan /* Some modules are dependent on this, so init earlier */
334386d17b2SKate Hsuan fs_initcall(intel_punit_ipc_init);
335386d17b2SKate Hsuan module_exit(intel_punit_ipc_exit);
336