1*d9a07880SDavid E. Box // SPDX-License-Identifier: GPL-2.0 2*d9a07880SDavid E. Box /* 3*d9a07880SDavid E. Box * Copyright (c) 2025, Intel Corporation. 4*d9a07880SDavid E. Box * All Rights Reserved. 5*d9a07880SDavid E. Box * 6*d9a07880SDavid E. Box * Author: "David E. Box" <david.e.box@linux.intel.com> 7*d9a07880SDavid E. Box */ 8*d9a07880SDavid E. Box 9*d9a07880SDavid E. Box #include <linux/export.h> 10*d9a07880SDavid E. Box #include <linux/types.h> 11*d9a07880SDavid E. Box 12*d9a07880SDavid E. Box #include <linux/intel_pmt_features.h> 13*d9a07880SDavid E. Box 14*d9a07880SDavid E. Box const char * const pmt_feature_names[] = { 15*d9a07880SDavid E. Box [FEATURE_PER_CORE_PERF_TELEM] = "per_core_performance_telemetry", 16*d9a07880SDavid E. Box [FEATURE_PER_CORE_ENV_TELEM] = "per_core_environment_telemetry", 17*d9a07880SDavid E. Box [FEATURE_PER_RMID_PERF_TELEM] = "per_rmid_perf_telemetry", 18*d9a07880SDavid E. Box [FEATURE_ACCEL_TELEM] = "accelerator_telemetry", 19*d9a07880SDavid E. Box [FEATURE_UNCORE_TELEM] = "uncore_telemetry", 20*d9a07880SDavid E. Box [FEATURE_CRASH_LOG] = "crash_log", 21*d9a07880SDavid E. Box [FEATURE_PETE_LOG] = "pete_log", 22*d9a07880SDavid E. Box [FEATURE_TPMI_CTRL] = "tpmi_control", 23*d9a07880SDavid E. Box [FEATURE_TRACING] = "tracing", 24*d9a07880SDavid E. Box [FEATURE_PER_RMID_ENERGY_TELEM] = "per_rmid_energy_telemetry", 25*d9a07880SDavid E. Box }; 26*d9a07880SDavid E. Box EXPORT_SYMBOL_NS_GPL(pmt_feature_names, "INTEL_PMT_DISCOVERY"); 27*d9a07880SDavid E. Box 28*d9a07880SDavid E. Box enum feature_layout feature_layout[] = { 29*d9a07880SDavid E. Box [FEATURE_PER_CORE_PERF_TELEM] = LAYOUT_WATCHER, 30*d9a07880SDavid E. Box [FEATURE_PER_CORE_ENV_TELEM] = LAYOUT_WATCHER, 31*d9a07880SDavid E. Box [FEATURE_PER_RMID_PERF_TELEM] = LAYOUT_RMID, 32*d9a07880SDavid E. Box [FEATURE_ACCEL_TELEM] = LAYOUT_WATCHER, 33*d9a07880SDavid E. Box [FEATURE_UNCORE_TELEM] = LAYOUT_WATCHER, 34*d9a07880SDavid E. Box [FEATURE_CRASH_LOG] = LAYOUT_COMMAND, 35*d9a07880SDavid E. Box [FEATURE_PETE_LOG] = LAYOUT_COMMAND, 36*d9a07880SDavid E. Box [FEATURE_TPMI_CTRL] = LAYOUT_CAPS_ONLY, 37*d9a07880SDavid E. Box [FEATURE_TRACING] = LAYOUT_CAPS_ONLY, 38*d9a07880SDavid E. Box [FEATURE_PER_RMID_ENERGY_TELEM] = LAYOUT_RMID, 39*d9a07880SDavid E. Box }; 40*d9a07880SDavid E. Box 41*d9a07880SDavid E. Box struct pmt_cap pmt_cap_common[] = { 42*d9a07880SDavid E. Box {PMT_CAP_TELEM, "telemetry"}, 43*d9a07880SDavid E. Box {PMT_CAP_WATCHER, "watcher"}, 44*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG, "crashlog"}, 45*d9a07880SDavid E. Box {PMT_CAP_STREAMING, "streaming"}, 46*d9a07880SDavid E. Box {PMT_CAP_THRESHOLD, "threshold"}, 47*d9a07880SDavid E. Box {PMT_CAP_WINDOW, "window"}, 48*d9a07880SDavid E. Box {PMT_CAP_CONFIG, "config"}, 49*d9a07880SDavid E. Box {PMT_CAP_TRACING, "tracing"}, 50*d9a07880SDavid E. Box {PMT_CAP_INBAND, "inband"}, 51*d9a07880SDavid E. Box {PMT_CAP_OOB, "oob"}, 52*d9a07880SDavid E. Box {PMT_CAP_SECURED_CHAN, "secure_chan"}, 53*d9a07880SDavid E. Box {PMT_CAP_PMT_SP, "pmt_sp"}, 54*d9a07880SDavid E. Box {PMT_CAP_PMT_SP_POLICY, "pmt_sp_policy"}, 55*d9a07880SDavid E. Box {} 56*d9a07880SDavid E. Box }; 57*d9a07880SDavid E. Box 58*d9a07880SDavid E. Box struct pmt_cap pmt_cap_pcpt[] = { 59*d9a07880SDavid E. Box {PMT_CAP_PCPT_CORE_PERF, "core_performance"}, 60*d9a07880SDavid E. Box {PMT_CAP_PCPT_CORE_C0_RES, "core_c0_residency"}, 61*d9a07880SDavid E. Box {PMT_CAP_PCPT_CORE_ACTIVITY, "core_activity"}, 62*d9a07880SDavid E. Box {PMT_CAP_PCPT_CACHE_PERF, "cache_performance"}, 63*d9a07880SDavid E. Box {PMT_CAP_PCPT_QUALITY_TELEM, "quality_telemetry"}, 64*d9a07880SDavid E. Box {} 65*d9a07880SDavid E. Box }; 66*d9a07880SDavid E. Box 67*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_pcpt[] = { 68*d9a07880SDavid E. Box pmt_cap_common, 69*d9a07880SDavid E. Box pmt_cap_pcpt, 70*d9a07880SDavid E. Box NULL 71*d9a07880SDavid E. Box }; 72*d9a07880SDavid E. Box 73*d9a07880SDavid E. Box struct pmt_cap pmt_cap_pcet[] = { 74*d9a07880SDavid E. Box {PMT_CAP_PCET_WORKPOINT_HIST, "workpoint_histogram"}, 75*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_CURR_TEMP, "core_current_temp"}, 76*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_INST_RES, "core_inst_residency"}, 77*d9a07880SDavid E. Box {PMT_CAP_PCET_QUALITY_TELEM, "quality_telemetry"}, 78*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_CDYN_LVL, "core_cdyn_level"}, 79*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_STRESS_LVL, "core_stress_level"}, 80*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_DAS, "core_digital_aging_sensor"}, 81*d9a07880SDavid E. Box {PMT_CAP_PCET_FIVR_HEALTH, "fivr_health"}, 82*d9a07880SDavid E. Box {PMT_CAP_PCET_ENERGY, "energy"}, 83*d9a07880SDavid E. Box {PMT_CAP_PCET_PEM_STATUS, "pem_status"}, 84*d9a07880SDavid E. Box {PMT_CAP_PCET_CORE_C_STATE, "core_c_state"}, 85*d9a07880SDavid E. Box {} 86*d9a07880SDavid E. Box }; 87*d9a07880SDavid E. Box 88*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_pcet[] = { 89*d9a07880SDavid E. Box pmt_cap_common, 90*d9a07880SDavid E. Box pmt_cap_pcet, 91*d9a07880SDavid E. Box NULL 92*d9a07880SDavid E. Box }; 93*d9a07880SDavid E. Box 94*d9a07880SDavid E. Box struct pmt_cap pmt_cap_rmid_perf[] = { 95*d9a07880SDavid E. Box {PMT_CAP_RMID_CORES_PERF, "core_performance"}, 96*d9a07880SDavid E. Box {PMT_CAP_RMID_CACHE_PERF, "cache_performance"}, 97*d9a07880SDavid E. Box {PMT_CAP_RMID_PERF_QUAL, "performance_quality"}, 98*d9a07880SDavid E. Box {} 99*d9a07880SDavid E. Box }; 100*d9a07880SDavid E. Box 101*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_rmid_perf[] = { 102*d9a07880SDavid E. Box pmt_cap_common, 103*d9a07880SDavid E. Box pmt_cap_rmid_perf, 104*d9a07880SDavid E. Box NULL 105*d9a07880SDavid E. Box }; 106*d9a07880SDavid E. Box 107*d9a07880SDavid E. Box struct pmt_cap pmt_cap_accel[] = { 108*d9a07880SDavid E. Box {PMT_CAP_ACCEL_CPM_TELEM, "content_processing_module"}, 109*d9a07880SDavid E. Box {PMT_CAP_ACCEL_TIP_TELEM, "content_turbo_ip"}, 110*d9a07880SDavid E. Box {} 111*d9a07880SDavid E. Box }; 112*d9a07880SDavid E. Box 113*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_accel[] = { 114*d9a07880SDavid E. Box pmt_cap_common, 115*d9a07880SDavid E. Box pmt_cap_accel, 116*d9a07880SDavid E. Box NULL 117*d9a07880SDavid E. Box }; 118*d9a07880SDavid E. Box 119*d9a07880SDavid E. Box struct pmt_cap pmt_cap_uncore[] = { 120*d9a07880SDavid E. Box {PMT_CAP_UNCORE_IO_CA_TELEM, "io_ca"}, 121*d9a07880SDavid E. Box {PMT_CAP_UNCORE_RMID_TELEM, "rmid"}, 122*d9a07880SDavid E. Box {PMT_CAP_UNCORE_D2D_ULA_TELEM, "d2d_ula"}, 123*d9a07880SDavid E. Box {PMT_CAP_UNCORE_PKGC_TELEM, "package_c"}, 124*d9a07880SDavid E. Box {} 125*d9a07880SDavid E. Box }; 126*d9a07880SDavid E. Box 127*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_uncore[] = { 128*d9a07880SDavid E. Box pmt_cap_common, 129*d9a07880SDavid E. Box pmt_cap_uncore, 130*d9a07880SDavid E. Box NULL 131*d9a07880SDavid E. Box }; 132*d9a07880SDavid E. Box 133*d9a07880SDavid E. Box struct pmt_cap pmt_cap_crashlog[] = { 134*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_MAN_TRIG, "manual_trigger"}, 135*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_CORE, "core"}, 136*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_UNCORE, "uncore"}, 137*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_TOR, "tor"}, 138*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_S3M, "s3m"}, 139*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_PERSISTENCY, "persistency"}, 140*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_CLIP_GPIO, "crashlog_in_progress"}, 141*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_PRE_RESET, "pre_reset_extraction"}, 142*d9a07880SDavid E. Box {PMT_CAP_CRASHLOG_POST_RESET, "post_reset_extraction"}, 143*d9a07880SDavid E. Box {} 144*d9a07880SDavid E. Box }; 145*d9a07880SDavid E. Box 146*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_crashlog[] = { 147*d9a07880SDavid E. Box pmt_cap_common, 148*d9a07880SDavid E. Box pmt_cap_crashlog, 149*d9a07880SDavid E. Box NULL 150*d9a07880SDavid E. Box }; 151*d9a07880SDavid E. Box 152*d9a07880SDavid E. Box struct pmt_cap pmt_cap_pete[] = { 153*d9a07880SDavid E. Box {PMT_CAP_PETE_MAN_TRIG, "manual_trigger"}, 154*d9a07880SDavid E. Box {PMT_CAP_PETE_ENCRYPTION, "encryption"}, 155*d9a07880SDavid E. Box {PMT_CAP_PETE_PERSISTENCY, "persistency"}, 156*d9a07880SDavid E. Box {PMT_CAP_PETE_REQ_TOKENS, "required_tokens"}, 157*d9a07880SDavid E. Box {PMT_CAP_PETE_PROD_ENABLED, "production_enabled"}, 158*d9a07880SDavid E. Box {PMT_CAP_PETE_DEBUG_ENABLED, "debug_enabled"}, 159*d9a07880SDavid E. Box {} 160*d9a07880SDavid E. Box }; 161*d9a07880SDavid E. Box 162*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_pete[] = { 163*d9a07880SDavid E. Box pmt_cap_common, 164*d9a07880SDavid E. Box pmt_cap_pete, 165*d9a07880SDavid E. Box NULL 166*d9a07880SDavid E. Box }; 167*d9a07880SDavid E. Box 168*d9a07880SDavid E. Box struct pmt_cap pmt_cap_tpmi[] = { 169*d9a07880SDavid E. Box {PMT_CAP_TPMI_MAILBOX, "mailbox"}, 170*d9a07880SDavid E. Box {PMT_CAP_TPMI_LOCK, "bios_lock"}, 171*d9a07880SDavid E. Box {} 172*d9a07880SDavid E. Box }; 173*d9a07880SDavid E. Box 174*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_tpmi[] = { 175*d9a07880SDavid E. Box pmt_cap_common, 176*d9a07880SDavid E. Box pmt_cap_tpmi, 177*d9a07880SDavid E. Box NULL 178*d9a07880SDavid E. Box }; 179*d9a07880SDavid E. Box 180*d9a07880SDavid E. Box struct pmt_cap pmt_cap_tracing[] = { 181*d9a07880SDavid E. Box {PMT_CAP_TRACE_SRAR, "srar_errors"}, 182*d9a07880SDavid E. Box {PMT_CAP_TRACE_CORRECTABLE, "correctable_errors"}, 183*d9a07880SDavid E. Box {PMT_CAP_TRACE_MCTP, "mctp"}, 184*d9a07880SDavid E. Box {PMT_CAP_TRACE_MRT, "memory_resiliency"}, 185*d9a07880SDavid E. Box {} 186*d9a07880SDavid E. Box }; 187*d9a07880SDavid E. Box 188*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_tracing[] = { 189*d9a07880SDavid E. Box pmt_cap_common, 190*d9a07880SDavid E. Box pmt_cap_tracing, 191*d9a07880SDavid E. Box NULL 192*d9a07880SDavid E. Box }; 193*d9a07880SDavid E. Box 194*d9a07880SDavid E. Box struct pmt_cap pmt_cap_rmid_energy[] = { 195*d9a07880SDavid E. Box {PMT_CAP_RMID_ENERGY, "energy"}, 196*d9a07880SDavid E. Box {PMT_CAP_RMID_ACTIVITY, "activity"}, 197*d9a07880SDavid E. Box {PMT_CAP_RMID_ENERGY_QUAL, "energy_quality"}, 198*d9a07880SDavid E. Box {} 199*d9a07880SDavid E. Box }; 200*d9a07880SDavid E. Box 201*d9a07880SDavid E. Box struct pmt_cap *pmt_caps_rmid_energy[] = { 202*d9a07880SDavid E. Box pmt_cap_common, 203*d9a07880SDavid E. Box pmt_cap_rmid_energy, 204*d9a07880SDavid E. Box NULL 205*d9a07880SDavid E. Box }; 206