1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Wildcat Lake PCH. 5 * 6 * Copyright (c) 2025, Intel Corporation. 7 */ 8 9 #include <linux/bits.h> 10 #include <linux/pci.h> 11 12 #include "core.h" 13 14 static const struct pmc_bit_map wcl_pcdn_pfear_map[] = { 15 {"PMC_0", BIT(0)}, 16 {"FUSE_OSSE", BIT(1)}, 17 {"ESPISPI", BIT(2)}, 18 {"XHCI", BIT(3)}, 19 {"SPA", BIT(4)}, 20 {"RSVD", BIT(5)}, 21 {"MPFPW2", BIT(6)}, 22 {"GBE", BIT(7)}, 23 24 {"SBR16B21", BIT(0)}, 25 {"SBR16B5", BIT(1)}, 26 {"SBR8B1", BIT(2)}, 27 {"SBR8B0", BIT(3)}, 28 {"P2SB0", BIT(4)}, 29 {"D2D_DISP_1", BIT(5)}, 30 {"LPSS", BIT(6)}, 31 {"LPC", BIT(7)}, 32 33 {"SMB", BIT(0)}, 34 {"ISH", BIT(1)}, 35 {"DBG_SBR16B", BIT(2)}, 36 {"NPK_0", BIT(3)}, 37 {"D2D_NOC_1", BIT(4)}, 38 {"FIA_P", BIT(5)}, 39 {"FUSE", BIT(6)}, 40 {"DBG_PSF", BIT(7)}, 41 42 {"DISP_PGA1", BIT(0)}, 43 {"XDCI", BIT(1)}, 44 {"EXI", BIT(2)}, 45 {"CSE", BIT(3)}, 46 {"KVMCC", BIT(4)}, 47 {"PMT", BIT(5)}, 48 {"CLINK", BIT(6)}, 49 {"PTIO", BIT(7)}, 50 51 {"USBR0", BIT(0)}, 52 {"SBR16B22", BIT(1)}, 53 {"SMT1", BIT(2)}, 54 {"MPFPW1", BIT(3)}, 55 {"SMS2", BIT(4)}, 56 {"SMS1", BIT(5)}, 57 {"CSMERTC", BIT(6)}, 58 {"CSMEPSF", BIT(7)}, 59 60 {"D2D_NOC_0", BIT(0)}, 61 {"ESE", BIT(1)}, 62 {"FIACPCB_P", BIT(2)}, 63 {"RSVD", BIT(3)}, 64 {"SBR8B2", BIT(4)}, 65 {"OSSE_SMT1", BIT(5)}, 66 {"D2D_DISP", BIT(6)}, 67 {"P2SB1", BIT(7)}, 68 69 {"U3FPW1", BIT(0)}, 70 {"SBR16B3", BIT(1)}, 71 {"PSF4", BIT(2)}, 72 {"CNVI", BIT(3)}, 73 {"UFSX2", BIT(4)}, 74 {"ENDBG", BIT(5)}, 75 {"DBC", BIT(6)}, 76 {"SBRG", BIT(7)}, 77 78 {"RSVD", BIT(0)}, 79 {"NPK1", BIT(1)}, 80 {"SBR16B7", BIT(2)}, 81 {"SBR16B4", BIT(3)}, 82 {"FIA_XG", BIT(4)}, 83 {"PSF6", BIT(5)}, 84 {"UFSPW1", BIT(6)}, 85 {"FIA_U", BIT(7)}, 86 87 {"PSF8", BIT(0)}, 88 {"PSF0", BIT(1)}, 89 {"RSVD", BIT(2)}, 90 {"FIACPCB_U", BIT(3)}, 91 {"TAM", BIT(4)}, 92 {"SBR16B0", BIT(5)}, 93 {"TBTLSX", BIT(6)}, 94 {"THC0", BIT(7)}, 95 96 {"THC1", BIT(0)}, 97 {"PMC_1", BIT(1)}, 98 {"FIACPCB_XG", BIT(2)}, 99 {"TCSS", BIT(3)}, 100 {"DISP_PGA", BIT(4)}, 101 {"SBR16B20", BIT(5)}, 102 {"SBR8B20", BIT(6)}, 103 {"DBG_SBR", BIT(7)}, 104 105 {"SPC", BIT(0)}, 106 {"ACE_0", BIT(1)}, 107 {"ACE_1", BIT(2)}, 108 {"ACE_2", BIT(3)}, 109 {"ACE_3", BIT(4)}, 110 {"ACE_4", BIT(5)}, 111 {"ACE_5", BIT(6)}, 112 {"ACE_6", BIT(7)}, 113 114 {"ACE_7", BIT(0)}, 115 {"ACE_8", BIT(1)}, 116 {"ACE_9", BIT(2)}, 117 {"ACE_10", BIT(3)}, 118 {"SBR16B2", BIT(4)}, 119 {"SBR8B4", BIT(5)}, 120 {"OSSE", BIT(6)}, 121 {"SBR16B1", BIT(7)}, 122 {} 123 }; 124 125 static const struct pmc_bit_map *ext_wcl_pcdn_pfear_map[] = { 126 wcl_pcdn_pfear_map, 127 NULL 128 }; 129 130 static const struct pmc_bit_map wcl_pcdn_ltr_show_map[] = { 131 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 132 {"RSVD", WCL_PMC_LTR_RESERVED}, 133 {"SATA", CNP_PMC_LTR_SATA}, 134 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 135 {"XHCI", CNP_PMC_LTR_XHCI}, 136 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 137 {"ME", CNP_PMC_LTR_ME}, 138 {"SATA1", CNP_PMC_LTR_EVA}, 139 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 140 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 141 {"CNV", CNP_PMC_LTR_CNV}, 142 {"LPSS", CNP_PMC_LTR_LPSS}, 143 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 144 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 145 {"SATA2", PTL_PMC_LTR_SATA2}, 146 {"ESPI", CNP_PMC_LTR_ESPI}, 147 {"SCC", CNP_PMC_LTR_SCC}, 148 {"ISH", CNP_PMC_LTR_ISH}, 149 {"UFSX2", CNP_PMC_LTR_UFSX2}, 150 {"EMMC", CNP_PMC_LTR_EMMC}, 151 {"WIGIG", ICL_PMC_LTR_WIGIG}, 152 {"THC0", TGL_PMC_LTR_THC0}, 153 {"THC1", TGL_PMC_LTR_THC1}, 154 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 155 {"ESE", MTL_PMC_LTR_ESE}, 156 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 157 {"DMI3", ARL_PMC_LTR_DMI3}, 158 {"OSSE", LNL_PMC_LTR_OSSE}, 159 160 /* Below two cannot be used for LTR_IGNORE */ 161 {"CURRENT_PLATFORM", PTL_PMC_LTR_CUR_PLT}, 162 {"AGGREGATED_SYSTEM", PTL_PMC_LTR_CUR_ASLT}, 163 {} 164 }; 165 166 static const struct pmc_bit_map wcl_pcdn_power_gating_status_0_map[] = { 167 {"PMC_PGD0_PG_STS", BIT(0), 0}, 168 {"FUSE_OSSE_PGD0_PG_STS", BIT(1), 0}, 169 {"ESPISPI_PGD0_PG_STS", BIT(2), 0}, 170 {"XHCI_PGD0_PG_STS", BIT(3), 1}, 171 {"SPA_PGD0_PG_STS", BIT(4), 1}, 172 {"RSVD_5", BIT(5), 0}, 173 {"MPFPW2_PGD0_PG_STS", BIT(6), 0}, 174 {"GBE_PGD0_PG_STS", BIT(7), 1}, 175 {"SBR16B21_PGD0_PG_STS", BIT(8), 0}, 176 {"SBR16B5_PGD0_PG_STS", BIT(9), 0}, 177 {"SBR8B1_PGD0_PG_STS", BIT(10), 0}, 178 {"SBR8B0_PGD0_PG_STS", BIT(11), 0}, 179 {"P2SB0_PG_STS", BIT(12), 1}, 180 {"D2D_DISP_PGD1_PG_STS", BIT(13), 0}, 181 {"LPSS_PGD0_PG_STS", BIT(14), 1}, 182 {"LPC_PGD0_PG_STS", BIT(15), 0}, 183 {"SMB_PGD0_PG_STS", BIT(16), 0}, 184 {"ISH_PGD0_PG_STS", BIT(17), 0}, 185 {"DBG_SBR16B_PGD0_PG_STS", BIT(18), 0}, 186 {"NPK_PGD0_PG_STS", BIT(19), 0}, 187 {"D2D_NOC_PGD1_PG_STS", BIT(20), 0}, 188 {"FIA_P_PGD0_PG_STS", BIT(21), 0}, 189 {"FUSE_PGD0_PG_STS", BIT(22), 0}, 190 {"DBG_PSF_PGD0_PG_STS", BIT(23), 0}, 191 {"DISP_PGA1_PGD0_PG_STS", BIT(24), 0}, 192 {"XDCI_PGD0_PG_STS", BIT(25), 1}, 193 {"EXI_PGD0_PG_STS", BIT(26), 0}, 194 {"CSE_PGD0_PG_STS", BIT(27), 1}, 195 {"KVMCC_PGD0_PG_STS", BIT(28), 1}, 196 {"PMT_PGD0_PG_STS", BIT(29), 1}, 197 {"CLINK_PGD0_PG_STS", BIT(30), 1}, 198 {"PTIO_PGD0_PG_STS", BIT(31), 1}, 199 {} 200 }; 201 202 static const struct pmc_bit_map wcl_pcdn_power_gating_status_1_map[] = { 203 {"USBR0_PGD0_PG_STS", BIT(0), 1}, 204 {"SBR16B22_PGD0_PG_STS", BIT(1), 0}, 205 {"SMT1_PGD0_PG_STS", BIT(2), 1}, 206 {"MPFPW1_PGD0_PG_STS", BIT(3), 0}, 207 {"SMS2_PGD0_PG_STS", BIT(4), 1}, 208 {"SMS1_PGD0_PG_STS", BIT(5), 1}, 209 {"CSMERTC_PGD0_PG_STS", BIT(6), 0}, 210 {"CSMEPSF_PGD0_PG_STS", BIT(7), 0}, 211 {"D2D_NOC_PGD0_PG_STS", BIT(8), 0}, 212 {"ESE_PGD0_PG_STS", BIT(9), 1}, 213 {"FIACPCB_P_PGD0_PG_STS", BIT(10), 0}, 214 {"SBR8B2_PGD0_PG_STS", BIT(12), 0}, 215 {"OSSE_SMT1_PGD0_PG_STS", BIT(13), 1}, 216 {"D2D_DISP_PGD0_PG_STS", BIT(14), 0}, 217 {"P2SB1_PGD0_PG_STS", BIT(15), 1}, 218 {"U3FPW1_PGD0_PG_STS", BIT(16), 0}, 219 {"SBR16B3_PGD0_PG_STS", BIT(17), 0}, 220 {"PSF4_PGD0_PG_STS", BIT(18), 0}, 221 {"CNVI_PGD0_PG_STS", BIT(19), 0}, 222 {"UFSX2_PGD0_PG_STS", BIT(20), 1}, 223 {"ENDBG_PGD0_PG_STS", BIT(21), 0}, 224 {"DBC_PGD0_PG_STS", BIT(22), 0}, 225 {"SBRG_PGD0_PG_STS", BIT(23), 0}, 226 {"NPK_PGD1_PG_STS", BIT(25), 0}, 227 {"SBR16B7_PGD0_PG_STS", BIT(26), 0}, 228 {"SBR16B4_PGD0_PG_STS", BIT(27), 0}, 229 {"FIA_XG_PSF_PGD0_PG_STS", BIT(28), 0}, 230 {"PSF6_PGD0_PG_STS", BIT(29), 0}, 231 {"UFSPW1_PGD0_PG_STS", BIT(30), 0}, 232 {"FIA_U_PGD0_PG_STS", BIT(31), 0}, 233 {} 234 }; 235 236 static const struct pmc_bit_map wcl_pcdn_power_gating_status_2_map[] = { 237 {"PSF8_PGD0_PG_STS", BIT(0), 0}, 238 {"PSF0_PGD0_PG_STS", BIT(1), 0}, 239 {"FIACPCB_U_PGD0_PG_STS", BIT(3), 0}, 240 {"TAM_PGD0_PG_STS", BIT(4), 1}, 241 {"SBR16B0_PGD0_PG_STS", BIT(5), 0}, 242 {"TBTLSX_PGD0_PG_STS", BIT(6), 1}, 243 {"THC0_PGD0_PG_STS", BIT(7), 1}, 244 {"THC1_PGD0_PG_STS", BIT(8), 1}, 245 {"PMC_PGD1_PG_STS", BIT(9), 0}, 246 {"FIACPCB_XG_PGD0_PG_STS", BIT(10), 0}, 247 {"TCSS_PGD0_PG_STS", BIT(11), 0}, 248 {"DISP_PGA_PGD0_PG_STS", BIT(12), 0}, 249 {"SBR8B4_PGD0_PG_STS", BIT(13), 0}, 250 {"SBR8B20_PGD0_PG_STS", BIT(14), 0}, 251 {"DBG_PGD0_PG_STS", BIT(15), 0}, 252 {"SPC_PGD0_PG_STS", BIT(16), 1}, 253 {"ACE_PGD0_PG_STS", BIT(17), 0}, 254 {"ACE_PGD1_PG_STS", BIT(18), 0}, 255 {"ACE_PGD2_PG_STS", BIT(19), 0}, 256 {"ACE_PGD3_PG_STS", BIT(20), 0}, 257 {"ACE_PGD4_PG_STS", BIT(21), 0}, 258 {"ACE_PGD5_PG_STS", BIT(22), 0}, 259 {"ACE_PGD6_PG_STS", BIT(23), 0}, 260 {"ACE_PGD7_PG_STS", BIT(24), 0}, 261 {"ACE_PGD8_PG_STS", BIT(25), 0}, 262 {"ACE_PGD9_PG_STS", BIT(26), 0}, 263 {"ACE_PGD10_PG_STS", BIT(27), 0}, 264 {"SBR16B2_PG_PGD0_PG_STS", BIT(28), 0}, 265 {"SBR16B20_PGD0_PG_STS", BIT(29), 0}, 266 {"OSSE_PGD0_PG_STS", BIT(30), 1}, 267 {"SBR16B1_PGD0_PG_STS", BIT(31), 0}, 268 {} 269 }; 270 271 static const struct pmc_bit_map wcl_pcdn_d3_status_0_map[] = { 272 {"LPSS_D3_STS", BIT(3), 1}, 273 {"XDCI_D3_STS", BIT(4), 1}, 274 {"XHCI_D3_STS", BIT(5), 1}, 275 {"SPA_D3_STS", BIT(12), 0}, 276 {"SPC_D3_STS", BIT(14), 0}, 277 {"OSSE_D3_STS", BIT(15), 0}, 278 {"ESPISPI_D3_STS", BIT(18), 0}, 279 {"PSTH_D3_STS", BIT(21), 0}, 280 {} 281 }; 282 283 static const struct pmc_bit_map wcl_pcdn_d3_status_1_map[] = { 284 {"OSSE_SMT1_D3_STS", BIT(16), 0}, 285 {"GBE_D3_STS", BIT(19), 0}, 286 {"ITSS_D3_STS", BIT(23), 0}, 287 {"CNVI_D3_STS", BIT(27), 0}, 288 {"UFSX2_D3_STS", BIT(28), 0}, 289 {} 290 }; 291 292 static const struct pmc_bit_map wcl_pcdn_d3_status_2_map[] = { 293 {"CSMERTC_D3_STS", BIT(1), 0}, 294 {"ESE_D3_STS", BIT(2), 0}, 295 {"CSE_D3_STS", BIT(4), 0}, 296 {"KVMCC_D3_STS", BIT(5), 0}, 297 {"USBR0_D3_STS", BIT(6), 0}, 298 {"ISH_D3_STS", BIT(7), 0}, 299 {"SMT1_D3_STS", BIT(8), 0}, 300 {"SMT2_D3_STS", BIT(9), 0}, 301 {"SMT3_D3_STS", BIT(10), 0}, 302 {"CLINK_D3_STS", BIT(14), 0}, 303 {"PTIO_D3_STS", BIT(16), 0}, 304 {"PMT_D3_STS", BIT(17), 0}, 305 {"SMS1_D3_STS", BIT(18), 0}, 306 {"SMS2_D3_STS", BIT(19), 0}, 307 {"OSSE_SMT2_D3_STS", BIT(22), 0}, 308 {} 309 }; 310 311 static const struct pmc_bit_map wcl_pcdn_d3_status_3_map[] = { 312 {"THC0_D3_STS", BIT(14), 1}, 313 {"THC1_D3_STS", BIT(15), 1}, 314 {"OSSE_SMT3_D3_STS", BIT(16), 0}, 315 {"ACE_D3_STS", BIT(23), 0}, 316 {} 317 }; 318 319 static const struct pmc_bit_map wcl_pcdn_vnn_req_status_0_map[] = { 320 {"LPSS_VNN_REQ_STS", BIT(3), 1}, 321 {"OSSE_VNN_REQ_STS", BIT(15), 1}, 322 {"ESPISPI_VNN_REQ_STS", BIT(18), 1}, 323 {} 324 }; 325 326 static const struct pmc_bit_map wcl_pcdn_vnn_req_status_1_map[] = { 327 {"NPK_VNN_REQ_STS", BIT(4), 1}, 328 {"DFXAGG_VNN_REQ_STS", BIT(8), 0}, 329 {"EXI_VNN_REQ_STS", BIT(9), 1}, 330 {"OSSE_SMT1_VNN_REQ_STS", BIT(16), 1}, 331 {"P2D_VNN_REQ_STS", BIT(18), 1}, 332 {"GBE_VNN_REQ_STS", BIT(19), 1}, 333 {"SMB_VNN_REQ_STS", BIT(25), 1}, 334 {"LPC_VNN_REQ_STS", BIT(26), 0}, 335 {} 336 }; 337 338 static const struct pmc_bit_map wcl_pcdn_vnn_req_status_2_map[] = { 339 {"CSMERTC_VNN_REQ_STS", BIT(1), 1}, 340 {"ESE_VNN_REQ_STS", BIT(2), 1}, 341 {"CSE_VNN_REQ_STS", BIT(4), 1}, 342 {"ISH_VNN_REQ_STS", BIT(7), 1}, 343 {"SMT1_VNN_REQ_STS", BIT(8), 1}, 344 {"CLINK_VNN_REQ_STS", BIT(14), 1}, 345 {"SMS1_VNN_REQ_STS", BIT(18), 1}, 346 {"SMS2_VNN_REQ_STS", BIT(19), 1}, 347 {"GPIOCOM4_VNN_REQ_STS", BIT(20), 1}, 348 {"GPIOCOM3_VNN_REQ_STS", BIT(21), 1}, 349 {"GPIOCOM1_VNN_REQ_STS", BIT(23), 1}, 350 {"GPIOCOM0_VNN_REQ_STS", BIT(24), 1}, 351 {"DISP_SHIM_VNN_REQ_STS", BIT(31), 1}, 352 {} 353 }; 354 355 static const struct pmc_bit_map wcl_pcdn_vnn_misc_status_map[] = { 356 {"CPU_C10_REQ_STS", BIT(0), 0}, 357 {"TS_OFF_REQ_STS", BIT(1), 0}, 358 {"PNDE_MET_REQ_STS", BIT(2), 1}, 359 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4), 0}, 360 {"VNN_SOC_REQ_STS", BIT(6), 1}, 361 {"ISH_VNNAON_REQ_STS", BIT(7), 0}, 362 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8), 1}, 363 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9), 1}, 364 {"PLT_GREATER_REQ_STS", BIT(11), 1}, 365 {"ALL_SBR_IDLE_REQ_STS", BIT(12), 0}, 366 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13), 0}, 367 {"PM_SYNC_STATES_REQ_STS", BIT(14), 0}, 368 {"EA_REQ_STS", BIT(15), 0}, 369 {"MPHY_CORE_OFF_REQ_STS", BIT(16), 0}, 370 {"BRK_EV_EN_REQ_STS", BIT(17), 0}, 371 {"AUTO_DEMO_EN_REQ_STS", BIT(18), 0}, 372 {"ITSS_CLK_SRC_REQ_STS", BIT(19), 1}, 373 {"ARC_IDLE_REQ_STS", BIT(21), 0}, 374 {"FIA_DEEP_PM_REQ_STS", BIT(23), 0}, 375 {"XDCI_ATTACHED_REQ_STS", BIT(24), 1}, 376 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25), 0}, 377 {"D2D_DISP_DDI_QACTIVE_REQ_STS", BIT(26), 1}, 378 {"PRE_WAKE0_REQ_STS", BIT(27), 1}, 379 {"PRE_WAKE1_REQ_STS", BIT(28), 1}, 380 {"PRE_WAKE2_REQ_STS", BIT(29), 1}, 381 {} 382 }; 383 384 static const struct pmc_bit_map wcl_pcdn_rsc_status_map[] = { 385 {"Memory", 0, 1}, 386 {"PSF0", 0, 1}, 387 {"PSF6", 0, 1}, 388 {"PSF8", 0, 1}, 389 {"SAF_CFI_LINK", 0, 1}, 390 {"SB", 0, 1}, 391 {} 392 }; 393 394 static const struct pmc_bit_map *wcl_pcdn_lpm_maps[] = { 395 ptl_pcdp_clocksource_status_map, 396 wcl_pcdn_power_gating_status_0_map, 397 wcl_pcdn_power_gating_status_1_map, 398 wcl_pcdn_power_gating_status_2_map, 399 wcl_pcdn_d3_status_0_map, 400 wcl_pcdn_d3_status_1_map, 401 wcl_pcdn_d3_status_2_map, 402 wcl_pcdn_d3_status_3_map, 403 wcl_pcdn_vnn_req_status_0_map, 404 wcl_pcdn_vnn_req_status_1_map, 405 wcl_pcdn_vnn_req_status_2_map, 406 ptl_pcdp_vnn_req_status_3_map, 407 wcl_pcdn_vnn_misc_status_map, 408 ptl_pcdp_signal_status_map, 409 NULL 410 }; 411 412 static const struct pmc_bit_map *wcl_pcdn_blk_maps[] = { 413 wcl_pcdn_power_gating_status_0_map, 414 wcl_pcdn_power_gating_status_1_map, 415 wcl_pcdn_power_gating_status_2_map, 416 wcl_pcdn_rsc_status_map, 417 wcl_pcdn_vnn_req_status_0_map, 418 wcl_pcdn_vnn_req_status_1_map, 419 wcl_pcdn_vnn_req_status_2_map, 420 ptl_pcdp_vnn_req_status_3_map, 421 wcl_pcdn_d3_status_0_map, 422 wcl_pcdn_d3_status_1_map, 423 wcl_pcdn_d3_status_2_map, 424 wcl_pcdn_d3_status_3_map, 425 ptl_pcdp_clocksource_status_map, 426 wcl_pcdn_vnn_misc_status_map, 427 ptl_pcdp_signal_status_map, 428 NULL 429 }; 430 431 static const struct pmc_reg_map wcl_pcdn_reg_map = { 432 .pfear_sts = ext_wcl_pcdn_pfear_map, 433 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 434 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 435 .ltr_show_sts = wcl_pcdn_ltr_show_map, 436 .msr_sts = msr_map, 437 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 438 .regmap_length = WCL_PCD_PMC_MMIO_REG_LEN, 439 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 440 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 441 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 442 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 443 .lpm_num_maps = PTL_LPM_NUM_MAPS, 444 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 445 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 446 .etr3_offset = ETR3_OFFSET, 447 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 448 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 449 .lpm_en_offset = MTL_LPM_EN_OFFSET, 450 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 451 .lpm_sts = wcl_pcdn_lpm_maps, 452 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 453 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 454 .s0ix_blocker_maps = wcl_pcdn_blk_maps, 455 .s0ix_blocker_offset = LNL_S0IX_BLOCKER_OFFSET, 456 }; 457 458 #define WCL_NPU_PCI_DEV 0xfd3e 459 460 /* 461 * Set power state of select devices that do not have drivers to D3 462 * so that they do not block Package C entry. 463 */ 464 static void wcl_d3_fixup(void) 465 { 466 pmc_core_set_device_d3(WCL_NPU_PCI_DEV); 467 } 468 469 static int wcl_resume(struct pmc_dev *pmcdev) 470 { 471 wcl_d3_fixup(); 472 return cnl_resume(pmcdev); 473 } 474 475 static int wcl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 476 { 477 wcl_d3_fixup(); 478 return generic_core_init(pmcdev, pmc_dev_info); 479 } 480 481 struct pmc_dev_info wcl_pmc_dev = { 482 .map = &wcl_pcdn_reg_map, 483 .suspend = cnl_suspend, 484 .resume = wcl_resume, 485 .init = wcl_core_init, 486 }; 487