xref: /linux/drivers/platform/x86/intel/pmc/ssram_telemetry.c (revision 4663747812d1a272312d1b95cbd128f0cdb329f2)
1e9f9cf3fSXi Pardee // SPDX-License-Identifier: GPL-2.0
2e9f9cf3fSXi Pardee /*
3b5d46539SXi Pardee  * Intel PMC SSRAM TELEMETRY PCI Driver
4e9f9cf3fSXi Pardee  *
5e9f9cf3fSXi Pardee  * Copyright (c) 2023, Intel Corporation.
6e9f9cf3fSXi Pardee  */
7e9f9cf3fSXi Pardee 
8e9f9cf3fSXi Pardee #include <linux/cleanup.h>
9e9f9cf3fSXi Pardee #include <linux/intel_vsec.h>
10e9f9cf3fSXi Pardee #include <linux/pci.h>
11b5d46539SXi Pardee #include <linux/types.h>
12e9f9cf3fSXi Pardee #include <linux/io-64-nonatomic-lo-hi.h>
13e9f9cf3fSXi Pardee 
14e9f9cf3fSXi Pardee #include "core.h"
15b5d46539SXi Pardee #include "ssram_telemetry.h"
16e9f9cf3fSXi Pardee 
17e9f9cf3fSXi Pardee #define SSRAM_HDR_SIZE		0x100
18e9f9cf3fSXi Pardee #define SSRAM_PWRM_OFFSET	0x14
19e9f9cf3fSXi Pardee #define SSRAM_DVSEC_OFFSET	0x1C
20e9f9cf3fSXi Pardee #define SSRAM_DVSEC_SIZE	0x10
21e9f9cf3fSXi Pardee #define SSRAM_PCH_OFFSET	0x60
22e9f9cf3fSXi Pardee #define SSRAM_IOE_OFFSET	0x68
23e9f9cf3fSXi Pardee #define SSRAM_DEVID_OFFSET	0x70
24e9f9cf3fSXi Pardee 
25b5d46539SXi Pardee DEFINE_FREE(pmc_ssram_telemetry_iounmap, void __iomem *, if (_T) iounmap(_T))
26e9f9cf3fSXi Pardee 
27b5d46539SXi Pardee static struct pmc_ssram_telemetry *pmc_ssram_telems;
28b5d46539SXi Pardee static bool device_probed;
29b5d46539SXi Pardee 
30b5d46539SXi Pardee static int
pmc_ssram_telemetry_add_pmt(struct pci_dev * pcidev,u64 ssram_base,void __iomem * ssram)31b5d46539SXi Pardee pmc_ssram_telemetry_add_pmt(struct pci_dev *pcidev, u64 ssram_base, void __iomem *ssram)
32e9f9cf3fSXi Pardee {
33e9f9cf3fSXi Pardee 	struct intel_vsec_platform_info info = {};
34e9f9cf3fSXi Pardee 	struct intel_vsec_header *headers[2] = {};
35e9f9cf3fSXi Pardee 	struct intel_vsec_header header;
36e9f9cf3fSXi Pardee 	void __iomem *dvsec;
37e9f9cf3fSXi Pardee 	u32 dvsec_offset;
38e9f9cf3fSXi Pardee 	u32 table, hdr;
39e9f9cf3fSXi Pardee 
40e9f9cf3fSXi Pardee 	dvsec_offset = readl(ssram + SSRAM_DVSEC_OFFSET);
41e9f9cf3fSXi Pardee 	dvsec = ioremap(ssram_base + dvsec_offset, SSRAM_DVSEC_SIZE);
42e9f9cf3fSXi Pardee 	if (!dvsec)
43b5d46539SXi Pardee 		return -ENOMEM;
44e9f9cf3fSXi Pardee 
45e9f9cf3fSXi Pardee 	hdr = readl(dvsec + PCI_DVSEC_HEADER1);
46e9f9cf3fSXi Pardee 	header.id = readw(dvsec + PCI_DVSEC_HEADER2);
47e9f9cf3fSXi Pardee 	header.rev = PCI_DVSEC_HEADER1_REV(hdr);
48e9f9cf3fSXi Pardee 	header.length = PCI_DVSEC_HEADER1_LEN(hdr);
49e9f9cf3fSXi Pardee 	header.num_entries = readb(dvsec + INTEL_DVSEC_ENTRIES);
50e9f9cf3fSXi Pardee 	header.entry_size = readb(dvsec + INTEL_DVSEC_SIZE);
51e9f9cf3fSXi Pardee 
52e9f9cf3fSXi Pardee 	table = readl(dvsec + INTEL_DVSEC_TABLE);
53e9f9cf3fSXi Pardee 	header.tbir = INTEL_DVSEC_TABLE_BAR(table);
54e9f9cf3fSXi Pardee 	header.offset = INTEL_DVSEC_TABLE_OFFSET(table);
55e9f9cf3fSXi Pardee 	iounmap(dvsec);
56e9f9cf3fSXi Pardee 
57e9f9cf3fSXi Pardee 	headers[0] = &header;
58e9f9cf3fSXi Pardee 	info.caps = VSEC_CAP_TELEMETRY;
59e9f9cf3fSXi Pardee 	info.headers = headers;
60e9f9cf3fSXi Pardee 	info.base_addr = ssram_base;
61b5d46539SXi Pardee 	info.parent = &pcidev->dev;
62e9f9cf3fSXi Pardee 
63b5d46539SXi Pardee 	return intel_vsec_register(pcidev, &info);
64e9f9cf3fSXi Pardee }
65e9f9cf3fSXi Pardee 
get_base(void __iomem * addr,u32 offset)66e9f9cf3fSXi Pardee static inline u64 get_base(void __iomem *addr, u32 offset)
67e9f9cf3fSXi Pardee {
68e9f9cf3fSXi Pardee 	return lo_hi_readq(addr + offset) & GENMASK_ULL(63, 3);
69e9f9cf3fSXi Pardee }
70e9f9cf3fSXi Pardee 
71e9f9cf3fSXi Pardee static int
pmc_ssram_telemetry_get_pmc(struct pci_dev * pcidev,unsigned int pmc_idx,u32 offset)72b5d46539SXi Pardee pmc_ssram_telemetry_get_pmc(struct pci_dev *pcidev, unsigned int pmc_idx, u32 offset)
73e9f9cf3fSXi Pardee {
74b5d46539SXi Pardee 	void __iomem __free(pmc_ssram_telemetry_iounmap) *tmp_ssram = NULL;
75b5d46539SXi Pardee 	void __iomem __free(pmc_ssram_telemetry_iounmap) *ssram = NULL;
76e9f9cf3fSXi Pardee 	u64 ssram_base, pwrm_base;
77e9f9cf3fSXi Pardee 	u16 devid;
78e9f9cf3fSXi Pardee 
79b5d46539SXi Pardee 	ssram_base = pci_resource_start(pcidev, 0);
80e9f9cf3fSXi Pardee 	tmp_ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);
81e9f9cf3fSXi Pardee 	if (!tmp_ssram)
82e9f9cf3fSXi Pardee 		return -ENOMEM;
83e9f9cf3fSXi Pardee 
84e9f9cf3fSXi Pardee 	if (pmc_idx != PMC_IDX_MAIN) {
85e9f9cf3fSXi Pardee 		/*
86e9f9cf3fSXi Pardee 		 * The secondary PMC BARS (which are behind hidden PCI devices)
87e9f9cf3fSXi Pardee 		 * are read from fixed offsets in MMIO of the primary PMC BAR.
88e9f9cf3fSXi Pardee 		 * If a device is not present, the value will be 0.
89e9f9cf3fSXi Pardee 		 */
90e9f9cf3fSXi Pardee 		ssram_base = get_base(tmp_ssram, offset);
91e9f9cf3fSXi Pardee 		if (!ssram_base)
92e9f9cf3fSXi Pardee 			return 0;
93e9f9cf3fSXi Pardee 
94e9f9cf3fSXi Pardee 		ssram = ioremap(ssram_base, SSRAM_HDR_SIZE);
95e9f9cf3fSXi Pardee 		if (!ssram)
96e9f9cf3fSXi Pardee 			return -ENOMEM;
97e9f9cf3fSXi Pardee 
98e9f9cf3fSXi Pardee 	} else {
99e9f9cf3fSXi Pardee 		ssram = no_free_ptr(tmp_ssram);
100e9f9cf3fSXi Pardee 	}
101e9f9cf3fSXi Pardee 
102e9f9cf3fSXi Pardee 	pwrm_base = get_base(ssram, SSRAM_PWRM_OFFSET);
103e9f9cf3fSXi Pardee 	devid = readw(ssram + SSRAM_DEVID_OFFSET);
104e9f9cf3fSXi Pardee 
105b5d46539SXi Pardee 	pmc_ssram_telems[pmc_idx].devid = devid;
106b5d46539SXi Pardee 	pmc_ssram_telems[pmc_idx].base_addr = pwrm_base;
107b5d46539SXi Pardee 
108e9f9cf3fSXi Pardee 	/* Find and register and PMC telemetry entries */
109b5d46539SXi Pardee 	return pmc_ssram_telemetry_add_pmt(pcidev, ssram_base, ssram);
110e9f9cf3fSXi Pardee }
111e9f9cf3fSXi Pardee 
112b5d46539SXi Pardee /**
113b5d46539SXi Pardee  * pmc_ssram_telemetry_get_pmc_info() - Get a PMC devid and base_addr information
114b5d46539SXi Pardee  * @pmc_idx:               Index of the PMC
115b5d46539SXi Pardee  * @pmc_ssram_telemetry:   pmc_ssram_telemetry structure to store the PMC information
116b5d46539SXi Pardee  *
117b5d46539SXi Pardee  * Return:
118b5d46539SXi Pardee  * * 0           - Success
119b5d46539SXi Pardee  * * -EAGAIN     - Probe function has not finished yet. Try again.
120b5d46539SXi Pardee  * * -EINVAL     - Invalid pmc_idx
121b5d46539SXi Pardee  * * -ENODEV     - PMC device is not available
122b5d46539SXi Pardee  */
pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx,struct pmc_ssram_telemetry * pmc_ssram_telemetry)123b5d46539SXi Pardee int pmc_ssram_telemetry_get_pmc_info(unsigned int pmc_idx,
124b5d46539SXi Pardee 				     struct pmc_ssram_telemetry *pmc_ssram_telemetry)
125e9f9cf3fSXi Pardee {
126b5d46539SXi Pardee 	/*
127b5d46539SXi Pardee 	 * PMCs are discovered in probe function. If this function is called before
128b5d46539SXi Pardee 	 * probe function complete, the result would be invalid. Use device_probed
129b5d46539SXi Pardee 	 * variable to avoid this case. Return -EAGAIN to inform the consumer to call
130b5d46539SXi Pardee 	 * again later.
131b5d46539SXi Pardee 	 */
132b5d46539SXi Pardee 	if (!device_probed)
133b5d46539SXi Pardee 		return -EAGAIN;
134b5d46539SXi Pardee 
135b5d46539SXi Pardee 	/*
136b5d46539SXi Pardee 	 * Memory barrier is used to ensure the correct read order between
137b5d46539SXi Pardee 	 * device_probed variable and PMC info.
138b5d46539SXi Pardee 	 */
139b5d46539SXi Pardee 	smp_rmb();
140b5d46539SXi Pardee 	if (pmc_idx >= MAX_NUM_PMC)
141b5d46539SXi Pardee 		return -EINVAL;
142b5d46539SXi Pardee 
143b5d46539SXi Pardee 	if (!pmc_ssram_telems || !pmc_ssram_telems[pmc_idx].devid)
144b5d46539SXi Pardee 		return -ENODEV;
145b5d46539SXi Pardee 
146b5d46539SXi Pardee 	pmc_ssram_telemetry->devid = pmc_ssram_telems[pmc_idx].devid;
147b5d46539SXi Pardee 	pmc_ssram_telemetry->base_addr = pmc_ssram_telems[pmc_idx].base_addr;
148b5d46539SXi Pardee 	return 0;
149b5d46539SXi Pardee }
150b5d46539SXi Pardee EXPORT_SYMBOL_GPL(pmc_ssram_telemetry_get_pmc_info);
151b5d46539SXi Pardee 
intel_pmc_ssram_telemetry_probe(struct pci_dev * pcidev,const struct pci_device_id * id)152b5d46539SXi Pardee static int intel_pmc_ssram_telemetry_probe(struct pci_dev *pcidev, const struct pci_device_id *id)
153b5d46539SXi Pardee {
154e9f9cf3fSXi Pardee 	int ret;
155e9f9cf3fSXi Pardee 
156b5d46539SXi Pardee 	pmc_ssram_telems = devm_kzalloc(&pcidev->dev, sizeof(*pmc_ssram_telems) * MAX_NUM_PMC,
157b5d46539SXi Pardee 					GFP_KERNEL);
158b5d46539SXi Pardee 	if (!pmc_ssram_telems) {
159b5d46539SXi Pardee 		ret = -ENOMEM;
160b5d46539SXi Pardee 		goto probe_finish;
161b5d46539SXi Pardee 	}
162e9f9cf3fSXi Pardee 
163e9f9cf3fSXi Pardee 	ret = pcim_enable_device(pcidev);
164b5d46539SXi Pardee 	if (ret) {
165b5d46539SXi Pardee 		dev_dbg(&pcidev->dev, "failed to enable PMC SSRAM device\n");
166b5d46539SXi Pardee 		goto probe_finish;
167b5d46539SXi Pardee 	}
168b5d46539SXi Pardee 
169b5d46539SXi Pardee 	ret = pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_MAIN, 0);
170e9f9cf3fSXi Pardee 	if (ret)
171b5d46539SXi Pardee 		goto probe_finish;
172e9f9cf3fSXi Pardee 
173b5d46539SXi Pardee 	pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_IOE, SSRAM_IOE_OFFSET);
174b5d46539SXi Pardee 	pmc_ssram_telemetry_get_pmc(pcidev, PMC_IDX_PCH, SSRAM_PCH_OFFSET);
175e9f9cf3fSXi Pardee 
176b5d46539SXi Pardee probe_finish:
177b5d46539SXi Pardee 	/*
178b5d46539SXi Pardee 	 * Memory barrier is used to ensure the correct write order between PMC info
179b5d46539SXi Pardee 	 * and device_probed variable.
180b5d46539SXi Pardee 	 */
181b5d46539SXi Pardee 	smp_wmb();
182b5d46539SXi Pardee 	device_probed = true;
183e9f9cf3fSXi Pardee 	return ret;
184e9f9cf3fSXi Pardee }
185b5d46539SXi Pardee 
186b5d46539SXi Pardee static const struct pci_device_id intel_pmc_ssram_telemetry_pci_ids[] = {
187b5d46539SXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_MTL_SOCM) },
188b5d46539SXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCS) },
189b5d46539SXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_ARL_SOCM) },
1902d5a84c3SXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_LNL_SOCM) },
191*be574d5eSXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDH) },
192*be574d5eSXi Pardee 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PMC_DEVID_PTL_PCDP) },
193b5d46539SXi Pardee 	{ }
194b5d46539SXi Pardee };
195b5d46539SXi Pardee MODULE_DEVICE_TABLE(pci, intel_pmc_ssram_telemetry_pci_ids);
196b5d46539SXi Pardee 
197b5d46539SXi Pardee static struct pci_driver intel_pmc_ssram_telemetry_driver = {
198b5d46539SXi Pardee 	.name = "intel_pmc_ssram_telemetry",
199b5d46539SXi Pardee 	.id_table = intel_pmc_ssram_telemetry_pci_ids,
200b5d46539SXi Pardee 	.probe = intel_pmc_ssram_telemetry_probe,
201b5d46539SXi Pardee };
202b5d46539SXi Pardee module_pci_driver(intel_pmc_ssram_telemetry_driver);
203b5d46539SXi Pardee 
204e9f9cf3fSXi Pardee MODULE_IMPORT_NS("INTEL_VSEC");
205b5d46539SXi Pardee MODULE_AUTHOR("Xi Pardee <xi.pardee@intel.com>");
206b5d46539SXi Pardee MODULE_DESCRIPTION("Intel PMC SSRAM Telemetry driver");
207b5d46539SXi Pardee MODULE_LICENSE("GPL");
208