1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Meteor Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include <linux/pci.h> 12 #include "core.h" 13 #include "../pmt/telemetry.h" 14 15 /* PMC SSRAM PMT Telemetry GUIDS */ 16 #define SOCP_LPM_REQ_GUID 0x2625030 17 #define IOEM_LPM_REQ_GUID 0x4357464 18 #define IOEP_LPM_REQ_GUID 0x5077612 19 20 static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; 21 22 /* 23 * Die Mapping to Product. 24 * Product SOCDie IOEDie PCHDie 25 * MTL-M SOC-M IOE-M None 26 * MTL-P SOC-M IOE-P None 27 * MTL-S SOC-S IOE-P PCH-S 28 */ 29 30 const struct pmc_bit_map mtl_socm_pfear_map[] = { 31 {"PMC", BIT(0)}, 32 {"OPI", BIT(1)}, 33 {"SPI", BIT(2)}, 34 {"XHCI", BIT(3)}, 35 {"SPA", BIT(4)}, 36 {"SPB", BIT(5)}, 37 {"SPC", BIT(6)}, 38 {"GBE", BIT(7)}, 39 40 {"SATA", BIT(0)}, 41 {"DSP0", BIT(1)}, 42 {"DSP1", BIT(2)}, 43 {"DSP2", BIT(3)}, 44 {"DSP3", BIT(4)}, 45 {"SPD", BIT(5)}, 46 {"LPSS", BIT(6)}, 47 {"LPC", BIT(7)}, 48 49 {"SMB", BIT(0)}, 50 {"ISH", BIT(1)}, 51 {"P2SB", BIT(2)}, 52 {"NPK_VNN", BIT(3)}, 53 {"SDX", BIT(4)}, 54 {"SPE", BIT(5)}, 55 {"FUSE", BIT(6)}, 56 {"SBR8", BIT(7)}, 57 58 {"RSVD24", BIT(0)}, 59 {"OTG", BIT(1)}, 60 {"EXI", BIT(2)}, 61 {"CSE", BIT(3)}, 62 {"CSME_KVM", BIT(4)}, 63 {"CSME_PMT", BIT(5)}, 64 {"CSME_CLINK", BIT(6)}, 65 {"CSME_PTIO", BIT(7)}, 66 67 {"CSME_USBR", BIT(0)}, 68 {"CSME_SUSRAM", BIT(1)}, 69 {"CSME_SMT1", BIT(2)}, 70 {"RSVD35", BIT(3)}, 71 {"CSME_SMS2", BIT(4)}, 72 {"CSME_SMS", BIT(5)}, 73 {"CSME_RTC", BIT(6)}, 74 {"CSME_PSF", BIT(7)}, 75 76 {"SBR0", BIT(0)}, 77 {"SBR1", BIT(1)}, 78 {"SBR2", BIT(2)}, 79 {"SBR3", BIT(3)}, 80 {"SBR4", BIT(4)}, 81 {"SBR5", BIT(5)}, 82 {"RSVD46", BIT(6)}, 83 {"PSF1", BIT(7)}, 84 85 {"PSF2", BIT(0)}, 86 {"PSF3", BIT(1)}, 87 {"PSF4", BIT(2)}, 88 {"CNVI", BIT(3)}, 89 {"UFSX2", BIT(4)}, 90 {"EMMC", BIT(5)}, 91 {"SPF", BIT(6)}, 92 {"SBR6", BIT(7)}, 93 94 {"SBR7", BIT(0)}, 95 {"NPK_AON", BIT(1)}, 96 {"HDA4", BIT(2)}, 97 {"HDA5", BIT(3)}, 98 {"HDA6", BIT(4)}, 99 {"PSF6", BIT(5)}, 100 {"RSVD62", BIT(6)}, 101 {"RSVD63", BIT(7)}, 102 {} 103 }; 104 105 const struct pmc_bit_map *ext_mtl_socm_pfear_map[] = { 106 mtl_socm_pfear_map, 107 NULL 108 }; 109 110 const struct pmc_bit_map mtl_socm_ltr_show_map[] = { 111 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 112 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 113 {"SATA", CNP_PMC_LTR_SATA}, 114 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 115 {"XHCI", CNP_PMC_LTR_XHCI}, 116 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 117 {"ME", CNP_PMC_LTR_ME}, 118 {"SATA1", CNP_PMC_LTR_EVA}, 119 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 120 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 121 {"CNV", CNP_PMC_LTR_CNV}, 122 {"LPSS", CNP_PMC_LTR_LPSS}, 123 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 124 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 125 {"SATA2", CNP_PMC_LTR_CAM}, 126 {"ESPI", CNP_PMC_LTR_ESPI}, 127 {"SCC", CNP_PMC_LTR_SCC}, 128 {"ISH", CNP_PMC_LTR_ISH}, 129 {"UFSX2", CNP_PMC_LTR_UFSX2}, 130 {"EMMC", CNP_PMC_LTR_EMMC}, 131 {"WIGIG", ICL_PMC_LTR_WIGIG}, 132 {"THC0", TGL_PMC_LTR_THC0}, 133 {"THC1", TGL_PMC_LTR_THC1}, 134 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 135 {"ESE", MTL_PMC_LTR_ESE}, 136 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 137 138 /* Below two cannot be used for LTR_IGNORE */ 139 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 140 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 141 {} 142 }; 143 144 const struct pmc_bit_map mtl_socm_clocksource_status_map[] = { 145 {"AON2_OFF_STS", BIT(0)}, 146 {"AON3_OFF_STS", BIT(1)}, 147 {"AON4_OFF_STS", BIT(2)}, 148 {"AON5_OFF_STS", BIT(3)}, 149 {"AON1_OFF_STS", BIT(4)}, 150 {"XTAL_LVM_OFF_STS", BIT(5)}, 151 {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, 152 {"MPFPW1_1_PLL_OFF_STS", BIT(7)}, 153 {"USB3_PLL_OFF_STS", BIT(8)}, 154 {"AON3_SPL_OFF_STS", BIT(9)}, 155 {"MPFPW2_0_PLL_OFF_STS", BIT(12)}, 156 {"MPFPW3_0_PLL_OFF_STS", BIT(13)}, 157 {"XTAL_AGGR_OFF_STS", BIT(17)}, 158 {"USB2_PLL_OFF_STS", BIT(18)}, 159 {"FILTER_PLL_OFF_STS", BIT(22)}, 160 {"ACE_PLL_OFF_STS", BIT(24)}, 161 {"FABRIC_PLL_OFF_STS", BIT(25)}, 162 {"SOC_PLL_OFF_STS", BIT(26)}, 163 {"PCIFAB_PLL_OFF_STS", BIT(27)}, 164 {"REF_PLL_OFF_STS", BIT(28)}, 165 {"IMG_PLL_OFF_STS", BIT(29)}, 166 {"RTC_PLL_OFF_STS", BIT(31)}, 167 {} 168 }; 169 170 const struct pmc_bit_map mtl_socm_power_gating_status_0_map[] = { 171 {"PMC_PGD0_PG_STS", BIT(0)}, 172 {"DMI_PGD0_PG_STS", BIT(1)}, 173 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 174 {"XHCI_PGD0_PG_STS", BIT(3)}, 175 {"SPA_PGD0_PG_STS", BIT(4)}, 176 {"SPB_PGD0_PG_STS", BIT(5)}, 177 {"SPC_PGD0_PG_STS", BIT(6)}, 178 {"GBE_PGD0_PG_STS", BIT(7)}, 179 {"SATA_PGD0_PG_STS", BIT(8)}, 180 {"PSF13_PGD0_PG_STS", BIT(9)}, 181 {"SOC_D2D_PGD3_PG_STS", BIT(10)}, 182 {"MPFPW3_PGD0_PG_STS", BIT(11)}, 183 {"ESE_PGD0_PG_STS", BIT(12)}, 184 {"SPD_PGD0_PG_STS", BIT(13)}, 185 {"LPSS_PGD0_PG_STS", BIT(14)}, 186 {"LPC_PGD0_PG_STS", BIT(15)}, 187 {"SMB_PGD0_PG_STS", BIT(16)}, 188 {"ISH_PGD0_PG_STS", BIT(17)}, 189 {"P2S_PGD0_PG_STS", BIT(18)}, 190 {"NPK_PGD0_PG_STS", BIT(19)}, 191 {"DBG_SBR_PGD0_PG_STS", BIT(20)}, 192 {"SBRG_PGD0_PG_STS", BIT(21)}, 193 {"FUSE_PGD0_PG_STS", BIT(22)}, 194 {"SBR8_PGD0_PG_STS", BIT(23)}, 195 {"SOC_D2D_PGD2_PG_STS", BIT(24)}, 196 {"XDCI_PGD0_PG_STS", BIT(25)}, 197 {"EXI_PGD0_PG_STS", BIT(26)}, 198 {"CSE_PGD0_PG_STS", BIT(27)}, 199 {"KVMCC_PGD0_PG_STS", BIT(28)}, 200 {"PMT_PGD0_PG_STS", BIT(29)}, 201 {"CLINK_PGD0_PG_STS", BIT(30)}, 202 {"PTIO_PGD0_PG_STS", BIT(31)}, 203 {} 204 }; 205 206 const struct pmc_bit_map mtl_socm_power_gating_status_1_map[] = { 207 {"USBR0_PGD0_PG_STS", BIT(0)}, 208 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 209 {"SMT1_PGD0_PG_STS", BIT(2)}, 210 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 211 {"SMS2_PGD0_PG_STS", BIT(4)}, 212 {"SMS1_PGD0_PG_STS", BIT(5)}, 213 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 214 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 215 {"SBR0_PGD0_PG_STS", BIT(8)}, 216 {"SBR1_PGD0_PG_STS", BIT(9)}, 217 {"SBR2_PGD0_PG_STS", BIT(10)}, 218 {"SBR3_PGD0_PG_STS", BIT(11)}, 219 {"U3FPW1_PGD0_PG_STS", BIT(12)}, 220 {"SBR5_PGD0_PG_STS", BIT(13)}, 221 {"MPFPW1_PGD0_PG_STS", BIT(14)}, 222 {"UFSPW1_PGD0_PG_STS", BIT(15)}, 223 {"FIA_X_PGD0_PG_STS", BIT(16)}, 224 {"SOC_D2D_PGD0_PG_STS", BIT(17)}, 225 {"MPFPW2_PGD0_PG_STS", BIT(18)}, 226 {"CNVI_PGD0_PG_STS", BIT(19)}, 227 {"UFSX2_PGD0_PG_STS", BIT(20)}, 228 {"ENDBG_PGD0_PG_STS", BIT(21)}, 229 {"DBG_PSF_PGD0_PG_STS", BIT(22)}, 230 {"SBR6_PGD0_PG_STS", BIT(23)}, 231 {"SBR7_PGD0_PG_STS", BIT(24)}, 232 {"NPK_PGD1_PG_STS", BIT(25)}, 233 {"FIACPCB_X_PGD0_PG_STS", BIT(26)}, 234 {"DBC_PGD0_PG_STS", BIT(27)}, 235 {"FUSEGPSB_PGD0_PG_STS", BIT(28)}, 236 {"PSF6_PGD0_PG_STS", BIT(29)}, 237 {"PSF7_PGD0_PG_STS", BIT(30)}, 238 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 239 {} 240 }; 241 242 const struct pmc_bit_map mtl_socm_power_gating_status_2_map[] = { 243 {"PSF8_PGD0_PG_STS", BIT(0)}, 244 {"FIA_PGD0_PG_STS", BIT(1)}, 245 {"SOC_D2D_PGD1_PG_STS", BIT(2)}, 246 {"FIA_U_PGD0_PG_STS", BIT(3)}, 247 {"TAM_PGD0_PG_STS", BIT(4)}, 248 {"GBETSN_PGD0_PG_STS", BIT(5)}, 249 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 250 {"THC0_PGD0_PG_STS", BIT(7)}, 251 {"THC1_PGD0_PG_STS", BIT(8)}, 252 {"PMC_PGD1_PG_STS", BIT(9)}, 253 {"GNA_PGD0_PG_STS", BIT(10)}, 254 {"ACE_PGD0_PG_STS", BIT(11)}, 255 {"ACE_PGD1_PG_STS", BIT(12)}, 256 {"ACE_PGD2_PG_STS", BIT(13)}, 257 {"ACE_PGD3_PG_STS", BIT(14)}, 258 {"ACE_PGD4_PG_STS", BIT(15)}, 259 {"ACE_PGD5_PG_STS", BIT(16)}, 260 {"ACE_PGD6_PG_STS", BIT(17)}, 261 {"ACE_PGD7_PG_STS", BIT(18)}, 262 {"ACE_PGD8_PG_STS", BIT(19)}, 263 {"FIA_PGS_PGD0_PG_STS", BIT(20)}, 264 {"FIACPCB_PGS_PGD0_PG_STS", BIT(21)}, 265 {"FUSEPMSB_PGD0_PG_STS", BIT(22)}, 266 {} 267 }; 268 269 const struct pmc_bit_map mtl_socm_d3_status_0_map[] = { 270 {"LPSS_D3_STS", BIT(3)}, 271 {"XDCI_D3_STS", BIT(4)}, 272 {"XHCI_D3_STS", BIT(5)}, 273 {"SPA_D3_STS", BIT(12)}, 274 {"SPB_D3_STS", BIT(13)}, 275 {"SPC_D3_STS", BIT(14)}, 276 {"SPD_D3_STS", BIT(15)}, 277 {"ESPISPI_D3_STS", BIT(18)}, 278 {"SATA_D3_STS", BIT(20)}, 279 {"PSTH_D3_STS", BIT(21)}, 280 {"DMI_D3_STS", BIT(22)}, 281 {} 282 }; 283 284 const struct pmc_bit_map mtl_socm_d3_status_1_map[] = { 285 {"GBETSN1_D3_STS", BIT(14)}, 286 {"GBE_D3_STS", BIT(19)}, 287 {"ITSS_D3_STS", BIT(23)}, 288 {"P2S_D3_STS", BIT(24)}, 289 {"CNVI_D3_STS", BIT(27)}, 290 {"UFSX2_D3_STS", BIT(28)}, 291 {} 292 }; 293 294 const struct pmc_bit_map mtl_socm_d3_status_2_map[] = { 295 {"GNA_D3_STS", BIT(0)}, 296 {"CSMERTC_D3_STS", BIT(1)}, 297 {"SUSRAM_D3_STS", BIT(2)}, 298 {"CSE_D3_STS", BIT(4)}, 299 {"KVMCC_D3_STS", BIT(5)}, 300 {"USBR0_D3_STS", BIT(6)}, 301 {"ISH_D3_STS", BIT(7)}, 302 {"SMT1_D3_STS", BIT(8)}, 303 {"SMT2_D3_STS", BIT(9)}, 304 {"SMT3_D3_STS", BIT(10)}, 305 {"CLINK_D3_STS", BIT(14)}, 306 {"PTIO_D3_STS", BIT(16)}, 307 {"PMT_D3_STS", BIT(17)}, 308 {"SMS1_D3_STS", BIT(18)}, 309 {"SMS2_D3_STS", BIT(19)}, 310 {} 311 }; 312 313 const struct pmc_bit_map mtl_socm_d3_status_3_map[] = { 314 {"ESE_D3_STS", BIT(2)}, 315 {"GBETSN_D3_STS", BIT(13)}, 316 {"THC0_D3_STS", BIT(14)}, 317 {"THC1_D3_STS", BIT(15)}, 318 {"ACE_D3_STS", BIT(23)}, 319 {} 320 }; 321 322 const struct pmc_bit_map mtl_socm_vnn_req_status_0_map[] = { 323 {"LPSS_VNN_REQ_STS", BIT(3)}, 324 {"FIA_VNN_REQ_STS", BIT(17)}, 325 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 326 {} 327 }; 328 329 const struct pmc_bit_map mtl_socm_vnn_req_status_1_map[] = { 330 {"NPK_VNN_REQ_STS", BIT(4)}, 331 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 332 {"EXI_VNN_REQ_STS", BIT(9)}, 333 {"P2D_VNN_REQ_STS", BIT(18)}, 334 {"GBE_VNN_REQ_STS", BIT(19)}, 335 {"SMB_VNN_REQ_STS", BIT(25)}, 336 {"LPC_VNN_REQ_STS", BIT(26)}, 337 {} 338 }; 339 340 const struct pmc_bit_map mtl_socm_vnn_req_status_2_map[] = { 341 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 342 {"CSE_VNN_REQ_STS", BIT(4)}, 343 {"ISH_VNN_REQ_STS", BIT(7)}, 344 {"SMT1_VNN_REQ_STS", BIT(8)}, 345 {"CLINK_VNN_REQ_STS", BIT(14)}, 346 {"SMS1_VNN_REQ_STS", BIT(18)}, 347 {"SMS2_VNN_REQ_STS", BIT(19)}, 348 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 349 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 350 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 351 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 352 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 353 {} 354 }; 355 356 const struct pmc_bit_map mtl_socm_vnn_req_status_3_map[] = { 357 {"ESE_VNN_REQ_STS", BIT(2)}, 358 {"DTS0_VNN_REQ_STS", BIT(7)}, 359 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 360 {} 361 }; 362 363 const struct pmc_bit_map mtl_socm_vnn_misc_status_map[] = { 364 {"CPU_C10_REQ_STS", BIT(0)}, 365 {"TS_OFF_REQ_STS", BIT(1)}, 366 {"PNDE_MET_REQ_STS", BIT(2)}, 367 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 368 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 369 {"NPK_VNNAON_REQ_STS", BIT(5)}, 370 {"VNN_SOC_REQ_STS", BIT(6)}, 371 {"ISH_VNNAON_REQ_STS", BIT(7)}, 372 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)}, 373 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)}, 374 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)}, 375 {"PLT_GREATER_REQ_STS", BIT(11)}, 376 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 377 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 378 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 379 {"EA_REQ_STS", BIT(15)}, 380 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 381 {"BRK_EV_EN_REQ_STS", BIT(17)}, 382 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 383 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 384 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 385 {"ARC_IDLE_REQ_STS", BIT(21)}, 386 {"MPHY_SUS_REQ_STS", BIT(22)}, 387 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 388 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 389 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 390 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 391 {"PRE_WAKE0_REQ_STS", BIT(27)}, 392 {"PRE_WAKE1_REQ_STS", BIT(28)}, 393 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 394 {"WOV_REQ_STS", BIT(30)}, 395 {"CNVI_V1P05_REQ_STS", BIT(31)}, 396 {} 397 }; 398 399 const struct pmc_bit_map mtl_socm_signal_status_map[] = { 400 {"LSX_Wake0_En_STS", BIT(0)}, 401 {"LSX_Wake0_Pol_STS", BIT(1)}, 402 {"LSX_Wake1_En_STS", BIT(2)}, 403 {"LSX_Wake1_Pol_STS", BIT(3)}, 404 {"LSX_Wake2_En_STS", BIT(4)}, 405 {"LSX_Wake2_Pol_STS", BIT(5)}, 406 {"LSX_Wake3_En_STS", BIT(6)}, 407 {"LSX_Wake3_Pol_STS", BIT(7)}, 408 {"LSX_Wake4_En_STS", BIT(8)}, 409 {"LSX_Wake4_Pol_STS", BIT(9)}, 410 {"LSX_Wake5_En_STS", BIT(10)}, 411 {"LSX_Wake5_Pol_STS", BIT(11)}, 412 {"LSX_Wake6_En_STS", BIT(12)}, 413 {"LSX_Wake6_Pol_STS", BIT(13)}, 414 {"LSX_Wake7_En_STS", BIT(14)}, 415 {"LSX_Wake7_Pol_STS", BIT(15)}, 416 {"LPSS_Wake0_En_STS", BIT(16)}, 417 {"LPSS_Wake0_Pol_STS", BIT(17)}, 418 {"LPSS_Wake1_En_STS", BIT(18)}, 419 {"LPSS_Wake1_Pol_STS", BIT(19)}, 420 {"Int_Timer_SS_Wake0_En_STS", BIT(20)}, 421 {"Int_Timer_SS_Wake0_Pol_STS", BIT(21)}, 422 {"Int_Timer_SS_Wake1_En_STS", BIT(22)}, 423 {"Int_Timer_SS_Wake1_Pol_STS", BIT(23)}, 424 {"Int_Timer_SS_Wake2_En_STS", BIT(24)}, 425 {"Int_Timer_SS_Wake2_Pol_STS", BIT(25)}, 426 {"Int_Timer_SS_Wake3_En_STS", BIT(26)}, 427 {"Int_Timer_SS_Wake3_Pol_STS", BIT(27)}, 428 {"Int_Timer_SS_Wake4_En_STS", BIT(28)}, 429 {"Int_Timer_SS_Wake4_Pol_STS", BIT(29)}, 430 {"Int_Timer_SS_Wake5_En_STS", BIT(30)}, 431 {"Int_Timer_SS_Wake5_Pol_STS", BIT(31)}, 432 {} 433 }; 434 435 const struct pmc_bit_map *mtl_socm_lpm_maps[] = { 436 mtl_socm_clocksource_status_map, 437 mtl_socm_power_gating_status_0_map, 438 mtl_socm_power_gating_status_1_map, 439 mtl_socm_power_gating_status_2_map, 440 mtl_socm_d3_status_0_map, 441 mtl_socm_d3_status_1_map, 442 mtl_socm_d3_status_2_map, 443 mtl_socm_d3_status_3_map, 444 mtl_socm_vnn_req_status_0_map, 445 mtl_socm_vnn_req_status_1_map, 446 mtl_socm_vnn_req_status_2_map, 447 mtl_socm_vnn_req_status_3_map, 448 mtl_socm_vnn_misc_status_map, 449 mtl_socm_signal_status_map, 450 NULL 451 }; 452 453 const struct pmc_reg_map mtl_socm_reg_map = { 454 .pfear_sts = ext_mtl_socm_pfear_map, 455 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 456 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 457 .ltr_show_sts = mtl_socm_ltr_show_map, 458 .msr_sts = msr_map, 459 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 460 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN, 461 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 462 .ppfear_buckets = MTL_SOCM_PPFEAR_NUM_ENTRIES, 463 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 464 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 465 .acpi_pm_tmr_ctl_offset = SPT_PMC_ACPI_PM_TMR_CTL_OFFSET, 466 .acpi_pm_tmr_disable_bit = SPT_PMC_BIT_ACPI_PM_TMR_DISABLE, 467 .lpm_num_maps = ADL_LPM_NUM_MAPS, 468 .ltr_ignore_max = MTL_SOCM_NUM_IP_IGN_ALLOWED, 469 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 470 .etr3_offset = ETR3_OFFSET, 471 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 472 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 473 .lpm_en_offset = MTL_LPM_EN_OFFSET, 474 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 475 .lpm_sts = mtl_socm_lpm_maps, 476 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 477 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 478 .lpm_reg_index = MTL_LPM_REG_INDEX, 479 }; 480 481 const struct pmc_bit_map mtl_ioep_pfear_map[] = { 482 {"PMC_0", BIT(0)}, 483 {"OPI", BIT(1)}, 484 {"TCSS", BIT(2)}, 485 {"RSVD3", BIT(3)}, 486 {"SPA", BIT(4)}, 487 {"SPB", BIT(5)}, 488 {"SPC", BIT(6)}, 489 {"IOE_D2D_3", BIT(7)}, 490 491 {"RSVD8", BIT(0)}, 492 {"RSVD9", BIT(1)}, 493 {"SPE", BIT(2)}, 494 {"RSVD11", BIT(3)}, 495 {"RSVD12", BIT(4)}, 496 {"SPD", BIT(5)}, 497 {"ACE_7", BIT(6)}, 498 {"RSVD15", BIT(7)}, 499 500 {"ACE_0", BIT(0)}, 501 {"FIACPCB_P", BIT(1)}, 502 {"P2S", BIT(2)}, 503 {"RSVD19", BIT(3)}, 504 {"ACE_8", BIT(4)}, 505 {"IOE_D2D_0", BIT(5)}, 506 {"FUSE", BIT(6)}, 507 {"RSVD23", BIT(7)}, 508 509 {"FIACPCB_P5", BIT(0)}, 510 {"ACE_3", BIT(1)}, 511 {"RSF5", BIT(2)}, 512 {"ACE_2", BIT(3)}, 513 {"ACE_4", BIT(4)}, 514 {"RSVD29", BIT(5)}, 515 {"RSF10", BIT(6)}, 516 {"MPFPW5", BIT(7)}, 517 518 {"PSF9", BIT(0)}, 519 {"MPFPW4", BIT(1)}, 520 {"RSVD34", BIT(2)}, 521 {"RSVD35", BIT(3)}, 522 {"RSVD36", BIT(4)}, 523 {"RSVD37", BIT(5)}, 524 {"RSVD38", BIT(6)}, 525 {"RSVD39", BIT(7)}, 526 527 {"SBR0", BIT(0)}, 528 {"SBR1", BIT(1)}, 529 {"SBR2", BIT(2)}, 530 {"SBR3", BIT(3)}, 531 {"SBR4", BIT(4)}, 532 {"SBR5", BIT(5)}, 533 {"RSVD46", BIT(6)}, 534 {"RSVD47", BIT(7)}, 535 536 {"RSVD48", BIT(0)}, 537 {"FIA_P5", BIT(1)}, 538 {"RSVD50", BIT(2)}, 539 {"RSVD51", BIT(3)}, 540 {"RSVD52", BIT(4)}, 541 {"RSVD53", BIT(5)}, 542 {"RSVD54", BIT(6)}, 543 {"ACE_1", BIT(7)}, 544 545 {"RSVD56", BIT(0)}, 546 {"ACE_5", BIT(1)}, 547 {"RSVD58", BIT(2)}, 548 {"G5FPW1", BIT(3)}, 549 {"RSVD60", BIT(4)}, 550 {"ACE_6", BIT(5)}, 551 {"RSVD62", BIT(6)}, 552 {"GBETSN1", BIT(7)}, 553 554 {"RSVD64", BIT(0)}, 555 {"FIA", BIT(1)}, 556 {"RSVD66", BIT(2)}, 557 {"FIA_P", BIT(3)}, 558 {"TAM", BIT(4)}, 559 {"GBETSN", BIT(5)}, 560 {"IOE_D2D_2", BIT(6)}, 561 {"IOE_D2D_1", BIT(7)}, 562 563 {"SPF", BIT(0)}, 564 {"PMC_1", BIT(1)}, 565 {} 566 }; 567 568 const struct pmc_bit_map *ext_mtl_ioep_pfear_map[] = { 569 mtl_ioep_pfear_map, 570 NULL 571 }; 572 573 const struct pmc_bit_map mtl_ioep_ltr_show_map[] = { 574 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 575 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 576 {"SATA", CNP_PMC_LTR_SATA}, 577 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 578 {"XHCI", CNP_PMC_LTR_XHCI}, 579 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 580 {"ME", CNP_PMC_LTR_ME}, 581 {"SATA1", CNP_PMC_LTR_EVA}, 582 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 583 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 584 {"CNV", CNP_PMC_LTR_CNV}, 585 {"LPSS", CNP_PMC_LTR_LPSS}, 586 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 587 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 588 {"SATA2", CNP_PMC_LTR_CAM}, 589 {"ESPI", CNP_PMC_LTR_ESPI}, 590 {"SCC", CNP_PMC_LTR_SCC}, 591 {"Reserved", MTL_PMC_LTR_RESERVED}, 592 {"UFSX2", CNP_PMC_LTR_UFSX2}, 593 {"EMMC", CNP_PMC_LTR_EMMC}, 594 {"WIGIG", ICL_PMC_LTR_WIGIG}, 595 {"THC0", TGL_PMC_LTR_THC0}, 596 {"THC1", TGL_PMC_LTR_THC1}, 597 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 598 599 /* Below two cannot be used for LTR_IGNORE */ 600 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 601 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 602 {} 603 }; 604 605 const struct pmc_bit_map mtl_ioep_clocksource_status_map[] = { 606 {"AON2_OFF_STS", BIT(0)}, 607 {"AON3_OFF_STS", BIT(1)}, 608 {"AON4_OFF_STS", BIT(2)}, 609 {"AON5_OFF_STS", BIT(3)}, 610 {"AON1_OFF_STS", BIT(4)}, 611 {"TBT_PLL_OFF_STS", BIT(5)}, 612 {"TMU_PLL_OFF_STS", BIT(6)}, 613 {"BCLK_PLL_OFF_STS", BIT(7)}, 614 {"D2D_PLL_OFF_STS", BIT(8)}, 615 {"AON3_SPL_OFF_STS", BIT(9)}, 616 {"MPFPW4_0_PLL_OFF_STS", BIT(12)}, 617 {"MPFPW5_0_PLL_OFF_STS", BIT(13)}, 618 {"G5FPW_0_PLL_OFF_STS", BIT(14)}, 619 {"G5FPW_1_PLL_OFF_STS", BIT(15)}, 620 {"XTAL_AGGR_OFF_STS", BIT(17)}, 621 {"FABRIC_PLL_OFF_STS", BIT(25)}, 622 {"SOC_PLL_OFF_STS", BIT(26)}, 623 {"REF_PLL_OFF_STS", BIT(28)}, 624 {"RTC_PLL_OFF_STS", BIT(31)}, 625 {} 626 }; 627 628 const struct pmc_bit_map mtl_ioep_power_gating_status_0_map[] = { 629 {"PMC_PGD0_PG_STS", BIT(0)}, 630 {"DMI_PGD0_PG_STS", BIT(1)}, 631 {"TCSS_PGD0_PG_STS", BIT(2)}, 632 {"SPA_PGD0_PG_STS", BIT(4)}, 633 {"SPB_PGD0_PG_STS", BIT(5)}, 634 {"SPC_PGD0_PG_STS", BIT(6)}, 635 {"IOE_D2D_PGD3_PG_STS", BIT(7)}, 636 {"SPE_PGD0_PG_STS", BIT(10)}, 637 {"SPD_PGD0_PG_STS", BIT(13)}, 638 {"ACE_PGD7_PG_STS", BIT(14)}, 639 {"ACE_PGD0_PG_STS", BIT(16)}, 640 {"FIACPCB_P_PGD0_PG_STS", BIT(17)}, 641 {"P2S_PGD0_PG_STS", BIT(18)}, 642 {"ACE_PGD8_PG_STS", BIT(20)}, 643 {"IOE_D2D_PGD0_PG_STS", BIT(21)}, 644 {"FUSE_PGD0_PG_STS", BIT(22)}, 645 {"FIACPCB_P5_PGD0_PG_STS", BIT(24)}, 646 {"ACE_PGD3_PG_STS", BIT(25)}, 647 {"PSF5_PGD0_PG_STS", BIT(26)}, 648 {"ACE_PGD2_PG_STS", BIT(27)}, 649 {"ACE_PGD4_PG_STS", BIT(28)}, 650 {"PSF10_PGD0_PG_STS", BIT(30)}, 651 {"MPFPW5_PGD0_PG_STS", BIT(31)}, 652 {} 653 }; 654 655 const struct pmc_bit_map mtl_ioep_power_gating_status_1_map[] = { 656 {"PSF9_PGD0_PG_STS", BIT(0)}, 657 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 658 {"SBR0_PGD0_PG_STS", BIT(8)}, 659 {"SBR1_PGD0_PG_STS", BIT(9)}, 660 {"SBR2_PGD0_PG_STS", BIT(10)}, 661 {"SBR3_PGD0_PG_STS", BIT(11)}, 662 {"SBR4_PGD0_PG_STS", BIT(12)}, 663 {"SBR5_PGD0_PG_STS", BIT(13)}, 664 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 665 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 666 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 667 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 668 {"ACE_PGD6_PG_STS", BIT(29)}, 669 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 670 {} 671 }; 672 673 const struct pmc_bit_map mtl_ioep_power_gating_status_2_map[] = { 674 {"FIA_PGD0_PG_STS", BIT(1)}, 675 {"FIA_P_PGD0_PG_STS", BIT(3)}, 676 {"TAM_PGD0_PG_STS", BIT(4)}, 677 {"GBETSN_PGD0_PG_STS", BIT(5)}, 678 {"IOE_D2D_PGD2_PG_STS", BIT(6)}, 679 {"IOE_D2D_PGD1_PG_STS", BIT(7)}, 680 {"SPF_PGD0_PG_STS", BIT(8)}, 681 {"PMC_PGD1_PG_STS", BIT(9)}, 682 {} 683 }; 684 685 const struct pmc_bit_map mtl_ioep_d3_status_0_map[] = { 686 {"SPF_D3_STS", BIT(0)}, 687 {"SPA_D3_STS", BIT(12)}, 688 {"SPB_D3_STS", BIT(13)}, 689 {"SPC_D3_STS", BIT(14)}, 690 {"SPD_D3_STS", BIT(15)}, 691 {"SPE_D3_STS", BIT(16)}, 692 {"DMI_D3_STS", BIT(22)}, 693 {} 694 }; 695 696 const struct pmc_bit_map mtl_ioep_d3_status_1_map[] = { 697 {"GBETSN1_D3_STS", BIT(14)}, 698 {"P2S_D3_STS", BIT(24)}, 699 {} 700 }; 701 702 const struct pmc_bit_map mtl_ioep_d3_status_2_map[] = { 703 {} 704 }; 705 706 const struct pmc_bit_map mtl_ioep_d3_status_3_map[] = { 707 {"GBETSN_D3_STS", BIT(13)}, 708 {"ACE_D3_STS", BIT(23)}, 709 {} 710 }; 711 712 const struct pmc_bit_map mtl_ioep_vnn_req_status_0_map[] = { 713 {"FIA_VNN_REQ_STS", BIT(17)}, 714 {} 715 }; 716 717 const struct pmc_bit_map mtl_ioep_vnn_req_status_1_map[] = { 718 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 719 {} 720 }; 721 722 const struct pmc_bit_map mtl_ioep_vnn_req_status_2_map[] = { 723 {} 724 }; 725 726 const struct pmc_bit_map mtl_ioep_vnn_req_status_3_map[] = { 727 {"DTS0_VNN_REQ_STS", BIT(7)}, 728 {"DISP_VNN_REQ_STS", BIT(19)}, 729 {} 730 }; 731 732 const struct pmc_bit_map mtl_ioep_vnn_misc_status_map[] = { 733 {"CPU_C10_REQ_STS", BIT(0)}, 734 {"TS_OFF_REQ_STS", BIT(1)}, 735 {"PNDE_MET_REQ_STS", BIT(2)}, 736 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 737 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 738 {"NPK_VNNAON_REQ_STS", BIT(5)}, 739 {"VNN_SOC_REQ_STS", BIT(6)}, 740 {"USB_DEVICE_ATTACHED_REQ_STS", BIT(8)}, 741 {"FIA_EXIT_REQ_STS", BIT(9)}, 742 {"USB2_SUS_PG_REQ_STS", BIT(10)}, 743 {"PLT_GREATER_REQ_STS", BIT(11)}, 744 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 745 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 746 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 747 {"EA_REQ_STS", BIT(15)}, 748 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 749 {"BRK_EV_EN_REQ_STS", BIT(17)}, 750 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 751 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 752 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 753 {"ARC_IDLE_REQ_STS", BIT(21)}, 754 {"MPHY_SUS_REQ_STS", BIT(22)}, 755 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 756 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 757 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 758 {"USB2_VNNAON_ACT_REQ_STS", BIT(26)}, 759 {"PRE_WAKE0_REQ_STS", BIT(27)}, 760 {"PRE_WAKE1_REQ_STS", BIT(28)}, 761 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 762 {"WOV_REQ_STS", BIT(30)}, 763 {"CNVI_V1P05_REQ_STS", BIT(31)}, 764 {} 765 }; 766 767 const struct pmc_bit_map *mtl_ioep_lpm_maps[] = { 768 mtl_ioep_clocksource_status_map, 769 mtl_ioep_power_gating_status_0_map, 770 mtl_ioep_power_gating_status_1_map, 771 mtl_ioep_power_gating_status_2_map, 772 mtl_ioep_d3_status_0_map, 773 mtl_ioep_d3_status_1_map, 774 mtl_ioep_d3_status_2_map, 775 mtl_ioep_d3_status_3_map, 776 mtl_ioep_vnn_req_status_0_map, 777 mtl_ioep_vnn_req_status_1_map, 778 mtl_ioep_vnn_req_status_2_map, 779 mtl_ioep_vnn_req_status_3_map, 780 mtl_ioep_vnn_misc_status_map, 781 mtl_socm_signal_status_map, 782 NULL 783 }; 784 785 const struct pmc_reg_map mtl_ioep_reg_map = { 786 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 787 .pfear_sts = ext_mtl_ioep_pfear_map, 788 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 789 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 790 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 791 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 792 .lpm_sts = mtl_ioep_lpm_maps, 793 .ltr_show_sts = mtl_ioep_ltr_show_map, 794 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 795 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 796 .lpm_num_maps = ADL_LPM_NUM_MAPS, 797 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 798 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 799 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 800 .lpm_en_offset = MTL_LPM_EN_OFFSET, 801 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 802 .lpm_reg_index = MTL_LPM_REG_INDEX, 803 }; 804 805 const struct pmc_bit_map mtl_ioem_pfear_map[] = { 806 {"PMC_0", BIT(0)}, 807 {"OPI", BIT(1)}, 808 {"TCSS", BIT(2)}, 809 {"RSVD3", BIT(3)}, 810 {"SPA", BIT(4)}, 811 {"SPB", BIT(5)}, 812 {"SPC", BIT(6)}, 813 {"IOE_D2D_3", BIT(7)}, 814 815 {"RSVD8", BIT(0)}, 816 {"RSVD9", BIT(1)}, 817 {"SPE", BIT(2)}, 818 {"RSVD11", BIT(3)}, 819 {"RSVD12", BIT(4)}, 820 {"SPD", BIT(5)}, 821 {"ACE_7", BIT(6)}, 822 {"RSVD15", BIT(7)}, 823 824 {"ACE_0", BIT(0)}, 825 {"FIACPCB_P", BIT(1)}, 826 {"P2S", BIT(2)}, 827 {"RSVD19", BIT(3)}, 828 {"ACE_8", BIT(4)}, 829 {"IOE_D2D_0", BIT(5)}, 830 {"FUSE", BIT(6)}, 831 {"RSVD23", BIT(7)}, 832 833 {"FIACPCB_P5", BIT(0)}, 834 {"ACE_3", BIT(1)}, 835 {"RSF5", BIT(2)}, 836 {"ACE_2", BIT(3)}, 837 {"ACE_4", BIT(4)}, 838 {"RSVD29", BIT(5)}, 839 {"RSF10", BIT(6)}, 840 {"MPFPW5", BIT(7)}, 841 842 {"PSF9", BIT(0)}, 843 {"MPFPW4", BIT(1)}, 844 {"RSVD34", BIT(2)}, 845 {"RSVD35", BIT(3)}, 846 {"RSVD36", BIT(4)}, 847 {"RSVD37", BIT(5)}, 848 {"RSVD38", BIT(6)}, 849 {"RSVD39", BIT(7)}, 850 851 {"SBR0", BIT(0)}, 852 {"SBR1", BIT(1)}, 853 {"SBR2", BIT(2)}, 854 {"SBR3", BIT(3)}, 855 {"SBR4", BIT(4)}, 856 {"RSVD45", BIT(5)}, 857 {"RSVD46", BIT(6)}, 858 {"RSVD47", BIT(7)}, 859 860 {"RSVD48", BIT(0)}, 861 {"FIA_P5", BIT(1)}, 862 {"RSVD50", BIT(2)}, 863 {"RSVD51", BIT(3)}, 864 {"RSVD52", BIT(4)}, 865 {"RSVD53", BIT(5)}, 866 {"RSVD54", BIT(6)}, 867 {"ACE_1", BIT(7)}, 868 869 {"RSVD56", BIT(0)}, 870 {"ACE_5", BIT(1)}, 871 {"RSVD58", BIT(2)}, 872 {"G5FPW1", BIT(3)}, 873 {"RSVD60", BIT(4)}, 874 {"ACE_6", BIT(5)}, 875 {"RSVD62", BIT(6)}, 876 {"GBETSN1", BIT(7)}, 877 878 {"RSVD64", BIT(0)}, 879 {"FIA", BIT(1)}, 880 {"RSVD66", BIT(2)}, 881 {"FIA_P", BIT(3)}, 882 {"TAM", BIT(4)}, 883 {"GBETSN", BIT(5)}, 884 {"IOE_D2D_2", BIT(6)}, 885 {"IOE_D2D_1", BIT(7)}, 886 887 {"SPF", BIT(0)}, 888 {"PMC_1", BIT(1)}, 889 {} 890 }; 891 892 const struct pmc_bit_map *ext_mtl_ioem_pfear_map[] = { 893 mtl_ioem_pfear_map, 894 NULL 895 }; 896 897 const struct pmc_bit_map mtl_ioem_power_gating_status_1_map[] = { 898 {"PSF9_PGD0_PG_STS", BIT(0)}, 899 {"MPFPW4_PGD0_PG_STS", BIT(1)}, 900 {"SBR0_PGD0_PG_STS", BIT(8)}, 901 {"SBR1_PGD0_PG_STS", BIT(9)}, 902 {"SBR2_PGD0_PG_STS", BIT(10)}, 903 {"SBR3_PGD0_PG_STS", BIT(11)}, 904 {"SBR4_PGD0_PG_STS", BIT(12)}, 905 {"FIA_P5_PGD0_PG_STS", BIT(17)}, 906 {"ACE_PGD1_PGD0_PG_STS", BIT(23)}, 907 {"ACE_PGD5_PGD1_PG_STS", BIT(25)}, 908 {"G5FPW1_PGD0_PG_STS", BIT(27)}, 909 {"ACE_PGD6_PG_STS", BIT(29)}, 910 {"GBETSN1_PGD0_PG_STS", BIT(31)}, 911 {} 912 }; 913 914 const struct pmc_bit_map *mtl_ioem_lpm_maps[] = { 915 mtl_ioep_clocksource_status_map, 916 mtl_ioep_power_gating_status_0_map, 917 mtl_ioem_power_gating_status_1_map, 918 mtl_ioep_power_gating_status_2_map, 919 mtl_ioep_d3_status_0_map, 920 mtl_ioep_d3_status_1_map, 921 mtl_ioep_d3_status_2_map, 922 mtl_ioep_d3_status_3_map, 923 mtl_ioep_vnn_req_status_0_map, 924 mtl_ioep_vnn_req_status_1_map, 925 mtl_ioep_vnn_req_status_2_map, 926 mtl_ioep_vnn_req_status_3_map, 927 mtl_ioep_vnn_misc_status_map, 928 mtl_socm_signal_status_map, 929 NULL 930 }; 931 932 const struct pmc_reg_map mtl_ioem_reg_map = { 933 .regmap_length = MTL_IOE_PMC_MMIO_REG_LEN, 934 .pfear_sts = ext_mtl_ioem_pfear_map, 935 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 936 .ppfear_buckets = MTL_IOE_PPFEAR_NUM_ENTRIES, 937 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 938 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 939 .lpm_sts = mtl_ioem_lpm_maps, 940 .ltr_show_sts = mtl_ioep_ltr_show_map, 941 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 942 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 943 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 944 .lpm_num_maps = ADL_LPM_NUM_MAPS, 945 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 946 .lpm_en_offset = MTL_LPM_EN_OFFSET, 947 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 948 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 949 .lpm_reg_index = MTL_LPM_REG_INDEX, 950 }; 951 952 #define PMC_DEVID_SOCM 0x7e7f 953 #define PMC_DEVID_IOEP 0x7ecf 954 #define PMC_DEVID_IOEM 0x7ebf 955 static struct pmc_info mtl_pmc_info_list[] = { 956 { 957 .guid = SOCP_LPM_REQ_GUID, 958 .devid = PMC_DEVID_SOCM, 959 .map = &mtl_socm_reg_map, 960 }, 961 { 962 .guid = IOEP_LPM_REQ_GUID, 963 .devid = PMC_DEVID_IOEP, 964 .map = &mtl_ioep_reg_map, 965 }, 966 { 967 .guid = IOEM_LPM_REQ_GUID, 968 .devid = PMC_DEVID_IOEM, 969 .map = &mtl_ioem_reg_map 970 }, 971 {} 972 }; 973 974 #define MTL_GNA_PCI_DEV 0x7e4c 975 #define MTL_IPU_PCI_DEV 0x7d19 976 #define MTL_VPU_PCI_DEV 0x7d1d 977 /* 978 * Set power state of select devices that do not have drivers to D3 979 * so that they do not block Package C entry. 980 */ 981 static void mtl_d3_fixup(void) 982 { 983 pmc_core_set_device_d3(MTL_GNA_PCI_DEV); 984 pmc_core_set_device_d3(MTL_IPU_PCI_DEV); 985 pmc_core_set_device_d3(MTL_VPU_PCI_DEV); 986 } 987 988 static int mtl_resume(struct pmc_dev *pmcdev) 989 { 990 mtl_d3_fixup(); 991 pmc_core_send_ltr_ignore(pmcdev, 3, 0); 992 993 return pmc_core_resume_common(pmcdev); 994 } 995 996 int mtl_core_init(struct pmc_dev *pmcdev) 997 { 998 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; 999 int ret; 1000 int func = 2; 1001 bool ssram_init = true; 1002 1003 mtl_d3_fixup(); 1004 1005 pmcdev->suspend = cnl_suspend; 1006 pmcdev->resume = mtl_resume; 1007 pmcdev->regmap_list = mtl_pmc_info_list; 1008 1009 /* 1010 * If ssram init fails use legacy method to at least get the 1011 * primary PMC 1012 */ 1013 ret = pmc_core_ssram_init(pmcdev, func); 1014 if (ret) { 1015 ssram_init = false; 1016 dev_warn(&pmcdev->pdev->dev, 1017 "ssram init failed, %d, using legacy init\n", ret); 1018 pmc->map = &mtl_socm_reg_map; 1019 ret = get_primary_reg_base(pmc); 1020 if (ret) 1021 return ret; 1022 } 1023 1024 pmc_core_get_low_power_modes(pmcdev); 1025 pmc_core_punit_pmt_init(pmcdev, MTL_PMT_DMU_GUID); 1026 1027 if (ssram_init) 1028 return pmc_core_ssram_get_lpm_reqs(pmcdev); 1029 1030 return 0; 1031 } 1032