1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Meteor Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include <linux/cpu.h> 12 #include <linux/pci.h> 13 14 #include "core.h" 15 16 #define SOCM_LPM_REQ_GUID 0x11594920 17 18 #define PMC_DEVID_SOCM 0xa87f 19 20 static const u8 LNL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; 21 22 static struct pmc_info lnl_pmc_info_list[] = { 23 { 24 .guid = SOCM_LPM_REQ_GUID, 25 .devid = PMC_DEVID_SOCM, 26 .map = &lnl_socm_reg_map, 27 }, 28 {} 29 }; 30 31 const struct pmc_bit_map lnl_ltr_show_map[] = { 32 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 33 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 34 {"SATA", CNP_PMC_LTR_SATA}, 35 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 36 {"XHCI", CNP_PMC_LTR_XHCI}, 37 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 38 {"ME", CNP_PMC_LTR_ME}, 39 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 40 {"SATA1", CNP_PMC_LTR_EVA}, 41 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 42 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 43 {"CNV", CNP_PMC_LTR_CNV}, 44 {"LPSS", CNP_PMC_LTR_LPSS}, 45 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 46 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 47 {"SATA2", CNP_PMC_LTR_CAM}, 48 {"ESPI", CNP_PMC_LTR_ESPI}, 49 {"SCC", CNP_PMC_LTR_SCC}, 50 {"ISH", CNP_PMC_LTR_ISH}, 51 {"UFSX2", CNP_PMC_LTR_UFSX2}, 52 {"EMMC", CNP_PMC_LTR_EMMC}, 53 /* 54 * Check intel_pmc_core_ids[] users of cnp_reg_map for 55 * a list of core SoCs using this. 56 */ 57 {"WIGIG", ICL_PMC_LTR_WIGIG}, 58 {"THC0", TGL_PMC_LTR_THC0}, 59 {"THC1", TGL_PMC_LTR_THC1}, 60 {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, 61 62 {"ESE", MTL_PMC_LTR_ESE}, 63 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 64 {"DMI3", ARL_PMC_LTR_DMI3}, 65 {"OSSE", LNL_PMC_LTR_OSSE}, 66 67 /* Below two cannot be used for LTR_IGNORE */ 68 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 69 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 70 {} 71 }; 72 73 const struct pmc_bit_map lnl_power_gating_status_0_map[] = { 74 {"PMC_PGD0_PG_STS", BIT(0)}, 75 {"FUSE_OSSE_PGD0_PG_STS", BIT(1)}, 76 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 77 {"XHCI_PGD0_PG_STS", BIT(3)}, 78 {"SPA_PGD0_PG_STS", BIT(4)}, 79 {"SPB_PGD0_PG_STS", BIT(5)}, 80 {"SPR16B0_PGD0_PG_STS", BIT(6)}, 81 {"GBE_PGD0_PG_STS", BIT(7)}, 82 {"SBR8B7_PGD0_PG_STS", BIT(8)}, 83 {"SBR8B6_PGD0_PG_STS", BIT(9)}, 84 {"SBR16B1_PGD0_PG_STS", BIT(10)}, 85 {"SBR8B8_PGD0_PG_STS", BIT(11)}, 86 {"ESE_PGD3_PG_STS", BIT(12)}, 87 {"D2D_DISP_PGD0_PG_STS", BIT(13)}, 88 {"LPSS_PGD0_PG_STS", BIT(14)}, 89 {"LPC_PGD0_PG_STS", BIT(15)}, 90 {"SMB_PGD0_PG_STS", BIT(16)}, 91 {"ISH_PGD0_PG_STS", BIT(17)}, 92 {"SBR8B2_PGD0_PG_STS", BIT(18)}, 93 {"NPK_PGD0_PG_STS", BIT(19)}, 94 {"D2D_NOC_PGD0_PG_STS", BIT(20)}, 95 {"SAFSS_PGD0_PG_STS", BIT(21)}, 96 {"FUSE_PGD0_PG_STS", BIT(22)}, 97 {"D2D_DISP_PGD1_PG_STS", BIT(23)}, 98 {"MPFPW1_PGD0_PG_STS", BIT(24)}, 99 {"XDCI_PGD0_PG_STS", BIT(25)}, 100 {"EXI_PGD0_PG_STS", BIT(26)}, 101 {"CSE_PGD0_PG_STS", BIT(27)}, 102 {"KVMCC_PGD0_PG_STS", BIT(28)}, 103 {"PMT_PGD0_PG_STS", BIT(29)}, 104 {"CLINK_PGD0_PG_STS", BIT(30)}, 105 {"PTIO_PGD0_PG_STS", BIT(31)}, 106 {} 107 }; 108 109 const struct pmc_bit_map lnl_power_gating_status_1_map[] = { 110 {"USBR0_PGD0_PG_STS", BIT(0)}, 111 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 112 {"SMT1_PGD0_PG_STS", BIT(2)}, 113 {"U3FPW1_PGD0_PG_STS", BIT(3)}, 114 {"SMS2_PGD0_PG_STS", BIT(4)}, 115 {"SMS1_PGD0_PG_STS", BIT(5)}, 116 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 117 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 118 {"FIA_PG_PGD0_PG_STS", BIT(8)}, 119 {"SBR16B4_PGD0_PG_STS", BIT(9)}, 120 {"P2SB8B_PGD0_PG_STS", BIT(10)}, 121 {"DBG_SBR_PGD0_PG_STS", BIT(11)}, 122 {"SBR8B9_PGD0_PG_STS", BIT(12)}, 123 {"OSSE_SMT1_PGD0_PG_STS", BIT(13)}, 124 {"SBR8B10_PGD0_PG_STS", BIT(14)}, 125 {"SBR16B3_PGD0_PG_STS", BIT(15)}, 126 {"G5FPW1_PGD0_PG_STS", BIT(16)}, 127 {"SBRG_PGD0_PG_STS", BIT(17)}, 128 {"PSF4_PGD0_PG_STS", BIT(18)}, 129 {"CNVI_PGD0_PG_STS", BIT(19)}, 130 {"USFX2_PGD0_PG_STS", BIT(20)}, 131 {"ENDBG_PGD0_PG_STS", BIT(21)}, 132 {"FIACPCB_P5X4_PGD0_PG_STS", BIT(22)}, 133 {"SBR8B3_PGD0_PG_STS", BIT(23)}, 134 {"SBR8B0_PGD0_PG_STS", BIT(24)}, 135 {"NPK_PGD1_PG_STS", BIT(25)}, 136 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(26)}, 137 {"D2D_NOC_PGD2_PG_STS", BIT(27)}, 138 {"SBR8B1_PGD0_PG_STS", BIT(28)}, 139 {"PSF6_PGD0_PG_STS", BIT(29)}, 140 {"PSF7_PGD0_PG_STS", BIT(30)}, 141 {"FIA_U_PGD0_PG_STS", BIT(31)}, 142 {} 143 }; 144 145 const struct pmc_bit_map lnl_power_gating_status_2_map[] = { 146 {"PSF8_PGD0_PG_STS", BIT(0)}, 147 {"SBR16B2_PGD0_PG_STS", BIT(1)}, 148 {"D2D_IPU_PGD0_PG_STS", BIT(2)}, 149 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 150 {"TAM_PGD0_PG_STS", BIT(4)}, 151 {"D2D_NOC_PGD1_PG_STS", BIT(5)}, 152 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 153 {"THC0_PGD0_PG_STS", BIT(7)}, 154 {"THC1_PGD0_PG_STS", BIT(8)}, 155 {"PMC_PGD0_PG_STS", BIT(9)}, 156 {"SBR8B5_PGD0_PG_STS", BIT(10)}, 157 {"UFSPW1_PGD0_PG_STS", BIT(11)}, 158 {"DBC_PGD0_PG_STS", BIT(12)}, 159 {"TCSS_PGD0_PG_STS", BIT(13)}, 160 {"FIA_P5X4_PGD0_PG_STS", BIT(14)}, 161 {"DISP_PGA_PGD0_PG_STS", BIT(15)}, 162 {"DISP_PSF_PGD0_PG_STS", BIT(16)}, 163 {"PSF0_PGD0_PG_STS", BIT(17)}, 164 {"P2SB16B_PGD0_PG_STS", BIT(18)}, 165 {"ACE_PGD0_PG_STS", BIT(19)}, 166 {"ACE_PGD1_PG_STS", BIT(20)}, 167 {"ACE_PGD2_PG_STS", BIT(21)}, 168 {"ACE_PGD3_PG_STS", BIT(22)}, 169 {"ACE_PGD4_PG_STS", BIT(23)}, 170 {"ACE_PGD5_PG_STS", BIT(24)}, 171 {"ACE_PGD6_PG_STS", BIT(25)}, 172 {"ACE_PGD7_PG_STS", BIT(26)}, 173 {"ACE_PGD8_PG_STS", BIT(27)}, 174 {"ACE_PGD9_PG_STS", BIT(28)}, 175 {"ACE_PGD10_PG_STS", BIT(29)}, 176 {"FIACPCB_PG_PGD0_PG_STS", BIT(30)}, 177 {"OSSE_PGD0_PG_STS", BIT(31)}, 178 {} 179 }; 180 181 const struct pmc_bit_map lnl_d3_status_0_map[] = { 182 {"LPSS_D3_STS", BIT(3)}, 183 {"XDCI_D3_STS", BIT(4)}, 184 {"XHCI_D3_STS", BIT(5)}, 185 {"SPA_D3_STS", BIT(12)}, 186 {"SPB_D3_STS", BIT(13)}, 187 {"OSSE_D3_STS", BIT(15)}, 188 {"ESPISPI_D3_STS", BIT(18)}, 189 {"PSTH_D3_STS", BIT(21)}, 190 {} 191 }; 192 193 const struct pmc_bit_map lnl_d3_status_1_map[] = { 194 {"OSSE_SMT1_D3_STS", BIT(7)}, 195 {"GBE_D3_STS", BIT(19)}, 196 {"ITSS_D3_STS", BIT(23)}, 197 {"CNVI_D3_STS", BIT(27)}, 198 {"UFSX2_D3_STS", BIT(28)}, 199 {"OSSE_HOTHAM_D3_STS", BIT(31)}, 200 {} 201 }; 202 203 const struct pmc_bit_map lnl_d3_status_2_map[] = { 204 {"ESE_D3_STS", BIT(0)}, 205 {"CSMERTC_D3_STS", BIT(1)}, 206 {"SUSRAM_D3_STS", BIT(2)}, 207 {"CSE_D3_STS", BIT(4)}, 208 {"KVMCC_D3_STS", BIT(5)}, 209 {"USBR0_D3_STS", BIT(6)}, 210 {"ISH_D3_STS", BIT(7)}, 211 {"SMT1_D3_STS", BIT(8)}, 212 {"SMT2_D3_STS", BIT(9)}, 213 {"SMT3_D3_STS", BIT(10)}, 214 {"OSSE_SMT2_D3_STS", BIT(13)}, 215 {"CLINK_D3_STS", BIT(14)}, 216 {"PTIO_D3_STS", BIT(16)}, 217 {"PMT_D3_STS", BIT(17)}, 218 {"SMS1_D3_STS", BIT(18)}, 219 {"SMS2_D3_STS", BIT(19)}, 220 {} 221 }; 222 223 const struct pmc_bit_map lnl_d3_status_3_map[] = { 224 {"THC0_D3_STS", BIT(14)}, 225 {"THC1_D3_STS", BIT(15)}, 226 {"OSSE_SMT3_D3_STS", BIT(21)}, 227 {"ACE_D3_STS", BIT(23)}, 228 {} 229 }; 230 231 const struct pmc_bit_map lnl_vnn_req_status_0_map[] = { 232 {"LPSS_VNN_REQ_STS", BIT(3)}, 233 {"OSSE_VNN_REQ_STS", BIT(15)}, 234 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 235 {} 236 }; 237 238 const struct pmc_bit_map lnl_vnn_req_status_1_map[] = { 239 {"NPK_VNN_REQ_STS", BIT(4)}, 240 {"OSSE_SMT1_VNN_REQ_STS", BIT(7)}, 241 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 242 {"EXI_VNN_REQ_STS", BIT(9)}, 243 {"P2D_VNN_REQ_STS", BIT(18)}, 244 {"GBE_VNN_REQ_STS", BIT(19)}, 245 {"SMB_VNN_REQ_STS", BIT(25)}, 246 {"LPC_VNN_REQ_STS", BIT(26)}, 247 {} 248 }; 249 250 const struct pmc_bit_map lnl_vnn_req_status_2_map[] = { 251 {"eSE_VNN_REQ_STS", BIT(0)}, 252 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 253 {"CSE_VNN_REQ_STS", BIT(4)}, 254 {"ISH_VNN_REQ_STS", BIT(7)}, 255 {"SMT1_VNN_REQ_STS", BIT(8)}, 256 {"CLINK_VNN_REQ_STS", BIT(14)}, 257 {"SMS1_VNN_REQ_STS", BIT(18)}, 258 {"SMS2_VNN_REQ_STS", BIT(19)}, 259 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 260 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 261 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 262 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 263 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 264 {} 265 }; 266 267 const struct pmc_bit_map lnl_vnn_req_status_3_map[] = { 268 {"DISP_SHIM_VNN_REQ_STS", BIT(2)}, 269 {"DTS0_VNN_REQ_STS", BIT(7)}, 270 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 271 {} 272 }; 273 274 const struct pmc_bit_map lnl_vnn_misc_status_map[] = { 275 {"CPU_C10_REQ_STS", BIT(0)}, 276 {"TS_OFF_REQ_STS", BIT(1)}, 277 {"PNDE_MET_REQ_STS", BIT(2)}, 278 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 279 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 280 {"NPK_VNNAON_REQ_STS", BIT(5)}, 281 {"VNN_SOC_REQ_STS", BIT(6)}, 282 {"ISH_VNNAON_REQ_STS", BIT(7)}, 283 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8)}, 284 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9)}, 285 {"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10)}, 286 {"PLT_GREATER_REQ_STS", BIT(11)}, 287 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 288 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 289 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 290 {"EA_REQ_STS", BIT(15)}, 291 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 292 {"BRK_EV_EN_REQ_STS", BIT(17)}, 293 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 294 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 295 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 296 {"ARC_IDLE_REQ_STS", BIT(21)}, 297 {"MPHY_SUS_REQ_STS", BIT(22)}, 298 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 299 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 300 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 301 {"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26)}, 302 {"PRE_WAKE0_REQ_STS", BIT(27)}, 303 {"PRE_WAKE1_REQ_STS", BIT(28)}, 304 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 305 {"WOV_REQ_STS", BIT(30)}, 306 {"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31)}, 307 {} 308 }; 309 310 const struct pmc_bit_map lnl_clocksource_status_map[] = { 311 {"AON2_OFF_STS", BIT(0)}, 312 {"AON3_OFF_STS", BIT(1)}, 313 {"AON4_OFF_STS", BIT(2)}, 314 {"AON5_OFF_STS", BIT(3)}, 315 {"AON1_OFF_STS", BIT(4)}, 316 {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, 317 {"USB3_PLL_OFF_STS", BIT(8)}, 318 {"AON3_SPL_OFF_STS", BIT(9)}, 319 {"G5FPW1_PLL_OFF_STS", BIT(15)}, 320 {"XTAL_AGGR_OFF_STS", BIT(17)}, 321 {"USB2_PLL_OFF_STS", BIT(18)}, 322 {"SAF_PLL_OFF_STS", BIT(19)}, 323 {"SE_TCSS_PLL_OFF_STS", BIT(20)}, 324 {"DDI_PLL_OFF_STS", BIT(21)}, 325 {"FILTER_PLL_OFF_STS", BIT(22)}, 326 {"ACE_PLL_OFF_STS", BIT(24)}, 327 {"FABRIC_PLL_OFF_STS", BIT(25)}, 328 {"SOC_PLL_OFF_STS", BIT(26)}, 329 {"REF_OFF_STS", BIT(28)}, 330 {"IMG_OFF_STS", BIT(29)}, 331 {"RTC_PLL_OFF_STS", BIT(31)}, 332 {} 333 }; 334 335 const struct pmc_bit_map *lnl_lpm_maps[] = { 336 lnl_clocksource_status_map, 337 lnl_power_gating_status_0_map, 338 lnl_power_gating_status_1_map, 339 lnl_power_gating_status_2_map, 340 lnl_d3_status_0_map, 341 lnl_d3_status_1_map, 342 lnl_d3_status_2_map, 343 lnl_d3_status_3_map, 344 lnl_vnn_req_status_0_map, 345 lnl_vnn_req_status_1_map, 346 lnl_vnn_req_status_2_map, 347 lnl_vnn_req_status_3_map, 348 lnl_vnn_misc_status_map, 349 mtl_socm_signal_status_map, 350 NULL 351 }; 352 353 const struct pmc_bit_map lnl_pfear_map[] = { 354 {"PMC_0", BIT(0)}, 355 {"FUSE_OSSE", BIT(1)}, 356 {"ESPISPI", BIT(2)}, 357 {"XHCI", BIT(3)}, 358 {"SPA", BIT(4)}, 359 {"SPB", BIT(5)}, 360 {"SBR16B0", BIT(6)}, 361 {"GBE", BIT(7)}, 362 363 {"SBR8B7", BIT(0)}, 364 {"SBR8B6", BIT(1)}, 365 {"SBR16B1", BIT(1)}, 366 {"SBR8B8", BIT(2)}, 367 {"ESE", BIT(3)}, 368 {"SBR8B10", BIT(4)}, 369 {"D2D_DISP_0", BIT(5)}, 370 {"LPSS", BIT(6)}, 371 {"LPC", BIT(7)}, 372 373 {"SMB", BIT(0)}, 374 {"ISH", BIT(1)}, 375 {"SBR8B2", BIT(2)}, 376 {"NPK_0", BIT(3)}, 377 {"D2D_NOC_0", BIT(4)}, 378 {"SAFSS", BIT(5)}, 379 {"FUSE", BIT(6)}, 380 {"D2D_DISP_1", BIT(7)}, 381 382 {"MPFPW1", BIT(0)}, 383 {"XDCI", BIT(1)}, 384 {"EXI", BIT(2)}, 385 {"CSE", BIT(3)}, 386 {"KVMCC", BIT(4)}, 387 {"PMT", BIT(5)}, 388 {"CLINK", BIT(6)}, 389 {"PTIO", BIT(7)}, 390 391 {"USBR", BIT(0)}, 392 {"SUSRAM", BIT(1)}, 393 {"SMT1", BIT(2)}, 394 {"U3FPW1", BIT(3)}, 395 {"SMS2", BIT(4)}, 396 {"SMS1", BIT(5)}, 397 {"CSMERTC", BIT(6)}, 398 {"CSMEPSF", BIT(7)}, 399 400 {"FIA_PG", BIT(0)}, 401 {"SBR16B4", BIT(1)}, 402 {"P2SB8B", BIT(2)}, 403 {"DBG_SBR", BIT(3)}, 404 {"SBR8B9", BIT(4)}, 405 {"OSSE_SMT1", BIT(5)}, 406 {"SBR8B10", BIT(6)}, 407 {"SBR16B3", BIT(7)}, 408 409 {"G5FPW1", BIT(0)}, 410 {"SBRG", BIT(1)}, 411 {"PSF4", BIT(2)}, 412 {"CNVI", BIT(3)}, 413 {"UFSX2", BIT(4)}, 414 {"ENDBG", BIT(5)}, 415 {"FIACPCB_P5X4", BIT(6)}, 416 {"SBR8B3", BIT(7)}, 417 418 {"SBR8B0", BIT(0)}, 419 {"NPK_1", BIT(1)}, 420 {"OSSE_HOTHAM", BIT(2)}, 421 {"D2D_NOC_2", BIT(3)}, 422 {"SBR8B1", BIT(4)}, 423 {"PSF6", BIT(5)}, 424 {"PSF7", BIT(6)}, 425 {"FIA_U", BIT(7)}, 426 427 {"PSF8", BIT(0)}, 428 {"SBR16B2", BIT(1)}, 429 {"D2D_IPU", BIT(2)}, 430 {"FIACPCB_U", BIT(3)}, 431 {"TAM", BIT(4)}, 432 {"D2D_NOC_1", BIT(5)}, 433 {"TBTLSX", BIT(6)}, 434 {"THC0", BIT(7)}, 435 436 {"THC1", BIT(0)}, 437 {"PMC_1", BIT(1)}, 438 {"SBR8B5", BIT(2)}, 439 {"UFSPW1", BIT(3)}, 440 {"DBC", BIT(4)}, 441 {"TCSS", BIT(5)}, 442 {"FIA_P5X4", BIT(6)}, 443 {"DISP_PGA", BIT(7)}, 444 445 {"DBG_PSF", BIT(0)}, 446 {"PSF0", BIT(1)}, 447 {"P2SB16B", BIT(2)}, 448 {"ACE0", BIT(3)}, 449 {"ACE1", BIT(4)}, 450 {"ACE2", BIT(5)}, 451 {"ACE3", BIT(6)}, 452 {"ACE4", BIT(7)}, 453 454 {"ACE5", BIT(0)}, 455 {"ACE6", BIT(1)}, 456 {"ACE7", BIT(2)}, 457 {"ACE8", BIT(3)}, 458 {"ACE9", BIT(4)}, 459 {"ACE10", BIT(5)}, 460 {"FIACPCB", BIT(6)}, 461 {"OSSE", BIT(7)}, 462 {} 463 }; 464 465 const struct pmc_bit_map *ext_lnl_pfear_map[] = { 466 lnl_pfear_map, 467 NULL 468 }; 469 470 const struct pmc_reg_map lnl_socm_reg_map = { 471 .pfear_sts = ext_lnl_pfear_map, 472 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 473 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 474 .ltr_show_sts = lnl_ltr_show_map, 475 .msr_sts = msr_map, 476 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 477 .regmap_length = LNL_PMC_MMIO_REG_LEN, 478 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 479 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 480 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 481 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 482 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 483 .lpm_num_maps = ADL_LPM_NUM_MAPS, 484 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 485 .etr3_offset = ETR3_OFFSET, 486 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 487 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 488 .lpm_en_offset = MTL_LPM_EN_OFFSET, 489 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 490 .lpm_sts = lnl_lpm_maps, 491 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 492 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 493 .lpm_reg_index = LNL_LPM_REG_INDEX, 494 }; 495 496 #define LNL_NPU_PCI_DEV 0x643e 497 #define LNL_IPU_PCI_DEV 0x645d 498 499 /* 500 * Set power state of select devices that do not have drivers to D3 501 * so that they do not block Package C entry. 502 */ 503 static void lnl_d3_fixup(void) 504 { 505 pmc_core_set_device_d3(LNL_IPU_PCI_DEV); 506 pmc_core_set_device_d3(LNL_NPU_PCI_DEV); 507 } 508 509 static int lnl_resume(struct pmc_dev *pmcdev) 510 { 511 lnl_d3_fixup(); 512 pmc_core_send_ltr_ignore(pmcdev, 3, 0); 513 514 return pmc_core_resume_common(pmcdev); 515 } 516 517 int lnl_core_init(struct pmc_dev *pmcdev) 518 { 519 int ret; 520 int func = 2; 521 bool ssram_init = true; 522 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; 523 524 lnl_d3_fixup(); 525 526 pmcdev->suspend = cnl_suspend; 527 pmcdev->resume = lnl_resume; 528 pmcdev->regmap_list = lnl_pmc_info_list; 529 ret = pmc_core_ssram_init(pmcdev, func); 530 531 /* If regbase not assigned, set map and discover using legacy method */ 532 if (ret) { 533 ssram_init = false; 534 pmc->map = &lnl_socm_reg_map; 535 ret = get_primary_reg_base(pmc); 536 if (ret) 537 return ret; 538 } 539 540 pmc_core_get_low_power_modes(pmcdev); 541 542 if (ssram_init) { 543 ret = pmc_core_ssram_get_lpm_reqs(pmcdev); 544 if (ret) 545 return ret; 546 } 547 548 return 0; 549 } 550