1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Meteor Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include <linux/cpu.h> 12 #include <linux/pci.h> 13 14 #include "core.h" 15 16 const struct pmc_bit_map lnl_ltr_show_map[] = { 17 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 18 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 19 {"SATA", CNP_PMC_LTR_SATA}, 20 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 21 {"XHCI", CNP_PMC_LTR_XHCI}, 22 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 23 {"ME", CNP_PMC_LTR_ME}, 24 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 25 {"SATA1", CNP_PMC_LTR_EVA}, 26 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 27 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 28 {"CNV", CNP_PMC_LTR_CNV}, 29 {"LPSS", CNP_PMC_LTR_LPSS}, 30 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 31 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 32 {"SATA2", CNP_PMC_LTR_CAM}, 33 {"ESPI", CNP_PMC_LTR_ESPI}, 34 {"SCC", CNP_PMC_LTR_SCC}, 35 {"ISH", CNP_PMC_LTR_ISH}, 36 {"UFSX2", CNP_PMC_LTR_UFSX2}, 37 {"EMMC", CNP_PMC_LTR_EMMC}, 38 /* 39 * Check intel_pmc_core_ids[] users of cnp_reg_map for 40 * a list of core SoCs using this. 41 */ 42 {"WIGIG", ICL_PMC_LTR_WIGIG}, 43 {"THC0", TGL_PMC_LTR_THC0}, 44 {"THC1", TGL_PMC_LTR_THC1}, 45 {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, 46 47 {"ESE", MTL_PMC_LTR_ESE}, 48 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 49 {"DMI3", ARL_PMC_LTR_DMI3}, 50 {"OSSE", LNL_PMC_LTR_OSSE}, 51 52 /* Below two cannot be used for LTR_IGNORE */ 53 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 54 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 55 {} 56 }; 57 58 const struct pmc_bit_map lnl_power_gating_status_0_map[] = { 59 {"PMC_PGD0_PG_STS", BIT(0)}, 60 {"FUSE_OSSE_PGD0_PG_STS", BIT(1)}, 61 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 62 {"XHCI_PGD0_PG_STS", BIT(3)}, 63 {"SPA_PGD0_PG_STS", BIT(4)}, 64 {"SPB_PGD0_PG_STS", BIT(5)}, 65 {"SPR16B0_PGD0_PG_STS", BIT(6)}, 66 {"GBE_PGD0_PG_STS", BIT(7)}, 67 {"SBR8B7_PGD0_PG_STS", BIT(8)}, 68 {"SBR8B6_PGD0_PG_STS", BIT(9)}, 69 {"SBR16B1_PGD0_PG_STS", BIT(10)}, 70 {"SBR8B8_PGD0_PG_STS", BIT(11)}, 71 {"ESE_PGD3_PG_STS", BIT(12)}, 72 {"D2D_DISP_PGD0_PG_STS", BIT(13)}, 73 {"LPSS_PGD0_PG_STS", BIT(14)}, 74 {"LPC_PGD0_PG_STS", BIT(15)}, 75 {"SMB_PGD0_PG_STS", BIT(16)}, 76 {"ISH_PGD0_PG_STS", BIT(17)}, 77 {"SBR8B2_PGD0_PG_STS", BIT(18)}, 78 {"NPK_PGD0_PG_STS", BIT(19)}, 79 {"D2D_NOC_PGD0_PG_STS", BIT(20)}, 80 {"SAFSS_PGD0_PG_STS", BIT(21)}, 81 {"FUSE_PGD0_PG_STS", BIT(22)}, 82 {"D2D_DISP_PGD1_PG_STS", BIT(23)}, 83 {"MPFPW1_PGD0_PG_STS", BIT(24)}, 84 {"XDCI_PGD0_PG_STS", BIT(25)}, 85 {"EXI_PGD0_PG_STS", BIT(26)}, 86 {"CSE_PGD0_PG_STS", BIT(27)}, 87 {"KVMCC_PGD0_PG_STS", BIT(28)}, 88 {"PMT_PGD0_PG_STS", BIT(29)}, 89 {"CLINK_PGD0_PG_STS", BIT(30)}, 90 {"PTIO_PGD0_PG_STS", BIT(31)}, 91 {} 92 }; 93 94 const struct pmc_bit_map lnl_power_gating_status_1_map[] = { 95 {"USBR0_PGD0_PG_STS", BIT(0)}, 96 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 97 {"SMT1_PGD0_PG_STS", BIT(2)}, 98 {"U3FPW1_PGD0_PG_STS", BIT(3)}, 99 {"SMS2_PGD0_PG_STS", BIT(4)}, 100 {"SMS1_PGD0_PG_STS", BIT(5)}, 101 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 102 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 103 {"FIA_PG_PGD0_PG_STS", BIT(8)}, 104 {"SBR16B4_PGD0_PG_STS", BIT(9)}, 105 {"P2SB8B_PGD0_PG_STS", BIT(10)}, 106 {"DBG_SBR_PGD0_PG_STS", BIT(11)}, 107 {"SBR8B9_PGD0_PG_STS", BIT(12)}, 108 {"OSSE_SMT1_PGD0_PG_STS", BIT(13)}, 109 {"SBR8B10_PGD0_PG_STS", BIT(14)}, 110 {"SBR16B3_PGD0_PG_STS", BIT(15)}, 111 {"G5FPW1_PGD0_PG_STS", BIT(16)}, 112 {"SBRG_PGD0_PG_STS", BIT(17)}, 113 {"PSF4_PGD0_PG_STS", BIT(18)}, 114 {"CNVI_PGD0_PG_STS", BIT(19)}, 115 {"USFX2_PGD0_PG_STS", BIT(20)}, 116 {"ENDBG_PGD0_PG_STS", BIT(21)}, 117 {"FIACPCB_P5X4_PGD0_PG_STS", BIT(22)}, 118 {"SBR8B3_PGD0_PG_STS", BIT(23)}, 119 {"SBR8B0_PGD0_PG_STS", BIT(24)}, 120 {"NPK_PGD1_PG_STS", BIT(25)}, 121 {"OSSE_HOTHAM_PGD0_PG_STS", BIT(26)}, 122 {"D2D_NOC_PGD2_PG_STS", BIT(27)}, 123 {"SBR8B1_PGD0_PG_STS", BIT(28)}, 124 {"PSF6_PGD0_PG_STS", BIT(29)}, 125 {"PSF7_PGD0_PG_STS", BIT(30)}, 126 {"FIA_U_PGD0_PG_STS", BIT(31)}, 127 {} 128 }; 129 130 const struct pmc_bit_map lnl_power_gating_status_2_map[] = { 131 {"PSF8_PGD0_PG_STS", BIT(0)}, 132 {"SBR16B2_PGD0_PG_STS", BIT(1)}, 133 {"D2D_IPU_PGD0_PG_STS", BIT(2)}, 134 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 135 {"TAM_PGD0_PG_STS", BIT(4)}, 136 {"D2D_NOC_PGD1_PG_STS", BIT(5)}, 137 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 138 {"THC0_PGD0_PG_STS", BIT(7)}, 139 {"THC1_PGD0_PG_STS", BIT(8)}, 140 {"PMC_PGD0_PG_STS", BIT(9)}, 141 {"SBR8B5_PGD0_PG_STS", BIT(10)}, 142 {"UFSPW1_PGD0_PG_STS", BIT(11)}, 143 {"DBC_PGD0_PG_STS", BIT(12)}, 144 {"TCSS_PGD0_PG_STS", BIT(13)}, 145 {"FIA_P5X4_PGD0_PG_STS", BIT(14)}, 146 {"DISP_PGA_PGD0_PG_STS", BIT(15)}, 147 {"DISP_PSF_PGD0_PG_STS", BIT(16)}, 148 {"PSF0_PGD0_PG_STS", BIT(17)}, 149 {"P2SB16B_PGD0_PG_STS", BIT(18)}, 150 {"ACE_PGD0_PG_STS", BIT(19)}, 151 {"ACE_PGD1_PG_STS", BIT(20)}, 152 {"ACE_PGD2_PG_STS", BIT(21)}, 153 {"ACE_PGD3_PG_STS", BIT(22)}, 154 {"ACE_PGD4_PG_STS", BIT(23)}, 155 {"ACE_PGD5_PG_STS", BIT(24)}, 156 {"ACE_PGD6_PG_STS", BIT(25)}, 157 {"ACE_PGD7_PG_STS", BIT(26)}, 158 {"ACE_PGD8_PG_STS", BIT(27)}, 159 {"ACE_PGD9_PG_STS", BIT(28)}, 160 {"ACE_PGD10_PG_STS", BIT(29)}, 161 {"FIACPCB_PG_PGD0_PG_STS", BIT(30)}, 162 {"OSSE_PGD0_PG_STS", BIT(31)}, 163 {} 164 }; 165 166 const struct pmc_bit_map lnl_d3_status_0_map[] = { 167 {"LPSS_D3_STS", BIT(3)}, 168 {"XDCI_D3_STS", BIT(4)}, 169 {"XHCI_D3_STS", BIT(5)}, 170 {"SPA_D3_STS", BIT(12)}, 171 {"SPB_D3_STS", BIT(13)}, 172 {"OSSE_D3_STS", BIT(15)}, 173 {"ESPISPI_D3_STS", BIT(18)}, 174 {"PSTH_D3_STS", BIT(21)}, 175 {} 176 }; 177 178 const struct pmc_bit_map lnl_d3_status_1_map[] = { 179 {"OSSE_SMT1_D3_STS", BIT(7)}, 180 {"GBE_D3_STS", BIT(19)}, 181 {"ITSS_D3_STS", BIT(23)}, 182 {"CNVI_D3_STS", BIT(27)}, 183 {"UFSX2_D3_STS", BIT(28)}, 184 {"OSSE_HOTHAM_D3_STS", BIT(31)}, 185 {} 186 }; 187 188 const struct pmc_bit_map lnl_d3_status_2_map[] = { 189 {"ESE_D3_STS", BIT(0)}, 190 {"CSMERTC_D3_STS", BIT(1)}, 191 {"SUSRAM_D3_STS", BIT(2)}, 192 {"CSE_D3_STS", BIT(4)}, 193 {"KVMCC_D3_STS", BIT(5)}, 194 {"USBR0_D3_STS", BIT(6)}, 195 {"ISH_D3_STS", BIT(7)}, 196 {"SMT1_D3_STS", BIT(8)}, 197 {"SMT2_D3_STS", BIT(9)}, 198 {"SMT3_D3_STS", BIT(10)}, 199 {"OSSE_SMT2_D3_STS", BIT(13)}, 200 {"CLINK_D3_STS", BIT(14)}, 201 {"PTIO_D3_STS", BIT(16)}, 202 {"PMT_D3_STS", BIT(17)}, 203 {"SMS1_D3_STS", BIT(18)}, 204 {"SMS2_D3_STS", BIT(19)}, 205 {} 206 }; 207 208 const struct pmc_bit_map lnl_d3_status_3_map[] = { 209 {"THC0_D3_STS", BIT(14)}, 210 {"THC1_D3_STS", BIT(15)}, 211 {"OSSE_SMT3_D3_STS", BIT(21)}, 212 {"ACE_D3_STS", BIT(23)}, 213 {} 214 }; 215 216 const struct pmc_bit_map lnl_vnn_req_status_0_map[] = { 217 {"LPSS_VNN_REQ_STS", BIT(3)}, 218 {"OSSE_VNN_REQ_STS", BIT(15)}, 219 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 220 {} 221 }; 222 223 const struct pmc_bit_map lnl_vnn_req_status_1_map[] = { 224 {"NPK_VNN_REQ_STS", BIT(4)}, 225 {"OSSE_SMT1_VNN_REQ_STS", BIT(7)}, 226 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 227 {"EXI_VNN_REQ_STS", BIT(9)}, 228 {"P2D_VNN_REQ_STS", BIT(18)}, 229 {"GBE_VNN_REQ_STS", BIT(19)}, 230 {"SMB_VNN_REQ_STS", BIT(25)}, 231 {"LPC_VNN_REQ_STS", BIT(26)}, 232 {} 233 }; 234 235 const struct pmc_bit_map lnl_vnn_req_status_2_map[] = { 236 {"eSE_VNN_REQ_STS", BIT(0)}, 237 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 238 {"CSE_VNN_REQ_STS", BIT(4)}, 239 {"ISH_VNN_REQ_STS", BIT(7)}, 240 {"SMT1_VNN_REQ_STS", BIT(8)}, 241 {"CLINK_VNN_REQ_STS", BIT(14)}, 242 {"SMS1_VNN_REQ_STS", BIT(18)}, 243 {"SMS2_VNN_REQ_STS", BIT(19)}, 244 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 245 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 246 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 247 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 248 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 249 {} 250 }; 251 252 const struct pmc_bit_map lnl_vnn_req_status_3_map[] = { 253 {"DISP_SHIM_VNN_REQ_STS", BIT(2)}, 254 {"DTS0_VNN_REQ_STS", BIT(7)}, 255 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 256 {} 257 }; 258 259 const struct pmc_bit_map lnl_vnn_misc_status_map[] = { 260 {"CPU_C10_REQ_STS", BIT(0)}, 261 {"TS_OFF_REQ_STS", BIT(1)}, 262 {"PNDE_MET_REQ_STS", BIT(2)}, 263 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 264 {"PMC_CLK_THROTTLE_EN_REQ_STS", BIT(4)}, 265 {"NPK_VNNAON_REQ_STS", BIT(5)}, 266 {"VNN_SOC_REQ_STS", BIT(6)}, 267 {"ISH_VNNAON_REQ_STS", BIT(7)}, 268 {"D2D_NOC_CFI_QACTIVE_REQ_STS", BIT(8)}, 269 {"D2D_NOC_GPSB_QACTIVE_REQ_STS", BIT(9)}, 270 {"D2D_NOC_IPU_QACTIVE_REQ_STS", BIT(10)}, 271 {"PLT_GREATER_REQ_STS", BIT(11)}, 272 {"PCIE_CLKREQ_REQ_STS", BIT(12)}, 273 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 274 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 275 {"EA_REQ_STS", BIT(15)}, 276 {"MPHY_CORE_OFF_REQ_STS", BIT(16)}, 277 {"BRK_EV_EN_REQ_STS", BIT(17)}, 278 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 279 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 280 {"LPC_CLK_SRC_REQ_STS", BIT(20)}, 281 {"ARC_IDLE_REQ_STS", BIT(21)}, 282 {"MPHY_SUS_REQ_STS", BIT(22)}, 283 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 284 {"UXD_CONNECTED_REQ_STS", BIT(24)}, 285 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 286 {"D2D_NOC_DISP_DDI_QACTIVE_REQ_STS", BIT(26)}, 287 {"PRE_WAKE0_REQ_STS", BIT(27)}, 288 {"PRE_WAKE1_REQ_STS", BIT(28)}, 289 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 290 {"WOV_REQ_STS", BIT(30)}, 291 {"D2D_NOC_DISP_EDP_QACTIVE_REQ_STS_31", BIT(31)}, 292 {} 293 }; 294 295 const struct pmc_bit_map lnl_clocksource_status_map[] = { 296 {"AON2_OFF_STS", BIT(0)}, 297 {"AON3_OFF_STS", BIT(1)}, 298 {"AON4_OFF_STS", BIT(2)}, 299 {"AON5_OFF_STS", BIT(3)}, 300 {"AON1_OFF_STS", BIT(4)}, 301 {"MPFPW1_0_PLL_OFF_STS", BIT(6)}, 302 {"USB3_PLL_OFF_STS", BIT(8)}, 303 {"AON3_SPL_OFF_STS", BIT(9)}, 304 {"G5FPW1_PLL_OFF_STS", BIT(15)}, 305 {"XTAL_AGGR_OFF_STS", BIT(17)}, 306 {"USB2_PLL_OFF_STS", BIT(18)}, 307 {"SAF_PLL_OFF_STS", BIT(19)}, 308 {"SE_TCSS_PLL_OFF_STS", BIT(20)}, 309 {"DDI_PLL_OFF_STS", BIT(21)}, 310 {"FILTER_PLL_OFF_STS", BIT(22)}, 311 {"ACE_PLL_OFF_STS", BIT(24)}, 312 {"FABRIC_PLL_OFF_STS", BIT(25)}, 313 {"SOC_PLL_OFF_STS", BIT(26)}, 314 {"REF_OFF_STS", BIT(28)}, 315 {"IMG_OFF_STS", BIT(29)}, 316 {"RTC_PLL_OFF_STS", BIT(31)}, 317 {} 318 }; 319 320 const struct pmc_bit_map *lnl_lpm_maps[] = { 321 lnl_clocksource_status_map, 322 lnl_power_gating_status_0_map, 323 lnl_power_gating_status_1_map, 324 lnl_power_gating_status_2_map, 325 lnl_d3_status_0_map, 326 lnl_d3_status_1_map, 327 lnl_d3_status_2_map, 328 lnl_d3_status_3_map, 329 lnl_vnn_req_status_0_map, 330 lnl_vnn_req_status_1_map, 331 lnl_vnn_req_status_2_map, 332 lnl_vnn_req_status_3_map, 333 lnl_vnn_misc_status_map, 334 mtl_socm_signal_status_map, 335 NULL 336 }; 337 338 const struct pmc_bit_map lnl_pfear_map[] = { 339 {"PMC_0", BIT(0)}, 340 {"FUSE_OSSE", BIT(1)}, 341 {"ESPISPI", BIT(2)}, 342 {"XHCI", BIT(3)}, 343 {"SPA", BIT(4)}, 344 {"SPB", BIT(5)}, 345 {"SBR16B0", BIT(6)}, 346 {"GBE", BIT(7)}, 347 348 {"SBR8B7", BIT(0)}, 349 {"SBR8B6", BIT(1)}, 350 {"SBR16B1", BIT(1)}, 351 {"SBR8B8", BIT(2)}, 352 {"ESE", BIT(3)}, 353 {"SBR8B10", BIT(4)}, 354 {"D2D_DISP_0", BIT(5)}, 355 {"LPSS", BIT(6)}, 356 {"LPC", BIT(7)}, 357 358 {"SMB", BIT(0)}, 359 {"ISH", BIT(1)}, 360 {"SBR8B2", BIT(2)}, 361 {"NPK_0", BIT(3)}, 362 {"D2D_NOC_0", BIT(4)}, 363 {"SAFSS", BIT(5)}, 364 {"FUSE", BIT(6)}, 365 {"D2D_DISP_1", BIT(7)}, 366 367 {"MPFPW1", BIT(0)}, 368 {"XDCI", BIT(1)}, 369 {"EXI", BIT(2)}, 370 {"CSE", BIT(3)}, 371 {"KVMCC", BIT(4)}, 372 {"PMT", BIT(5)}, 373 {"CLINK", BIT(6)}, 374 {"PTIO", BIT(7)}, 375 376 {"USBR", BIT(0)}, 377 {"SUSRAM", BIT(1)}, 378 {"SMT1", BIT(2)}, 379 {"U3FPW1", BIT(3)}, 380 {"SMS2", BIT(4)}, 381 {"SMS1", BIT(5)}, 382 {"CSMERTC", BIT(6)}, 383 {"CSMEPSF", BIT(7)}, 384 385 {"FIA_PG", BIT(0)}, 386 {"SBR16B4", BIT(1)}, 387 {"P2SB8B", BIT(2)}, 388 {"DBG_SBR", BIT(3)}, 389 {"SBR8B9", BIT(4)}, 390 {"OSSE_SMT1", BIT(5)}, 391 {"SBR8B10", BIT(6)}, 392 {"SBR16B3", BIT(7)}, 393 394 {"G5FPW1", BIT(0)}, 395 {"SBRG", BIT(1)}, 396 {"PSF4", BIT(2)}, 397 {"CNVI", BIT(3)}, 398 {"UFSX2", BIT(4)}, 399 {"ENDBG", BIT(5)}, 400 {"FIACPCB_P5X4", BIT(6)}, 401 {"SBR8B3", BIT(7)}, 402 403 {"SBR8B0", BIT(0)}, 404 {"NPK_1", BIT(1)}, 405 {"OSSE_HOTHAM", BIT(2)}, 406 {"D2D_NOC_2", BIT(3)}, 407 {"SBR8B1", BIT(4)}, 408 {"PSF6", BIT(5)}, 409 {"PSF7", BIT(6)}, 410 {"FIA_U", BIT(7)}, 411 412 {"PSF8", BIT(0)}, 413 {"SBR16B2", BIT(1)}, 414 {"D2D_IPU", BIT(2)}, 415 {"FIACPCB_U", BIT(3)}, 416 {"TAM", BIT(4)}, 417 {"D2D_NOC_1", BIT(5)}, 418 {"TBTLSX", BIT(6)}, 419 {"THC0", BIT(7)}, 420 421 {"THC1", BIT(0)}, 422 {"PMC_1", BIT(1)}, 423 {"SBR8B5", BIT(2)}, 424 {"UFSPW1", BIT(3)}, 425 {"DBC", BIT(4)}, 426 {"TCSS", BIT(5)}, 427 {"FIA_P5X4", BIT(6)}, 428 {"DISP_PGA", BIT(7)}, 429 430 {"DBG_PSF", BIT(0)}, 431 {"PSF0", BIT(1)}, 432 {"P2SB16B", BIT(2)}, 433 {"ACE0", BIT(3)}, 434 {"ACE1", BIT(4)}, 435 {"ACE2", BIT(5)}, 436 {"ACE3", BIT(6)}, 437 {"ACE4", BIT(7)}, 438 439 {"ACE5", BIT(0)}, 440 {"ACE6", BIT(1)}, 441 {"ACE7", BIT(2)}, 442 {"ACE8", BIT(3)}, 443 {"ACE9", BIT(4)}, 444 {"ACE10", BIT(5)}, 445 {"FIACPCB", BIT(6)}, 446 {"OSSE", BIT(7)}, 447 {} 448 }; 449 450 const struct pmc_bit_map *ext_lnl_pfear_map[] = { 451 lnl_pfear_map, 452 NULL 453 }; 454 455 const struct pmc_reg_map lnl_socm_reg_map = { 456 .pfear_sts = ext_lnl_pfear_map, 457 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 458 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 459 .ltr_show_sts = lnl_ltr_show_map, 460 .msr_sts = msr_map, 461 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 462 .regmap_length = LNL_PMC_MMIO_REG_LEN, 463 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 464 .ppfear_buckets = LNL_PPFEAR_NUM_ENTRIES, 465 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 466 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 467 .ltr_ignore_max = LNL_NUM_IP_IGN_ALLOWED, 468 .lpm_num_maps = ADL_LPM_NUM_MAPS, 469 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 470 .etr3_offset = ETR3_OFFSET, 471 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 472 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 473 .lpm_en_offset = MTL_LPM_EN_OFFSET, 474 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 475 .lpm_sts = lnl_lpm_maps, 476 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 477 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 478 }; 479 480 #define LNL_NPU_PCI_DEV 0x643e 481 #define LNL_IPU_PCI_DEV 0x645d 482 483 /* 484 * Set power state of select devices that do not have drivers to D3 485 * so that they do not block Package C entry. 486 */ 487 static void lnl_d3_fixup(void) 488 { 489 pmc_core_set_device_d3(LNL_IPU_PCI_DEV); 490 pmc_core_set_device_d3(LNL_NPU_PCI_DEV); 491 } 492 493 static int lnl_resume(struct pmc_dev *pmcdev) 494 { 495 lnl_d3_fixup(); 496 pmc_core_send_ltr_ignore(pmcdev, 3, 0); 497 498 return pmc_core_resume_common(pmcdev); 499 } 500 501 int lnl_core_init(struct pmc_dev *pmcdev) 502 { 503 int ret; 504 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_SOC]; 505 506 lnl_d3_fixup(); 507 508 pmcdev->suspend = cnl_suspend; 509 pmcdev->resume = lnl_resume; 510 511 pmc->map = &lnl_socm_reg_map; 512 ret = get_primary_reg_base(pmc); 513 if (ret) 514 return ret; 515 516 pmc_core_get_low_power_modes(pmcdev); 517 518 return 0; 519 } 520