1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Arrow Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include <linux/pci.h> 12 #include "core.h" 13 14 /* PMC SSRAM PMT Telemetry GUID */ 15 #define IOEP_LPM_REQ_GUID 0x5077612 16 #define SOCS_LPM_REQ_GUID 0x8478657 17 #define PCHS_LPM_REQ_GUID 0x9684572 18 #define SOCM_LPM_REQ_GUID 0x2625030 19 20 static const u8 ARL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 20}; 21 22 static const struct pmc_bit_map arl_socs_ltr_show_map[] = { 23 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 24 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 25 {"SATA", CNP_PMC_LTR_SATA}, 26 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 27 {"XHCI", CNP_PMC_LTR_XHCI}, 28 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 29 {"ME", CNP_PMC_LTR_ME}, 30 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 31 {"SATA1", CNP_PMC_LTR_EVA}, 32 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 33 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 34 {"CNV", CNP_PMC_LTR_CNV}, 35 {"LPSS", CNP_PMC_LTR_LPSS}, 36 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 37 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 38 {"SATA2", CNP_PMC_LTR_CAM}, 39 {"ESPI", CNP_PMC_LTR_ESPI}, 40 {"SCC", CNP_PMC_LTR_SCC}, 41 {"ISH", CNP_PMC_LTR_ISH}, 42 {"UFSX2", CNP_PMC_LTR_UFSX2}, 43 {"EMMC", CNP_PMC_LTR_EMMC}, 44 /* 45 * Check intel_pmc_core_ids[] users of cnp_reg_map for 46 * a list of core SoCs using this. 47 */ 48 {"WIGIG", ICL_PMC_LTR_WIGIG}, 49 {"THC0", TGL_PMC_LTR_THC0}, 50 {"THC1", TGL_PMC_LTR_THC1}, 51 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 52 {"Reserved", ARL_SOCS_PMC_LTR_RESERVED}, 53 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 54 {"DMI3", ARL_PMC_LTR_DMI3}, 55 56 /* Below two cannot be used for LTR_IGNORE */ 57 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 58 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 59 {} 60 }; 61 62 static const struct pmc_bit_map arl_socs_clocksource_status_map[] = { 63 {"AON2_OFF_STS", BIT(0)}, 64 {"AON3_OFF_STS", BIT(1)}, 65 {"AON4_OFF_STS", BIT(2)}, 66 {"AON5_OFF_STS", BIT(3)}, 67 {"AON1_OFF_STS", BIT(4)}, 68 {"XTAL_LVM_OFF_STS", BIT(5)}, 69 {"AON3_SPL_OFF_STS", BIT(9)}, 70 {"DMI3FPW_0_PLL_OFF_STS", BIT(10)}, 71 {"DMI3FPW_1_PLL_OFF_STS", BIT(11)}, 72 {"G5X16FPW_0_PLL_OFF_STS", BIT(14)}, 73 {"G5X16FPW_1_PLL_OFF_STS", BIT(15)}, 74 {"G5X16FPW_2_PLL_OFF_STS", BIT(16)}, 75 {"XTAL_AGGR_OFF_STS", BIT(17)}, 76 {"USB2_PLL_OFF_STS", BIT(18)}, 77 {"G5X16FPW_3_PLL_OFF_STS", BIT(19)}, 78 {"BCLK_EXT_INJ_CLK_OFF_STS", BIT(20)}, 79 {"PHY_OC_EXT_INJ_CLK_OFF_STS", BIT(21)}, 80 {"FILTER_PLL_OFF_STS", BIT(22)}, 81 {"FABRIC_PLL_OFF_STS", BIT(25)}, 82 {"SOC_PLL_OFF_STS", BIT(26)}, 83 {"PCIEFAB_PLL_OFF_STS", BIT(27)}, 84 {"REF_PLL_OFF_STS", BIT(28)}, 85 {"GENLOCK_FILTER_PLL_OFF_STS", BIT(30)}, 86 {"RTC_PLL_OFF_STS", BIT(31)}, 87 {} 88 }; 89 90 static const struct pmc_bit_map arl_socs_power_gating_status_0_map[] = { 91 {"PMC_PGD0_PG_STS", BIT(0)}, 92 {"DMI_PGD0_PG_STS", BIT(1)}, 93 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 94 {"XHCI_PGD0_PG_STS", BIT(3)}, 95 {"SPA_PGD0_PG_STS", BIT(4)}, 96 {"SPB_PGD0_PG_STS", BIT(5)}, 97 {"SPC_PGD0_PG_STS", BIT(6)}, 98 {"GBE_PGD0_PG_STS", BIT(7)}, 99 {"SATA_PGD0_PG_STS", BIT(8)}, 100 {"FIACPCB_P5x16_PGD0_PG_STS", BIT(9)}, 101 {"G5x16FPW_PGD0_PG_STS", BIT(10)}, 102 {"FIA_D_PGD0_PG_STS", BIT(11)}, 103 {"MPFPW2_PGD0_PG_STS", BIT(12)}, 104 {"SPD_PGD0_PG_STS", BIT(13)}, 105 {"LPSS_PGD0_PG_STS", BIT(14)}, 106 {"LPC_PGD0_PG_STS", BIT(15)}, 107 {"SMB_PGD0_PG_STS", BIT(16)}, 108 {"ISH_PGD0_PG_STS", BIT(17)}, 109 {"P2S_PGD0_PG_STS", BIT(18)}, 110 {"NPK_PGD0_PG_STS", BIT(19)}, 111 {"DMI3FPW_PGD0_PG_STS", BIT(20)}, 112 {"GBETSN1_PGD0_PG_STS", BIT(21)}, 113 {"FUSE_PGD0_PG_STS", BIT(22)}, 114 {"FIACPCB_D_PGD0_PG_STS", BIT(23)}, 115 {"FUSEGPSB_PGD0_PG_STS", BIT(24)}, 116 {"XDCI_PGD0_PG_STS", BIT(25)}, 117 {"EXI_PGD0_PG_STS", BIT(26)}, 118 {"CSE_PGD0_PG_STS", BIT(27)}, 119 {"KVMCC_PGD0_PG_STS", BIT(28)}, 120 {"PMT_PGD0_PG_STS", BIT(29)}, 121 {"CLINK_PGD0_PG_STS", BIT(30)}, 122 {"PTIO_PGD0_PG_STS", BIT(31)}, 123 {} 124 }; 125 126 static const struct pmc_bit_map arl_socs_power_gating_status_1_map[] = { 127 {"USBR0_PGD0_PG_STS", BIT(0)}, 128 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 129 {"SMT1_PGD0_PG_STS", BIT(2)}, 130 {"FIACPCB_U_PGD0_PG_STS", BIT(3)}, 131 {"SMS2_PGD0_PG_STS", BIT(4)}, 132 {"SMS1_PGD0_PG_STS", BIT(5)}, 133 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 134 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 135 {"SBR0_PGD0_PG_STS", BIT(8)}, 136 {"SBR1_PGD0_PG_STS", BIT(9)}, 137 {"SBR2_PGD0_PG_STS", BIT(10)}, 138 {"SBR3_PGD0_PG_STS", BIT(11)}, 139 {"MPFPW1_PGD0_PG_STS", BIT(12)}, 140 {"SBR5_PGD0_PG_STS", BIT(13)}, 141 {"FIA_X_PGD0_PG_STS", BIT(14)}, 142 {"FIACPCB_X_PGD0_PG_STS", BIT(15)}, 143 {"SBRG_PGD0_PG_STS", BIT(16)}, 144 {"SOC_D2D_PGD1_PG_STS", BIT(17)}, 145 {"PSF4_PGD0_PG_STS", BIT(18)}, 146 {"CNVI_PGD0_PG_STS", BIT(19)}, 147 {"UFSX2_PGD0_PG_STS", BIT(20)}, 148 {"ENDBG_PGD0_PG_STS", BIT(21)}, 149 {"DBG_PSF_PGD0_PG_STS", BIT(22)}, 150 {"SBR6_PGD0_PG_STS", BIT(23)}, 151 {"SOC_D2D_PGD2_PG_STS", BIT(24)}, 152 {"NPK_PGD1_PG_STS", BIT(25)}, 153 {"DMI3_PGD0_PG_STS", BIT(26)}, 154 {"DBG_SBR_PGD0_PG_STS", BIT(27)}, 155 {"SOC_D2D_PGD0_PG_STS", BIT(28)}, 156 {"PSF6_PGD0_PG_STS", BIT(29)}, 157 {"PSF7_PGD0_PG_STS", BIT(30)}, 158 {"MPFPW3_PGD0_PG_STS", BIT(31)}, 159 {} 160 }; 161 162 static const struct pmc_bit_map arl_socs_power_gating_status_2_map[] = { 163 {"PSF8_PGD0_PG_STS", BIT(0)}, 164 {"FIA_PGD0_PG_STS", BIT(1)}, 165 {"SOC_D2D_PGD3_PG_STS", BIT(2)}, 166 {"FIA_U_PGD0_PG_STS", BIT(3)}, 167 {"TAM_PGD0_PG_STS", BIT(4)}, 168 {"GBETSN_PGD0_PG_STS", BIT(5)}, 169 {"TBTLSX_PGD0_PG_STS", BIT(6)}, 170 {"THC0_PGD0_PG_STS", BIT(7)}, 171 {"THC1_PGD0_PG_STS", BIT(8)}, 172 {"PMC_PGD1_PG_STS", BIT(9)}, 173 {"FIA_P5x16_PGD0_PG_STS", BIT(10)}, 174 {"GNA_PGD0_PG_STS", BIT(11)}, 175 {"ACE_PGD0_PG_STS", BIT(12)}, 176 {"ACE_PGD1_PG_STS", BIT(13)}, 177 {"ACE_PGD2_PG_STS", BIT(14)}, 178 {"ACE_PGD3_PG_STS", BIT(15)}, 179 {"ACE_PGD4_PG_STS", BIT(16)}, 180 {"ACE_PGD5_PG_STS", BIT(17)}, 181 {"ACE_PGD6_PG_STS", BIT(18)}, 182 {"ACE_PGD7_PG_STS", BIT(19)}, 183 {"ACE_PGD8_PG_STS", BIT(20)}, 184 {"FIA_PGS_PGD0_PG_STS", BIT(21)}, 185 {"FIACPCB_PGS_PGD0_PG_STS", BIT(22)}, 186 {"FUSEPMSB_PGD0_PG_STS", BIT(23)}, 187 {} 188 }; 189 190 static const struct pmc_bit_map arl_socs_d3_status_2_map[] = { 191 {"CSMERTC_D3_STS", BIT(1)}, 192 {"SUSRAM_D3_STS", BIT(2)}, 193 {"CSE_D3_STS", BIT(4)}, 194 {"KVMCC_D3_STS", BIT(5)}, 195 {"USBR0_D3_STS", BIT(6)}, 196 {"ISH_D3_STS", BIT(7)}, 197 {"SMT1_D3_STS", BIT(8)}, 198 {"SMT2_D3_STS", BIT(9)}, 199 {"SMT3_D3_STS", BIT(10)}, 200 {"GNA_D3_STS", BIT(12)}, 201 {"CLINK_D3_STS", BIT(14)}, 202 {"PTIO_D3_STS", BIT(16)}, 203 {"PMT_D3_STS", BIT(17)}, 204 {"SMS1_D3_STS", BIT(18)}, 205 {"SMS2_D3_STS", BIT(19)}, 206 {} 207 }; 208 209 static const struct pmc_bit_map arl_socs_d3_status_3_map[] = { 210 {"GBETSN_D3_STS", BIT(13)}, 211 {"THC0_D3_STS", BIT(14)}, 212 {"THC1_D3_STS", BIT(15)}, 213 {"ACE_D3_STS", BIT(23)}, 214 {} 215 }; 216 217 static const struct pmc_bit_map arl_socs_vnn_req_status_3_map[] = { 218 {"DTS0_VNN_REQ_STS", BIT(7)}, 219 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 220 {} 221 }; 222 223 static const struct pmc_bit_map *arl_socs_lpm_maps[] = { 224 arl_socs_clocksource_status_map, 225 arl_socs_power_gating_status_0_map, 226 arl_socs_power_gating_status_1_map, 227 arl_socs_power_gating_status_2_map, 228 mtl_socm_d3_status_0_map, 229 mtl_socm_d3_status_1_map, 230 arl_socs_d3_status_2_map, 231 arl_socs_d3_status_3_map, 232 mtl_socm_vnn_req_status_0_map, 233 mtl_socm_vnn_req_status_1_map, 234 mtl_socm_vnn_req_status_2_map, 235 arl_socs_vnn_req_status_3_map, 236 mtl_socm_vnn_misc_status_map, 237 mtl_socm_signal_status_map, 238 NULL 239 }; 240 241 static const struct pmc_bit_map arl_socs_pfear_map[] = { 242 {"RSVD64", BIT(0)}, 243 {"RSVD65", BIT(1)}, 244 {"RSVD66", BIT(2)}, 245 {"RSVD67", BIT(3)}, 246 {"RSVD68", BIT(4)}, 247 {"GBETSN", BIT(5)}, 248 {"TBTLSX", BIT(6)}, 249 {} 250 }; 251 252 static const struct pmc_bit_map *ext_arl_socs_pfear_map[] = { 253 mtl_socm_pfear_map, 254 arl_socs_pfear_map, 255 NULL 256 }; 257 258 static const struct pmc_reg_map arl_socs_reg_map = { 259 .pfear_sts = ext_arl_socs_pfear_map, 260 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES, 261 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 262 .lpm_sts = arl_socs_lpm_maps, 263 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED, 264 .ltr_show_sts = arl_socs_ltr_show_map, 265 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 266 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 267 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 268 .msr_sts = msr_map, 269 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 270 .regmap_length = MTL_SOC_PMC_MMIO_REG_LEN, 271 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 272 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 273 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 274 .lpm_en_offset = MTL_LPM_EN_OFFSET, 275 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 276 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 277 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 278 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 279 .lpm_num_maps = ADL_LPM_NUM_MAPS, 280 .lpm_reg_index = ARL_LPM_REG_INDEX, 281 .etr3_offset = ETR3_OFFSET, 282 .pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET, 283 .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP, 284 .lpm_req_guid = SOCS_LPM_REQ_GUID, 285 }; 286 287 static const struct pmc_bit_map arl_pchs_ltr_show_map[] = { 288 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 289 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 290 {"SATA", CNP_PMC_LTR_SATA}, 291 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 292 {"XHCI", CNP_PMC_LTR_XHCI}, 293 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 294 {"ME", CNP_PMC_LTR_ME}, 295 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 296 {"SATA1", CNP_PMC_LTR_EVA}, 297 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 298 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 299 {"CNV", CNP_PMC_LTR_CNV}, 300 {"LPSS", CNP_PMC_LTR_LPSS}, 301 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 302 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 303 {"SATA2", CNP_PMC_LTR_CAM}, 304 {"ESPI", CNP_PMC_LTR_ESPI}, 305 {"SCC", CNP_PMC_LTR_SCC}, 306 {"ISH", CNP_PMC_LTR_ISH}, 307 {"UFSX2", CNP_PMC_LTR_UFSX2}, 308 {"EMMC", CNP_PMC_LTR_EMMC}, 309 /* 310 * Check intel_pmc_core_ids[] users of cnp_reg_map for 311 * a list of core SoCs using this. 312 */ 313 {"WIGIG", ICL_PMC_LTR_WIGIG}, 314 {"THC0", TGL_PMC_LTR_THC0}, 315 {"THC1", TGL_PMC_LTR_THC1}, 316 {"SOUTHPORT_G", MTL_PMC_LTR_SPG}, 317 {"ESE", MTL_PMC_LTR_ESE}, 318 {"IOE_PMC", MTL_PMC_LTR_IOE_PMC}, 319 {"DMI3", ARL_PMC_LTR_DMI3}, 320 321 /* Below two cannot be used for LTR_IGNORE */ 322 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 323 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 324 {} 325 }; 326 327 static const struct pmc_bit_map arl_pchs_clocksource_status_map[] = { 328 {"AON2_OFF_STS", BIT(0)}, 329 {"AON3_OFF_STS", BIT(1)}, 330 {"AON4_OFF_STS", BIT(2)}, 331 {"AON2_SPL_OFF_STS", BIT(3)}, 332 {"AONL_OFF_STS", BIT(4)}, 333 {"XTAL_LVM_OFF_STS", BIT(5)}, 334 {"AON5_ACRO_OFF_STS", BIT(6)}, 335 {"AON6_ACRO_OFF_STS", BIT(7)}, 336 {"USB3_PLL_OFF_STS", BIT(8)}, 337 {"ACRO_OFF_STS", BIT(9)}, 338 {"AUDIO_PLL_OFF_STS", BIT(10)}, 339 {"MAIN_CRO_OFF_STS", BIT(11)}, 340 {"MAIN_DIVIDER_OFF_STS", BIT(12)}, 341 {"REF_PLL_NON_OC_OFF_STS", BIT(13)}, 342 {"DMI_PLL_OFF_STS", BIT(14)}, 343 {"PHY_EXT_INJ_OFF_STS", BIT(15)}, 344 {"AON6_MCRO_OFF_STS", BIT(16)}, 345 {"XTAL_AGGR_OFF_STS", BIT(17)}, 346 {"USB2_PLL_OFF_STS", BIT(18)}, 347 {"TSN0_PLL_OFF_STS", BIT(19)}, 348 {"TSN1_PLL_OFF_STS", BIT(20)}, 349 {"GBE_PLL_OFF_STS", BIT(21)}, 350 {"SATA_PLL_OFF_STS", BIT(22)}, 351 {"PCIE0_PLL_OFF_STS", BIT(23)}, 352 {"PCIE1_PLL_OFF_STS", BIT(24)}, 353 {"PCIE2_PLL_OFF_STS", BIT(26)}, 354 {"PCIE3_PLL_OFF_STS", BIT(27)}, 355 {"REF_PLL_OFF_STS", BIT(28)}, 356 {"PCIE4_PLL_OFF_STS", BIT(29)}, 357 {"PCIE5_PLL_OFF_STS", BIT(30)}, 358 {"REF38P4_PLL_OFF_STS", BIT(31)}, 359 {} 360 }; 361 362 static const struct pmc_bit_map arl_pchs_power_gating_status_0_map[] = { 363 {"PMC_PGD0_PG_STS", BIT(0)}, 364 {"DMI_PGD0_PG_STS", BIT(1)}, 365 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 366 {"XHCI_PGD0_PG_STS", BIT(3)}, 367 {"SPA_PGD0_PG_STS", BIT(4)}, 368 {"SPB_PGD0_PG_STS", BIT(5)}, 369 {"SPC_PGD0_PG_STS", BIT(6)}, 370 {"GBE_PGD0_PG_STS", BIT(7)}, 371 {"SATA_PGD0_PG_STS", BIT(8)}, 372 {"FIA_X_PGD0_PG_STS", BIT(9)}, 373 {"MPFPW4_PGD0_PG_STS", BIT(10)}, 374 {"EAH_PGD0_PG_STS", BIT(11)}, 375 {"MPFPW1_PGD0_PG_STS", BIT(12)}, 376 {"SPD_PGD0_PG_STS", BIT(13)}, 377 {"LPSS_PGD0_PG_STS", BIT(14)}, 378 {"LPC_PGD0_PG_STS", BIT(15)}, 379 {"SMB_PGD0_PG_STS", BIT(16)}, 380 {"ISH_PGD0_PG_STS", BIT(17)}, 381 {"P2S_PGD0_PG_STS", BIT(18)}, 382 {"NPK_PGD0_PG_STS", BIT(19)}, 383 {"U3FPW1_PGD0_PG_STS", BIT(20)}, 384 {"PECI_PGD0_PG_STS", BIT(21)}, 385 {"FUSE_PGD0_PG_STS", BIT(22)}, 386 {"SBR8_PGD0_PG_STS", BIT(23)}, 387 {"EXE_PGD0_PG_STS", BIT(24)}, 388 {"XDCI_PGD0_PG_STS", BIT(25)}, 389 {"EXI_PGD0_PG_STS", BIT(26)}, 390 {"CSE_PGD0_PG_STS", BIT(27)}, 391 {"KVMCC_PGD0_PG_STS", BIT(28)}, 392 {"PMT_PGD0_PG_STS", BIT(29)}, 393 {"CLINK_PGD0_PG_STS", BIT(30)}, 394 {"PTIO_PGD0_PG_STS", BIT(31)}, 395 {} 396 }; 397 398 static const struct pmc_bit_map arl_pchs_power_gating_status_1_map[] = { 399 {"USBR0_PGD0_PG_STS", BIT(0)}, 400 {"SUSRAM_PGD0_PG_STS", BIT(1)}, 401 {"SMT1_PGD0_PG_STS", BIT(2)}, 402 {"SMT4_PGD0_PG_STS", BIT(3)}, 403 {"SMS2_PGD0_PG_STS", BIT(4)}, 404 {"SMS1_PGD0_PG_STS", BIT(5)}, 405 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 406 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 407 {"SBR0_PGD0_PG_STS", BIT(8)}, 408 {"SBR1_PGD0_PG_STS", BIT(9)}, 409 {"SBR2_PGD0_PG_STS", BIT(10)}, 410 {"SBR3_PGD0_PG_STS", BIT(11)}, 411 {"SBR4_PGD0_PG_STS", BIT(12)}, 412 {"SBR5_PGD0_PG_STS", BIT(13)}, 413 {"MPFPW3_PGD0_PG_STS", BIT(14)}, 414 {"PSF1_PGD0_PG_STS", BIT(15)}, 415 {"PSF2_PGD0_PG_STS", BIT(16)}, 416 {"PSF3_PGD0_PG_STS", BIT(17)}, 417 {"PSF4_PGD0_PG_STS", BIT(18)}, 418 {"CNVI_PGD0_PG_STS", BIT(19)}, 419 {"DMI3_PGD0_PG_STS", BIT(20)}, 420 {"ENDBG_PGD0_PG_STS", BIT(21)}, 421 {"DBG_SBR_PGD0_PG_STS", BIT(22)}, 422 {"SBR6_PGD0_PG_STS", BIT(23)}, 423 {"SBR7_PGD0_PG_STS", BIT(24)}, 424 {"NPK_PGD1_PG_STS", BIT(25)}, 425 {"U3FPW3_PGD0_PG_STS", BIT(26)}, 426 {"MPFPW2_PGD0_PG_STS", BIT(27)}, 427 {"MPFPW7_PGD0_PG_STS", BIT(28)}, 428 {"GBETSN1_PGD0_PG_STS", BIT(29)}, 429 {"PSF7_PGD0_PG_STS", BIT(30)}, 430 {"FIA2_PGD0_PG_STS", BIT(31)}, 431 {} 432 }; 433 434 static const struct pmc_bit_map arl_pchs_power_gating_status_2_map[] = { 435 {"U3FPW2_PGD0_PG_STS", BIT(0)}, 436 {"FIA_PGD0_PG_STS", BIT(1)}, 437 {"FIACPCB_X_PGD0_PG_STS", BIT(2)}, 438 {"FIA1_PGD0_PG_STS", BIT(3)}, 439 {"TAM_PGD0_PG_STS", BIT(4)}, 440 {"GBETSN_PGD0_PG_STS", BIT(5)}, 441 {"SBR9_PGD0_PG_STS", BIT(6)}, 442 {"THC0_PGD0_PG_STS", BIT(7)}, 443 {"THC1_PGD0_PG_STS", BIT(8)}, 444 {"PMC_PGD1_PG_STS", BIT(9)}, 445 {"DBC_PGD0_PG_STS", BIT(10)}, 446 {"DBG_PSF_PGD0_PG_STS", BIT(11)}, 447 {"SPF_PGD0_PG_STS", BIT(12)}, 448 {"ACE_PGD0_PG_STS", BIT(13)}, 449 {"ACE_PGD1_PG_STS", BIT(14)}, 450 {"ACE_PGD2_PG_STS", BIT(15)}, 451 {"ACE_PGD3_PG_STS", BIT(16)}, 452 {"ACE_PGD4_PG_STS", BIT(17)}, 453 {"ACE_PGD5_PG_STS", BIT(18)}, 454 {"ACE_PGD6_PG_STS", BIT(19)}, 455 {"ACE_PGD7_PG_STS", BIT(20)}, 456 {"SPE_PGD0_PG_STS", BIT(21)}, 457 {"MPFPW5_PG_STS", BIT(22)}, 458 {} 459 }; 460 461 static const struct pmc_bit_map arl_pchs_d3_status_0_map[] = { 462 {"SPF_D3_STS", BIT(0)}, 463 {"LPSS_D3_STS", BIT(3)}, 464 {"XDCI_D3_STS", BIT(4)}, 465 {"XHCI_D3_STS", BIT(5)}, 466 {"SPA_D3_STS", BIT(12)}, 467 {"SPB_D3_STS", BIT(13)}, 468 {"SPC_D3_STS", BIT(14)}, 469 {"SPD_D3_STS", BIT(15)}, 470 {"SPE_D3_STS", BIT(16)}, 471 {"ESPISPI_D3_STS", BIT(18)}, 472 {"SATA_D3_STS", BIT(20)}, 473 {"PSTH_D3_STS", BIT(21)}, 474 {"DMI_D3_STS", BIT(22)}, 475 {} 476 }; 477 478 static const struct pmc_bit_map arl_pchs_d3_status_1_map[] = { 479 {"GBETSN1_D3_STS", BIT(14)}, 480 {"GBE_D3_STS", BIT(19)}, 481 {"ITSS_D3_STS", BIT(23)}, 482 {"P2S_D3_STS", BIT(24)}, 483 {"CNVI_D3_STS", BIT(27)}, 484 {} 485 }; 486 487 static const struct pmc_bit_map arl_pchs_d3_status_2_map[] = { 488 {"CSMERTC_D3_STS", BIT(1)}, 489 {"SUSRAM_D3_STS", BIT(2)}, 490 {"CSE_D3_STS", BIT(4)}, 491 {"KVMCC_D3_STS", BIT(5)}, 492 {"USBR0_D3_STS", BIT(6)}, 493 {"ISH_D3_STS", BIT(7)}, 494 {"SMT1_D3_STS", BIT(8)}, 495 {"SMT2_D3_STS", BIT(9)}, 496 {"SMT3_D3_STS", BIT(10)}, 497 {"SMT4_D3_STS", BIT(11)}, 498 {"SMT5_D3_STS", BIT(12)}, 499 {"SMT6_D3_STS", BIT(13)}, 500 {"CLINK_D3_STS", BIT(14)}, 501 {"PTIO_D3_STS", BIT(16)}, 502 {"PMT_D3_STS", BIT(17)}, 503 {"SMS1_D3_STS", BIT(18)}, 504 {"SMS2_D3_STS", BIT(19)}, 505 {} 506 }; 507 508 static const struct pmc_bit_map arl_pchs_d3_status_3_map[] = { 509 {"ESE_D3_STS", BIT(3)}, 510 {"GBETSN_D3_STS", BIT(13)}, 511 {"THC0_D3_STS", BIT(14)}, 512 {"THC1_D3_STS", BIT(15)}, 513 {"ACE_D3_STS", BIT(23)}, 514 {} 515 }; 516 517 static const struct pmc_bit_map arl_pchs_vnn_req_status_0_map[] = { 518 {"FIA_VNN_REQ_STS", BIT(17)}, 519 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 520 {} 521 }; 522 523 static const struct pmc_bit_map arl_pchs_vnn_req_status_1_map[] = { 524 {"NPK_VNN_REQ_STS", BIT(4)}, 525 {"DFXAGG_VNN_REQ_STS", BIT(8)}, 526 {"EXI_VNN_REQ_STS", BIT(9)}, 527 {"GBE_VNN_REQ_STS", BIT(19)}, 528 {"SMB_VNN_REQ_STS", BIT(25)}, 529 {"LPC_VNN_REQ_STS", BIT(26)}, 530 {"CNVI_VNN_REQ_STS", BIT(27)}, 531 {} 532 }; 533 534 static const struct pmc_bit_map arl_pchs_vnn_req_status_2_map[] = { 535 {"FIA2_VNN_REQ_STS", BIT(0)}, 536 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 537 {"CSE_VNN_REQ_STS", BIT(4)}, 538 {"ISH_VNN_REQ_STS", BIT(7)}, 539 {"SMT1_VNN_REQ_STS", BIT(8)}, 540 {"SMT4_VNN_REQ_STS", BIT(11)}, 541 {"CLINK_VNN_REQ_STS", BIT(14)}, 542 {"SMS1_VNN_REQ_STS", BIT(18)}, 543 {"SMS2_VNN_REQ_STS", BIT(19)}, 544 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 545 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 546 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 547 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 548 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 549 {} 550 }; 551 552 static const struct pmc_bit_map arl_pchs_vnn_req_status_3_map[] = { 553 {"ESE_VNN_REQ_STS", BIT(3)}, 554 {"DTS0_VNN_REQ_STS", BIT(7)}, 555 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 556 {"FIA1_VNN_REQ_STS", BIT(12)}, 557 {} 558 }; 559 560 static const struct pmc_bit_map arl_pchs_vnn_misc_status_map[] = { 561 {"CPU_C10_REQ_STS", BIT(0)}, 562 {"TS_OFF_REQ_STS", BIT(1)}, 563 {"PNDE_MET_REQ_STS", BIT(2)}, 564 {"PCIE_DEEP_PM_REQ_STS", BIT(3)}, 565 {"FW_THROTTLE_ALLOWED_REQ_STS", BIT(4)}, 566 {"ISH_VNNAON_REQ_STS", BIT(7)}, 567 {"IOE_COND_MET_S02I2_0_REQ_STS", BIT(8)}, 568 {"IOE_COND_MET_S02I2_1_REQ_STS", BIT(9)}, 569 {"IOE_COND_MET_S02I2_2_REQ_STS", BIT(10)}, 570 {"PLT_GREATER_REQ_STS", BIT(11)}, 571 {"PMC_IDLE_FB_OCP_REQ_STS", BIT(13)}, 572 {"PM_SYNC_STATES_REQ_STS", BIT(14)}, 573 {"EA_REQ_STS", BIT(15)}, 574 {"DMI_CLKREQ_B_REQ_STS", BIT(16)}, 575 {"BRK_EV_EN_REQ_STS", BIT(17)}, 576 {"AUTO_DEMO_EN_REQ_STS", BIT(18)}, 577 {"ITSS_CLK_SRC_REQ_STS", BIT(19)}, 578 {"ARC_IDLE_REQ_STS", BIT(21)}, 579 {"DMI_IN_REQ_STS", BIT(22)}, 580 {"FIA_DEEP_PM_REQ_STS", BIT(23)}, 581 {"XDCI_ATTACHED_REQ_STS", BIT(24)}, 582 {"ARC_INTERRUPT_WAKE_REQ_STS", BIT(25)}, 583 {"PRE_WAKE0_REQ_STS", BIT(27)}, 584 {"PRE_WAKE1_REQ_STS", BIT(28)}, 585 {"PRE_WAKE2_EN_REQ_STS", BIT(29)}, 586 {"CNVI_V1P05_REQ_STS", BIT(31)}, 587 {} 588 }; 589 590 static const struct pmc_bit_map arl_pchs_signal_status_map[] = { 591 {"LSX_Wake0_STS", BIT(0)}, 592 {"LSX_Wake1_STS", BIT(1)}, 593 {"LSX_Wake2_STS", BIT(2)}, 594 {"LSX_Wake3_STS", BIT(3)}, 595 {"LSX_Wake4_STS", BIT(4)}, 596 {"LSX_Wake5_STS", BIT(5)}, 597 {"LSX_Wake6_STS", BIT(6)}, 598 {"LSX_Wake7_STS", BIT(7)}, 599 {"Int_Timer_SS_Wake0_STS", BIT(8)}, 600 {"Int_Timer_SS_Wake1_STS", BIT(9)}, 601 {"Int_Timer_SS_Wake0_STS", BIT(10)}, 602 {"Int_Timer_SS_Wake1_STS", BIT(11)}, 603 {"Int_Timer_SS_Wake2_STS", BIT(12)}, 604 {"Int_Timer_SS_Wake3_STS", BIT(13)}, 605 {"Int_Timer_SS_Wake4_STS", BIT(14)}, 606 {"Int_Timer_SS_Wake5_STS", BIT(15)}, 607 {} 608 }; 609 610 static const struct pmc_bit_map *arl_pchs_lpm_maps[] = { 611 arl_pchs_clocksource_status_map, 612 arl_pchs_power_gating_status_0_map, 613 arl_pchs_power_gating_status_1_map, 614 arl_pchs_power_gating_status_2_map, 615 arl_pchs_d3_status_0_map, 616 arl_pchs_d3_status_1_map, 617 arl_pchs_d3_status_2_map, 618 arl_pchs_d3_status_3_map, 619 arl_pchs_vnn_req_status_0_map, 620 arl_pchs_vnn_req_status_1_map, 621 arl_pchs_vnn_req_status_2_map, 622 arl_pchs_vnn_req_status_3_map, 623 arl_pchs_vnn_misc_status_map, 624 arl_pchs_signal_status_map, 625 NULL 626 }; 627 628 static const struct pmc_reg_map arl_pchs_reg_map = { 629 .pfear_sts = ext_arl_socs_pfear_map, 630 .ppfear_buckets = ARL_SOCS_PPFEAR_NUM_ENTRIES, 631 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 632 .ltr_ignore_max = ARL_SOCS_NUM_IP_IGN_ALLOWED, 633 .lpm_sts = arl_pchs_lpm_maps, 634 .ltr_show_sts = arl_pchs_ltr_show_map, 635 .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, 636 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 637 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 638 .msr_sts = msr_map, 639 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 640 .regmap_length = ARL_PCH_PMC_MMIO_REG_LEN, 641 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 642 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 643 .lpm_priority_offset = MTL_LPM_PRI_OFFSET, 644 .lpm_en_offset = MTL_LPM_EN_OFFSET, 645 .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET, 646 .lpm_status_offset = MTL_LPM_STATUS_OFFSET, 647 .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET, 648 .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET, 649 .lpm_num_maps = ADL_LPM_NUM_MAPS, 650 .lpm_reg_index = ARL_LPM_REG_INDEX, 651 .etr3_offset = ETR3_OFFSET, 652 .lpm_req_guid = PCHS_LPM_REQ_GUID, 653 }; 654 655 static struct pmc_info arl_pmc_info_list[] = { 656 { 657 .devid = PMC_DEVID_ARL_IOEP, 658 .map = &mtl_ioep_reg_map, 659 }, 660 { 661 .devid = PMC_DEVID_ARL_SOCS, 662 .map = &arl_socs_reg_map, 663 }, 664 { 665 .devid = PMC_DEVID_ARL_PCHS, 666 .map = &arl_pchs_reg_map, 667 }, 668 { 669 .devid = PMC_DEVID_ARL_SOCM, 670 .map = &mtl_socm_reg_map, 671 }, 672 {} 673 }; 674 675 #define ARL_NPU_PCI_DEV 0xad1d 676 #define ARL_GNA_PCI_DEV 0xae4c 677 #define ARL_H_NPU_PCI_DEV 0x7d1d 678 #define ARL_H_GNA_PCI_DEV 0x774c 679 /* 680 * Set power state of select devices that do not have drivers to D3 681 * so that they do not block Package C entry. 682 */ 683 static void arl_d3_fixup(void) 684 { 685 pmc_core_set_device_d3(ARL_NPU_PCI_DEV); 686 pmc_core_set_device_d3(ARL_GNA_PCI_DEV); 687 } 688 689 static void arl_h_d3_fixup(void) 690 { 691 pmc_core_set_device_d3(ARL_H_NPU_PCI_DEV); 692 pmc_core_set_device_d3(ARL_H_GNA_PCI_DEV); 693 } 694 695 static int arl_resume(struct pmc_dev *pmcdev) 696 { 697 arl_d3_fixup(); 698 699 return cnl_resume(pmcdev); 700 } 701 702 static int arl_h_resume(struct pmc_dev *pmcdev) 703 { 704 arl_h_d3_fixup(); 705 706 return cnl_resume(pmcdev); 707 } 708 709 static int arl_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 710 { 711 arl_d3_fixup(); 712 return generic_core_init(pmcdev, pmc_dev_info); 713 } 714 715 static int arl_h_core_init(struct pmc_dev *pmcdev, struct pmc_dev_info *pmc_dev_info) 716 { 717 arl_h_d3_fixup(); 718 return generic_core_init(pmcdev, pmc_dev_info); 719 } 720 721 static u32 ARL_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, 0x0}; 722 struct pmc_dev_info arl_pmc_dev = { 723 .pci_func = 0, 724 .dmu_guids = ARL_PMT_DMU_GUIDS, 725 .regmap_list = arl_pmc_info_list, 726 .map = &arl_socs_reg_map, 727 .sub_req_show = &pmc_core_substate_req_regs_fops, 728 .suspend = cnl_suspend, 729 .resume = arl_resume, 730 .init = arl_core_init, 731 .sub_req = pmc_core_pmt_get_lpm_req, 732 }; 733 734 static u32 ARL_H_PMT_DMU_GUIDS[] = {ARL_PMT_DMU_GUID, ARL_H_PMT_DMU_GUID, 0x0}; 735 struct pmc_dev_info arl_h_pmc_dev = { 736 .pci_func = 2, 737 .dmu_guids = ARL_H_PMT_DMU_GUIDS, 738 .regmap_list = arl_pmc_info_list, 739 .map = &mtl_socm_reg_map, 740 .sub_req_show = &pmc_core_substate_req_regs_fops, 741 .suspend = cnl_suspend, 742 .resume = arl_h_resume, 743 .init = arl_h_core_init, 744 .sub_req = pmc_core_pmt_get_lpm_req, 745 }; 746