1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains platform specific structure definitions 4 * and init function used by Alder Lake PCH. 5 * 6 * Copyright (c) 2022, Intel Corporation. 7 * All Rights Reserved. 8 * 9 */ 10 11 #include "core.h" 12 13 /* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */ 14 const struct pmc_bit_map adl_pfear_map[] = { 15 {"SPI/eSPI", BIT(2)}, 16 {"XHCI", BIT(3)}, 17 {"SPA", BIT(4)}, 18 {"SPB", BIT(5)}, 19 {"SPC", BIT(6)}, 20 {"GBE", BIT(7)}, 21 22 {"SATA", BIT(0)}, 23 {"HDA_PGD0", BIT(1)}, 24 {"HDA_PGD1", BIT(2)}, 25 {"HDA_PGD2", BIT(3)}, 26 {"HDA_PGD3", BIT(4)}, 27 {"SPD", BIT(5)}, 28 {"LPSS", BIT(6)}, 29 30 {"SMB", BIT(0)}, 31 {"ISH", BIT(1)}, 32 {"ITH", BIT(3)}, 33 34 {"XDCI", BIT(1)}, 35 {"DCI", BIT(2)}, 36 {"CSE", BIT(3)}, 37 {"CSME_KVM", BIT(4)}, 38 {"CSME_PMT", BIT(5)}, 39 {"CSME_CLINK", BIT(6)}, 40 {"CSME_PTIO", BIT(7)}, 41 42 {"CSME_USBR", BIT(0)}, 43 {"CSME_SUSRAM", BIT(1)}, 44 {"CSME_SMT1", BIT(2)}, 45 {"CSME_SMS2", BIT(4)}, 46 {"CSME_SMS1", BIT(5)}, 47 {"CSME_RTC", BIT(6)}, 48 {"CSME_PSF", BIT(7)}, 49 50 {"CNVI", BIT(3)}, 51 {"HDA_PGD4", BIT(2)}, 52 {"HDA_PGD5", BIT(3)}, 53 {"HDA_PGD6", BIT(4)}, 54 {} 55 }; 56 57 const struct pmc_bit_map *ext_adl_pfear_map[] = { 58 /* 59 * Check intel_pmc_core_ids[] users of cnp_reg_map for 60 * a list of core SoCs using this. 61 */ 62 adl_pfear_map, 63 NULL 64 }; 65 66 const struct pmc_bit_map adl_ltr_show_map[] = { 67 {"SOUTHPORT_A", CNP_PMC_LTR_SPA}, 68 {"SOUTHPORT_B", CNP_PMC_LTR_SPB}, 69 {"SATA", CNP_PMC_LTR_SATA}, 70 {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE}, 71 {"XHCI", CNP_PMC_LTR_XHCI}, 72 {"SOUTHPORT_F", ADL_PMC_LTR_SPF}, 73 {"ME", CNP_PMC_LTR_ME}, 74 /* EVA is Enterprise Value Add, doesn't really exist on PCH */ 75 {"SATA1", CNP_PMC_LTR_EVA}, 76 {"SOUTHPORT_C", CNP_PMC_LTR_SPC}, 77 {"HD_AUDIO", CNP_PMC_LTR_AZ}, 78 {"CNV", CNP_PMC_LTR_CNV}, 79 {"LPSS", CNP_PMC_LTR_LPSS}, 80 {"SOUTHPORT_D", CNP_PMC_LTR_SPD}, 81 {"SOUTHPORT_E", CNP_PMC_LTR_SPE}, 82 {"SATA2", CNP_PMC_LTR_CAM}, 83 {"ESPI", CNP_PMC_LTR_ESPI}, 84 {"SCC", CNP_PMC_LTR_SCC}, 85 {"ISH", CNP_PMC_LTR_ISH}, 86 {"UFSX2", CNP_PMC_LTR_UFSX2}, 87 {"EMMC", CNP_PMC_LTR_EMMC}, 88 /* 89 * Check intel_pmc_core_ids[] users of cnp_reg_map for 90 * a list of core SoCs using this. 91 */ 92 {"WIGIG", ICL_PMC_LTR_WIGIG}, 93 {"THC0", TGL_PMC_LTR_THC0}, 94 {"THC1", TGL_PMC_LTR_THC1}, 95 {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED}, 96 97 /* Below two cannot be used for LTR_IGNORE */ 98 {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT}, 99 {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, 100 {} 101 }; 102 103 const struct pmc_bit_map adl_clocksource_status_map[] = { 104 {"CLKPART1_OFF_STS", BIT(0)}, 105 {"CLKPART2_OFF_STS", BIT(1)}, 106 {"CLKPART3_OFF_STS", BIT(2)}, 107 {"CLKPART4_OFF_STS", BIT(3)}, 108 {"CLKPART5_OFF_STS", BIT(4)}, 109 {"CLKPART6_OFF_STS", BIT(5)}, 110 {"CLKPART7_OFF_STS", BIT(6)}, 111 {"CLKPART8_OFF_STS", BIT(7)}, 112 {"PCIE0PLL_OFF_STS", BIT(10)}, 113 {"PCIE1PLL_OFF_STS", BIT(11)}, 114 {"PCIE2PLL_OFF_STS", BIT(12)}, 115 {"PCIE3PLL_OFF_STS", BIT(13)}, 116 {"PCIE4PLL_OFF_STS", BIT(14)}, 117 {"PCIE5PLL_OFF_STS", BIT(15)}, 118 {"PCIE6PLL_OFF_STS", BIT(16)}, 119 {"USB2PLL_OFF_STS", BIT(18)}, 120 {"OCPLL_OFF_STS", BIT(22)}, 121 {"AUDIOPLL_OFF_STS", BIT(23)}, 122 {"GBEPLL_OFF_STS", BIT(24)}, 123 {"Fast_XTAL_Osc_OFF_STS", BIT(25)}, 124 {"AC_Ring_Osc_OFF_STS", BIT(26)}, 125 {"MC_Ring_Osc_OFF_STS", BIT(27)}, 126 {"SATAPLL_OFF_STS", BIT(29)}, 127 {"USB3PLL_OFF_STS", BIT(31)}, 128 {} 129 }; 130 131 const struct pmc_bit_map adl_power_gating_status_0_map[] = { 132 {"PMC_PGD0_PG_STS", BIT(0)}, 133 {"DMI_PGD0_PG_STS", BIT(1)}, 134 {"ESPISPI_PGD0_PG_STS", BIT(2)}, 135 {"XHCI_PGD0_PG_STS", BIT(3)}, 136 {"SPA_PGD0_PG_STS", BIT(4)}, 137 {"SPB_PGD0_PG_STS", BIT(5)}, 138 {"SPC_PGD0_PG_STS", BIT(6)}, 139 {"GBE_PGD0_PG_STS", BIT(7)}, 140 {"SATA_PGD0_PG_STS", BIT(8)}, 141 {"DSP_PGD0_PG_STS", BIT(9)}, 142 {"DSP_PGD1_PG_STS", BIT(10)}, 143 {"DSP_PGD2_PG_STS", BIT(11)}, 144 {"DSP_PGD3_PG_STS", BIT(12)}, 145 {"SPD_PGD0_PG_STS", BIT(13)}, 146 {"LPSS_PGD0_PG_STS", BIT(14)}, 147 {"SMB_PGD0_PG_STS", BIT(16)}, 148 {"ISH_PGD0_PG_STS", BIT(17)}, 149 {"NPK_PGD0_PG_STS", BIT(19)}, 150 {"PECI_PGD0_PG_STS", BIT(21)}, 151 {"XDCI_PGD0_PG_STS", BIT(25)}, 152 {"EXI_PGD0_PG_STS", BIT(26)}, 153 {"CSE_PGD0_PG_STS", BIT(27)}, 154 {"KVMCC_PGD0_PG_STS", BIT(28)}, 155 {"PMT_PGD0_PG_STS", BIT(29)}, 156 {"CLINK_PGD0_PG_STS", BIT(30)}, 157 {"PTIO_PGD0_PG_STS", BIT(31)}, 158 {} 159 }; 160 161 const struct pmc_bit_map adl_power_gating_status_1_map[] = { 162 {"USBR0_PGD0_PG_STS", BIT(0)}, 163 {"SMT1_PGD0_PG_STS", BIT(2)}, 164 {"CSMERTC_PGD0_PG_STS", BIT(6)}, 165 {"CSMEPSF_PGD0_PG_STS", BIT(7)}, 166 {"CNVI_PGD0_PG_STS", BIT(19)}, 167 {"DSP_PGD4_PG_STS", BIT(26)}, 168 {"SPG_PGD0_PG_STS", BIT(27)}, 169 {"SPE_PGD0_PG_STS", BIT(28)}, 170 {} 171 }; 172 173 const struct pmc_bit_map adl_power_gating_status_2_map[] = { 174 {"THC0_PGD0_PG_STS", BIT(7)}, 175 {"THC1_PGD0_PG_STS", BIT(8)}, 176 {"SPF_PGD0_PG_STS", BIT(14)}, 177 {} 178 }; 179 180 const struct pmc_bit_map adl_d3_status_0_map[] = { 181 {"ISH_D3_STS", BIT(2)}, 182 {"LPSS_D3_STS", BIT(3)}, 183 {"XDCI_D3_STS", BIT(4)}, 184 {"XHCI_D3_STS", BIT(5)}, 185 {"SPA_D3_STS", BIT(12)}, 186 {"SPB_D3_STS", BIT(13)}, 187 {"SPC_D3_STS", BIT(14)}, 188 {"SPD_D3_STS", BIT(15)}, 189 {"SPE_D3_STS", BIT(16)}, 190 {"DSP_D3_STS", BIT(19)}, 191 {"SATA_D3_STS", BIT(20)}, 192 {"DMI_D3_STS", BIT(22)}, 193 {} 194 }; 195 196 const struct pmc_bit_map adl_d3_status_1_map[] = { 197 {"GBE_D3_STS", BIT(19)}, 198 {"CNVI_D3_STS", BIT(27)}, 199 {} 200 }; 201 202 const struct pmc_bit_map adl_d3_status_2_map[] = { 203 {"CSMERTC_D3_STS", BIT(1)}, 204 {"CSE_D3_STS", BIT(4)}, 205 {"KVMCC_D3_STS", BIT(5)}, 206 {"USBR0_D3_STS", BIT(6)}, 207 {"SMT1_D3_STS", BIT(8)}, 208 {"PTIO_D3_STS", BIT(16)}, 209 {"PMT_D3_STS", BIT(17)}, 210 {} 211 }; 212 213 const struct pmc_bit_map adl_d3_status_3_map[] = { 214 {"THC0_D3_STS", BIT(14)}, 215 {"THC1_D3_STS", BIT(15)}, 216 {} 217 }; 218 219 const struct pmc_bit_map adl_vnn_req_status_0_map[] = { 220 {"ISH_VNN_REQ_STS", BIT(2)}, 221 {"ESPISPI_VNN_REQ_STS", BIT(18)}, 222 {"DSP_VNN_REQ_STS", BIT(19)}, 223 {} 224 }; 225 226 const struct pmc_bit_map adl_vnn_req_status_1_map[] = { 227 {"NPK_VNN_REQ_STS", BIT(4)}, 228 {"EXI_VNN_REQ_STS", BIT(9)}, 229 {"GBE_VNN_REQ_STS", BIT(19)}, 230 {"SMB_VNN_REQ_STS", BIT(25)}, 231 {"CNVI_VNN_REQ_STS", BIT(27)}, 232 {} 233 }; 234 235 const struct pmc_bit_map adl_vnn_req_status_2_map[] = { 236 {"CSMERTC_VNN_REQ_STS", BIT(1)}, 237 {"CSE_VNN_REQ_STS", BIT(4)}, 238 {"SMT1_VNN_REQ_STS", BIT(8)}, 239 {"CLINK_VNN_REQ_STS", BIT(14)}, 240 {"GPIOCOM4_VNN_REQ_STS", BIT(20)}, 241 {"GPIOCOM3_VNN_REQ_STS", BIT(21)}, 242 {"GPIOCOM2_VNN_REQ_STS", BIT(22)}, 243 {"GPIOCOM1_VNN_REQ_STS", BIT(23)}, 244 {"GPIOCOM0_VNN_REQ_STS", BIT(24)}, 245 {} 246 }; 247 248 const struct pmc_bit_map adl_vnn_req_status_3_map[] = { 249 {"GPIOCOM5_VNN_REQ_STS", BIT(11)}, 250 {} 251 }; 252 253 const struct pmc_bit_map adl_vnn_misc_status_map[] = { 254 {"CPU_C10_REQ_STS", BIT(0)}, 255 {"PCIe_LPM_En_REQ_STS", BIT(3)}, 256 {"ITH_REQ_STS", BIT(5)}, 257 {"CNVI_REQ_STS", BIT(6)}, 258 {"ISH_REQ_STS", BIT(7)}, 259 {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)}, 260 {"PCIe_Clk_REQ_STS", BIT(12)}, 261 {"MPHY_Core_DL_REQ_STS", BIT(16)}, 262 {"Break-even_En_REQ_STS", BIT(17)}, 263 {"MPHY_SUS_REQ_STS", BIT(22)}, 264 {"xDCI_attached_REQ_STS", BIT(24)}, 265 {} 266 }; 267 268 const struct pmc_bit_map *adl_lpm_maps[] = { 269 adl_clocksource_status_map, 270 adl_power_gating_status_0_map, 271 adl_power_gating_status_1_map, 272 adl_power_gating_status_2_map, 273 adl_d3_status_0_map, 274 adl_d3_status_1_map, 275 adl_d3_status_2_map, 276 adl_d3_status_3_map, 277 adl_vnn_req_status_0_map, 278 adl_vnn_req_status_1_map, 279 adl_vnn_req_status_2_map, 280 adl_vnn_req_status_3_map, 281 adl_vnn_misc_status_map, 282 tgl_signal_status_map, 283 NULL 284 }; 285 286 const struct pmc_reg_map adl_reg_map = { 287 .pfear_sts = ext_adl_pfear_map, 288 .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET, 289 .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP, 290 .ltr_show_sts = adl_ltr_show_map, 291 .msr_sts = msr_map, 292 .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, 293 .regmap_length = CNP_PMC_MMIO_REG_LEN, 294 .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, 295 .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, 296 .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, 297 .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, 298 .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED, 299 .lpm_num_modes = ADL_LPM_NUM_MODES, 300 .lpm_num_maps = ADL_LPM_NUM_MAPS, 301 .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2, 302 .etr3_offset = ETR3_OFFSET, 303 .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET, 304 .lpm_priority_offset = ADL_LPM_PRI_OFFSET, 305 .lpm_en_offset = ADL_LPM_EN_OFFSET, 306 .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET, 307 .lpm_sts = adl_lpm_maps, 308 .lpm_status_offset = ADL_LPM_STATUS_OFFSET, 309 .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET, 310 .pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET, 311 .pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP, 312 }; 313 314 int adl_core_init(struct pmc_dev *pmcdev) 315 { 316 struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN]; 317 int ret; 318 319 pmcdev->suspend = cnl_suspend; 320 pmcdev->resume = cnl_resume; 321 322 pmc->map = &adl_reg_map; 323 ret = get_primary_reg_base(pmc); 324 if (ret) 325 return ret; 326 327 pmc_core_get_low_power_modes(pmcdev); 328 329 return 0; 330 } 331