1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/input.h> 16 #include <linux/platform_profile.h> 17 18 #define POLICY_BUF_MAX_SZ 0x4b000 19 #define POLICY_SIGN_COOKIE 0x31535024 20 #define POLICY_COOKIE_OFFSET 0x10 21 22 struct cookie_header { 23 u32 sign; 24 u32 length; 25 } __packed; 26 27 /* APMF Functions */ 28 #define APMF_FUNC_VERIFY_INTERFACE 0 29 #define APMF_FUNC_GET_SYS_PARAMS 1 30 #define APMF_FUNC_SBIOS_REQUESTS 2 31 #define APMF_FUNC_SBIOS_HEARTBEAT 4 32 #define APMF_FUNC_AUTO_MODE 5 33 #define APMF_FUNC_SET_FAN_IDX 7 34 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 35 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 36 #define APMF_FUNC_DYN_SLIDER_AC 11 37 #define APMF_FUNC_DYN_SLIDER_DC 12 38 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 39 40 /* Message Definitions */ 41 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 42 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 43 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 44 #define GET_SPL 0x0B 45 #define GET_SPPT 0x0D 46 #define GET_FPPT 0x0F 47 #define SET_DRAM_ADDR_HIGH 0x14 48 #define SET_DRAM_ADDR_LOW 0x15 49 #define SET_TRANSFER_TABLE 0x16 50 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 51 #define SET_STT_LIMIT_APU 0x19 52 #define SET_STT_LIMIT_HS2 0x1A 53 #define SET_SPPT_APU_ONLY 0x1D 54 #define GET_SPPT_APU_ONLY 0x1E 55 #define GET_STT_MIN_LIMIT 0x1F 56 #define GET_STT_LIMIT_APU 0x20 57 #define GET_STT_LIMIT_HS2 0x21 58 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 59 #define SET_PMF_PPT 0x25 60 #define SET_PMF_PPT_APU_ONLY 0x26 61 62 /* OS slider update notification */ 63 #define DC_BEST_PERF 0 64 #define DC_BETTER_PERF 1 65 #define DC_BATTERY_SAVER 3 66 #define AC_BEST_PERF 4 67 #define AC_BETTER_PERF 5 68 #define AC_BETTER_BATTERY 6 69 70 /* Fan Index for Auto Mode */ 71 #define FAN_INDEX_AUTO 0xFFFFFFFF 72 73 #define ARG_NONE 0 74 #define AVG_SAMPLE_SIZE 3 75 76 /* Policy Actions */ 77 #define PMF_POLICY_SPL 2 78 #define PMF_POLICY_SPPT 3 79 #define PMF_POLICY_FPPT 4 80 #define PMF_POLICY_SPPT_APU_ONLY 5 81 #define PMF_POLICY_STT_MIN 6 82 #define PMF_POLICY_STT_SKINTEMP_APU 7 83 #define PMF_POLICY_STT_SKINTEMP_HS2 8 84 #define PMF_POLICY_SYSTEM_STATE 9 85 #define PMF_POLICY_P3T 38 86 87 /* TA macros */ 88 #define PMF_TA_IF_VERSION_MAJOR 1 89 #define TA_PMF_ACTION_MAX 32 90 #define TA_PMF_UNDO_MAX 8 91 #define TA_OUTPUT_RESERVED_MEM 906 92 #define MAX_OPERATION_PARAMS 4 93 94 #define PMF_IF_V1 1 95 #define PMF_IF_V2 2 96 97 #define APTS_MAX_STATES 16 98 99 /* APTS PMF BIOS Interface */ 100 struct amd_pmf_apts_output { 101 u16 table_version; 102 u32 fan_table_idx; 103 u32 pmf_ppt; 104 u32 ppt_pmf_apu_only; 105 u32 stt_min_limit; 106 u8 stt_skin_temp_limit_apu; 107 u8 stt_skin_temp_limit_hs2; 108 } __packed; 109 110 struct amd_pmf_apts_granular_output { 111 u16 size; 112 struct amd_pmf_apts_output val; 113 } __packed; 114 115 struct amd_pmf_apts_granular { 116 u16 size; 117 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 118 }; 119 120 struct sbios_hb_event_v2 { 121 u16 size; 122 u8 load; 123 u8 unload; 124 u8 suspend; 125 u8 resume; 126 } __packed; 127 128 enum sbios_hb_v2 { 129 ON_LOAD, 130 ON_UNLOAD, 131 ON_SUSPEND, 132 ON_RESUME, 133 }; 134 135 /* AMD PMF BIOS interfaces */ 136 struct apmf_verify_interface { 137 u16 size; 138 u16 version; 139 u32 notification_mask; 140 u32 supported_functions; 141 } __packed; 142 143 struct apmf_system_params { 144 u16 size; 145 u32 valid_mask; 146 u32 flags; 147 u8 command_code; 148 u32 heartbeat_int; 149 } __packed; 150 151 struct apmf_sbios_req { 152 u16 size; 153 u32 pending_req; 154 u8 rsd; 155 u8 cql_event; 156 u8 amt_event; 157 u32 fppt; 158 u32 sppt; 159 u32 fppt_apu_only; 160 u32 spl; 161 u32 stt_min_limit; 162 u8 skin_temp_apu; 163 u8 skin_temp_hs2; 164 } __packed; 165 166 struct apmf_sbios_req_v2 { 167 u16 size; 168 u32 pending_req; 169 u8 rsd; 170 u32 ppt_pmf; 171 u32 ppt_pmf_apu_only; 172 u32 stt_min_limit; 173 u8 skin_temp_apu; 174 u8 skin_temp_hs2; 175 u32 custom_policy[10]; 176 } __packed; 177 178 struct apmf_fan_idx { 179 u16 size; 180 u8 fan_ctl_mode; 181 u32 fan_ctl_idx; 182 } __packed; 183 184 struct smu_pmf_metrics { 185 u16 gfxclk_freq; /* in MHz */ 186 u16 socclk_freq; /* in MHz */ 187 u16 vclk_freq; /* in MHz */ 188 u16 dclk_freq; /* in MHz */ 189 u16 memclk_freq; /* in MHz */ 190 u16 spare; 191 u16 gfx_activity; /* in Centi */ 192 u16 uvd_activity; /* in Centi */ 193 u16 voltage[2]; /* in mV */ 194 u16 currents[2]; /* in mA */ 195 u16 power[2];/* in mW */ 196 u16 core_freq[8]; /* in MHz */ 197 u16 core_power[8]; /* in mW */ 198 u16 core_temp[8]; /* in centi-Celsius */ 199 u16 l3_freq; /* in MHz */ 200 u16 l3_temp; /* in centi-Celsius */ 201 u16 gfx_temp; /* in centi-Celsius */ 202 u16 soc_temp; /* in centi-Celsius */ 203 u16 throttler_status; 204 u16 current_socketpower; /* in mW */ 205 u16 stapm_orig_limit; /* in W */ 206 u16 stapm_cur_limit; /* in W */ 207 u32 apu_power; /* in mW */ 208 u32 dgpu_power; /* in mW */ 209 u16 vdd_tdc_val; /* in mA */ 210 u16 soc_tdc_val; /* in mA */ 211 u16 vdd_edc_val; /* in mA */ 212 u16 soc_edcv_al; /* in mA */ 213 u16 infra_cpu_maxfreq; /* in MHz */ 214 u16 infra_gfx_maxfreq; /* in MHz */ 215 u16 skin_temp; /* in centi-Celsius */ 216 u16 device_state; 217 u16 curtemp; /* in centi-Celsius */ 218 u16 filter_alpha_value; 219 u16 avg_gfx_clkfrequency; 220 u16 avg_fclk_frequency; 221 u16 avg_gfx_activity; 222 u16 avg_socclk_frequency; 223 u16 avg_vclk_frequency; 224 u16 avg_vcn_activity; 225 u16 avg_dram_reads; 226 u16 avg_dram_writes; 227 u16 avg_socket_power; 228 u16 avg_core_power[2]; 229 u16 avg_core_c0residency[16]; 230 u16 spare1; 231 u32 metrics_counter; 232 } __packed; 233 234 enum amd_stt_skin_temp { 235 STT_TEMP_APU, 236 STT_TEMP_HS2, 237 STT_TEMP_COUNT, 238 }; 239 240 enum amd_slider_op { 241 SLIDER_OP_GET, 242 SLIDER_OP_SET, 243 }; 244 245 enum power_source { 246 POWER_SOURCE_AC, 247 POWER_SOURCE_DC, 248 POWER_SOURCE_MAX, 249 }; 250 251 enum power_modes { 252 POWER_MODE_PERFORMANCE, 253 POWER_MODE_BALANCED_POWER, 254 POWER_MODE_POWER_SAVER, 255 POWER_MODE_MAX, 256 }; 257 258 enum power_modes_v2 { 259 POWER_MODE_BEST_PERFORMANCE, 260 POWER_MODE_BALANCED, 261 POWER_MODE_BEST_POWER_EFFICIENCY, 262 POWER_MODE_ENERGY_SAVE, 263 POWER_MODE_V2_MAX, 264 }; 265 266 struct amd_pmf_dev { 267 void __iomem *regbase; 268 void __iomem *smu_virt_addr; 269 void *buf; 270 u32 base_addr; 271 u32 cpu_id; 272 struct device *dev; 273 struct mutex lock; /* protects the PMF interface */ 274 u32 supported_func; 275 enum platform_profile_option current_profile; 276 struct platform_profile_handler pprof; 277 struct dentry *dbgfs_dir; 278 int hb_interval; /* SBIOS heartbeat interval */ 279 struct delayed_work heart_beat; 280 struct smu_pmf_metrics m_table; 281 struct delayed_work work_buffer; 282 ktime_t start_time; 283 int socket_power_history[AVG_SAMPLE_SIZE]; 284 int socket_power_history_idx; 285 bool amt_enabled; 286 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 287 bool cnqf_enabled; 288 bool cnqf_supported; 289 struct notifier_block pwr_src_notifier; 290 /* Smart PC solution builder */ 291 struct dentry *esbin; 292 unsigned char *policy_buf; 293 u32 policy_sz; 294 struct tee_context *tee_ctx; 295 struct tee_shm *fw_shm_pool; 296 u32 session_id; 297 void *shbuf; 298 struct delayed_work pb_work; 299 struct pmf_action_table *prev_data; 300 u64 policy_addr; 301 void __iomem *policy_base; 302 bool smart_pc_enabled; 303 u16 pmf_if_version; 304 struct input_dev *pmf_idev; 305 }; 306 307 struct apmf_sps_prop_granular_v2 { 308 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 309 } __packed; 310 311 struct apmf_sps_prop_granular { 312 u32 fppt; 313 u32 sppt; 314 u32 sppt_apu_only; 315 u32 spl; 316 u32 stt_min; 317 u8 stt_skin_temp[STT_TEMP_COUNT]; 318 u32 fan_id; 319 } __packed; 320 321 /* Static Slider */ 322 struct apmf_static_slider_granular_output { 323 u16 size; 324 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 325 } __packed; 326 327 struct amd_pmf_static_slider_granular { 328 u16 size; 329 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 330 }; 331 332 struct apmf_static_slider_granular_output_v2 { 333 u16 size; 334 struct apmf_sps_prop_granular_v2 sps_idx; 335 } __packed; 336 337 struct amd_pmf_static_slider_granular_v2 { 338 u16 size; 339 struct apmf_sps_prop_granular_v2 sps_idx; 340 }; 341 342 struct os_power_slider { 343 u16 size; 344 u8 slider_event; 345 } __packed; 346 347 struct fan_table_control { 348 bool manual; 349 unsigned long fan_id; 350 }; 351 352 struct power_table_control { 353 u32 spl; 354 u32 sppt; 355 u32 fppt; 356 u32 sppt_apu_only; 357 u32 stt_min; 358 u32 stt_skin_temp[STT_TEMP_COUNT]; 359 u32 reserved[16]; 360 }; 361 362 /* Auto Mode Layer */ 363 enum auto_mode_transition_priority { 364 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 365 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 366 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 367 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 368 AUTO_TRANSITION_MAX, 369 }; 370 371 enum auto_mode_mode { 372 AUTO_QUIET, 373 AUTO_BALANCE, 374 AUTO_PERFORMANCE_ON_LAP, 375 AUTO_PERFORMANCE, 376 AUTO_MODE_MAX, 377 }; 378 379 struct auto_mode_trans_params { 380 u32 time_constant; /* minimum time required to switch to next mode */ 381 u32 power_delta; /* delta power to shift mode */ 382 u32 power_threshold; 383 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 384 u32 applied; 385 enum auto_mode_mode target_mode; 386 u32 shifting_up; 387 }; 388 389 struct auto_mode_mode_settings { 390 struct power_table_control power_control; 391 struct fan_table_control fan_control; 392 u32 power_floor; 393 }; 394 395 struct auto_mode_mode_config { 396 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 397 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 398 enum auto_mode_mode current_mode; 399 }; 400 401 struct apmf_auto_mode { 402 u16 size; 403 /* time constant */ 404 u32 balanced_to_perf; 405 u32 perf_to_balanced; 406 u32 quiet_to_balanced; 407 u32 balanced_to_quiet; 408 /* power floor */ 409 u32 pfloor_perf; 410 u32 pfloor_balanced; 411 u32 pfloor_quiet; 412 /* Power delta for mode change */ 413 u32 pd_balanced_to_perf; 414 u32 pd_perf_to_balanced; 415 u32 pd_quiet_to_balanced; 416 u32 pd_balanced_to_quiet; 417 /* skin temperature limits */ 418 u8 stt_apu_perf_on_lap; /* CQL ON */ 419 u8 stt_hs2_perf_on_lap; /* CQL ON */ 420 u8 stt_apu_perf; 421 u8 stt_hs2_perf; 422 u8 stt_apu_balanced; 423 u8 stt_hs2_balanced; 424 u8 stt_apu_quiet; 425 u8 stt_hs2_quiet; 426 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 427 u32 stt_min_limit_perf; 428 u32 stt_min_limit_balanced; 429 u32 stt_min_limit_quiet; 430 /* SPL based */ 431 u32 fppt_perf_on_lap; /* CQL ON */ 432 u32 sppt_perf_on_lap; /* CQL ON */ 433 u32 spl_perf_on_lap; /* CQL ON */ 434 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 435 u32 fppt_perf; 436 u32 sppt_perf; 437 u32 spl_perf; 438 u32 sppt_apu_only_perf; 439 u32 fppt_balanced; 440 u32 sppt_balanced; 441 u32 spl_balanced; 442 u32 sppt_apu_only_balanced; 443 u32 fppt_quiet; 444 u32 sppt_quiet; 445 u32 spl_quiet; 446 u32 sppt_apu_only_quiet; 447 /* Fan ID */ 448 u32 fan_id_perf; 449 u32 fan_id_balanced; 450 u32 fan_id_quiet; 451 } __packed; 452 453 /* CnQF Layer */ 454 enum cnqf_trans_priority { 455 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 456 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 457 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 458 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 459 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 460 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 461 CNQF_TRANSITION_MAX, 462 }; 463 464 enum cnqf_mode { 465 CNQF_MODE_QUIET, 466 CNQF_MODE_BALANCE, 467 CNQF_MODE_PERFORMANCE, 468 CNQF_MODE_TURBO, 469 CNQF_MODE_MAX, 470 }; 471 472 enum apmf_cnqf_pos { 473 APMF_CNQF_TURBO, 474 APMF_CNQF_PERFORMANCE, 475 APMF_CNQF_BALANCE, 476 APMF_CNQF_QUIET, 477 APMF_CNQF_MAX, 478 }; 479 480 struct cnqf_mode_settings { 481 struct power_table_control power_control; 482 struct fan_table_control fan_control; 483 u32 power_floor; 484 }; 485 486 struct cnqf_tran_params { 487 u32 time_constant; /* minimum time required to switch to next mode */ 488 u32 power_threshold; 489 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 490 u32 total_power; 491 u32 count; 492 bool priority; 493 bool shifting_up; 494 enum cnqf_mode target_mode; 495 }; 496 497 struct cnqf_config { 498 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 499 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 500 struct power_table_control defaults; 501 enum cnqf_mode current_mode; 502 u32 power_src; 503 u32 avg_power; 504 }; 505 506 struct apmf_cnqf_power_set { 507 u32 pfloor; 508 u32 fppt; 509 u32 sppt; 510 u32 sppt_apu_only; 511 u32 spl; 512 u32 stt_min_limit; 513 u8 stt_skintemp[STT_TEMP_COUNT]; 514 u32 fan_id; 515 } __packed; 516 517 struct apmf_dyn_slider_output { 518 u16 size; 519 u16 flags; 520 u32 t_perf_to_turbo; 521 u32 t_balanced_to_perf; 522 u32 t_quiet_to_balanced; 523 u32 t_balanced_to_quiet; 524 u32 t_perf_to_balanced; 525 u32 t_turbo_to_perf; 526 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 527 } __packed; 528 529 /* Smart PC - TA internals */ 530 enum system_state { 531 SYSTEM_STATE_S0i3, 532 SYSTEM_STATE_S4, 533 SYSTEM_STATE_SCREEN_LOCK, 534 SYSTEM_STATE_MAX, 535 }; 536 537 enum ta_slider { 538 TA_BEST_BATTERY, 539 TA_BETTER_BATTERY, 540 TA_BETTER_PERFORMANCE, 541 TA_BEST_PERFORMANCE, 542 TA_MAX, 543 }; 544 545 /* Command ids for TA communication */ 546 enum ta_pmf_command { 547 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 548 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 549 }; 550 551 enum ta_pmf_error_type { 552 TA_PMF_TYPE_SUCCESS, 553 TA_PMF_ERROR_TYPE_GENERIC, 554 TA_PMF_ERROR_TYPE_CRYPTO, 555 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 556 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 557 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 558 TA_PMF_ERROR_TYPE_PB_CONVERT, 559 TA_PMF_ERROR_TYPE_PB_SETUP, 560 TA_PMF_ERROR_TYPE_PB_ENACT, 561 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 562 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 563 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 564 TA_PMF_ERROR_TYPE_MAX, 565 }; 566 567 struct pmf_action_table { 568 enum system_state system_state; 569 u32 spl; /* in mW */ 570 u32 sppt; /* in mW */ 571 u32 sppt_apuonly; /* in mW */ 572 u32 fppt; /* in mW */ 573 u32 stt_minlimit; /* in mW */ 574 u32 stt_skintemp_apu; /* in C */ 575 u32 stt_skintemp_hs2; /* in C */ 576 u32 p3t_limit; /* in mW */ 577 }; 578 579 /* Input conditions */ 580 struct ta_pmf_condition_info { 581 u32 power_source; 582 u32 bat_percentage; 583 u32 power_slider; 584 u32 lid_state; 585 bool user_present; 586 u32 rsvd1[2]; 587 u32 monitor_count; 588 u32 rsvd2[2]; 589 u32 bat_design; 590 u32 full_charge_capacity; 591 int drain_rate; 592 bool user_engaged; 593 u32 device_state; 594 u32 socket_power; 595 u32 skin_temperature; 596 u32 rsvd3[5]; 597 u32 ambient_light; 598 u32 length; 599 u32 avg_c0residency; 600 u32 max_c0residency; 601 u32 s0i3_entry; 602 u32 gfx_busy; 603 u32 rsvd4[7]; 604 bool camera_state; 605 u32 workload_type; 606 u32 display_type; 607 u32 display_state; 608 u32 rsvd5[150]; 609 }; 610 611 struct ta_pmf_load_policy_table { 612 u32 table_size; 613 u8 table[POLICY_BUF_MAX_SZ]; 614 }; 615 616 /* TA initialization params */ 617 struct ta_pmf_init_table { 618 u32 frequency; /* SMU sampling frequency */ 619 bool validate; 620 bool sku_check; 621 bool metadata_macrocheck; 622 struct ta_pmf_load_policy_table policies_table; 623 }; 624 625 /* Everything the TA needs to Enact Policies */ 626 struct ta_pmf_enact_table { 627 struct ta_pmf_condition_info ev_info; 628 u32 name; 629 }; 630 631 struct ta_pmf_action { 632 u32 action_index; 633 u32 value; 634 }; 635 636 /* Output actions from TA */ 637 struct ta_pmf_enact_result { 638 u32 actions_count; 639 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 640 u32 undo_count; 641 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 642 }; 643 644 union ta_pmf_input { 645 struct ta_pmf_enact_table enact_table; 646 struct ta_pmf_init_table init_table; 647 }; 648 649 union ta_pmf_output { 650 struct ta_pmf_enact_result policy_apply_table; 651 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 652 }; 653 654 struct ta_pmf_shared_memory { 655 int command_id; 656 int resp_id; 657 u32 pmf_result; 658 u32 if_version; 659 union ta_pmf_output pmf_output; 660 union ta_pmf_input pmf_input; 661 }; 662 663 /* Core Layer */ 664 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 665 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 666 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 667 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 668 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 669 int amd_pmf_get_power_source(void); 670 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 671 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 672 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 673 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 674 675 /* SPS Layer */ 676 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 677 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 678 struct amd_pmf_static_slider_granular *table); 679 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 680 void amd_pmf_deinit_sps(struct amd_pmf_dev *dev); 681 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 682 struct apmf_static_slider_granular_output *output); 683 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 684 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 685 const char *amd_pmf_source_as_str(unsigned int state); 686 687 const char *amd_pmf_source_as_str(unsigned int state); 688 689 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 690 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 691 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 692 struct apmf_static_slider_granular_output_v2 *data); 693 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 694 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 695 696 /* Auto Mode Layer */ 697 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 698 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 699 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 700 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 701 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 702 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 703 704 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 705 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 706 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 707 708 /* CnQF Layer */ 709 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 710 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 711 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 712 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 713 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 714 extern const struct attribute_group cnqf_feature_attribute_group; 715 716 /* Smart PC builder Layer */ 717 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 718 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 719 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 720 721 /* Smart PC - TA interfaces */ 722 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 723 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 724 725 /* Quirk infrastructure */ 726 void amd_pmf_quirks_init(struct amd_pmf_dev *dev); 727 728 #endif /* PMF_H */ 729