1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/input.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_profile.h> 18 19 #define POLICY_BUF_MAX_SZ 0x4b000 20 #define POLICY_SIGN_COOKIE 0x31535024 21 #define POLICY_COOKIE_OFFSET 0x10 22 23 /* List of supported CPU ids */ 24 #define AMD_CPU_ID_RMB 0x14b5 25 #define AMD_CPU_ID_PS 0x14e8 26 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 27 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 28 29 struct cookie_header { 30 u32 sign; 31 u32 length; 32 } __packed; 33 34 /* APMF Functions */ 35 #define APMF_FUNC_VERIFY_INTERFACE 0 36 #define APMF_FUNC_GET_SYS_PARAMS 1 37 #define APMF_FUNC_SBIOS_REQUESTS 2 38 #define APMF_FUNC_SBIOS_HEARTBEAT 4 39 #define APMF_FUNC_AUTO_MODE 5 40 #define APMF_FUNC_SET_FAN_IDX 7 41 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 42 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 43 #define APMF_FUNC_DYN_SLIDER_AC 11 44 #define APMF_FUNC_DYN_SLIDER_DC 12 45 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 46 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 47 48 /* Message Definitions */ 49 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 50 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 51 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 52 #define GET_SPL 0x0B 53 #define GET_SPPT 0x0D 54 #define GET_FPPT 0x0F 55 #define SET_DRAM_ADDR_HIGH 0x14 56 #define SET_DRAM_ADDR_LOW 0x15 57 #define SET_TRANSFER_TABLE 0x16 58 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 59 #define SET_STT_LIMIT_APU 0x19 60 #define SET_STT_LIMIT_HS2 0x1A 61 #define SET_SPPT_APU_ONLY 0x1D 62 #define GET_SPPT_APU_ONLY 0x1E 63 #define GET_STT_MIN_LIMIT 0x1F 64 #define GET_STT_LIMIT_APU 0x20 65 #define GET_STT_LIMIT_HS2 0x21 66 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 67 #define SET_PMF_PPT 0x25 68 #define SET_PMF_PPT_APU_ONLY 0x26 69 70 /* OS slider update notification */ 71 #define DC_BEST_PERF 0 72 #define DC_BETTER_PERF 1 73 #define DC_BATTERY_SAVER 3 74 #define AC_BEST_PERF 4 75 #define AC_BETTER_PERF 5 76 #define AC_BETTER_BATTERY 6 77 78 /* Fan Index for Auto Mode */ 79 #define FAN_INDEX_AUTO 0xFFFFFFFF 80 81 #define ARG_NONE 0 82 #define AVG_SAMPLE_SIZE 3 83 84 /* Policy Actions */ 85 #define PMF_POLICY_SPL 2 86 #define PMF_POLICY_SPPT 3 87 #define PMF_POLICY_FPPT 4 88 #define PMF_POLICY_SPPT_APU_ONLY 5 89 #define PMF_POLICY_STT_MIN 6 90 #define PMF_POLICY_STT_SKINTEMP_APU 7 91 #define PMF_POLICY_STT_SKINTEMP_HS2 8 92 #define PMF_POLICY_SYSTEM_STATE 9 93 #define PMF_POLICY_BIOS_OUTPUT_1 10 94 #define PMF_POLICY_BIOS_OUTPUT_2 11 95 #define PMF_POLICY_P3T 38 96 #define PMF_POLICY_PMF_PPT 54 97 #define PMF_POLICY_PMF_PPT_APU_ONLY 55 98 #define PMF_POLICY_BIOS_OUTPUT_3 57 99 #define PMF_POLICY_BIOS_OUTPUT_4 58 100 #define PMF_POLICY_BIOS_OUTPUT_5 59 101 #define PMF_POLICY_BIOS_OUTPUT_6 60 102 #define PMF_POLICY_BIOS_OUTPUT_7 61 103 #define PMF_POLICY_BIOS_OUTPUT_8 62 104 #define PMF_POLICY_BIOS_OUTPUT_9 63 105 #define PMF_POLICY_BIOS_OUTPUT_10 64 106 107 /* TA macros */ 108 #define PMF_TA_IF_VERSION_MAJOR 1 109 #define TA_PMF_ACTION_MAX 32 110 #define TA_PMF_UNDO_MAX 8 111 #define TA_OUTPUT_RESERVED_MEM 922 112 #define MAX_OPERATION_PARAMS 4 113 114 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 115 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 116 117 #define PMF_IF_V1 1 118 #define PMF_IF_V2 2 119 120 #define APTS_MAX_STATES 16 121 #define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7) 122 123 typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data); 124 125 /* APTS PMF BIOS Interface */ 126 struct amd_pmf_apts_output { 127 u16 table_version; 128 u32 fan_table_idx; 129 u32 pmf_ppt; 130 u32 ppt_pmf_apu_only; 131 u32 stt_min_limit; 132 u8 stt_skin_temp_limit_apu; 133 u8 stt_skin_temp_limit_hs2; 134 } __packed; 135 136 struct amd_pmf_apts_granular_output { 137 u16 size; 138 struct amd_pmf_apts_output val; 139 } __packed; 140 141 struct amd_pmf_apts_granular { 142 u16 size; 143 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 144 }; 145 146 struct sbios_hb_event_v2 { 147 u16 size; 148 u8 load; 149 u8 unload; 150 u8 suspend; 151 u8 resume; 152 } __packed; 153 154 enum sbios_hb_v2 { 155 ON_LOAD, 156 ON_UNLOAD, 157 ON_SUSPEND, 158 ON_RESUME, 159 }; 160 161 /* AMD PMF BIOS interfaces */ 162 struct apmf_verify_interface { 163 u16 size; 164 u16 version; 165 u32 notification_mask; 166 u32 supported_functions; 167 } __packed; 168 169 struct apmf_system_params { 170 u16 size; 171 u32 valid_mask; 172 u32 flags; 173 u8 command_code; 174 u32 heartbeat_int; 175 } __packed; 176 177 struct apmf_sbios_req { 178 u16 size; 179 u32 pending_req; 180 u8 rsd; 181 u8 cql_event; 182 u8 amt_event; 183 u32 fppt; 184 u32 sppt; 185 u32 fppt_apu_only; 186 u32 spl; 187 u32 stt_min_limit; 188 u8 skin_temp_apu; 189 u8 skin_temp_hs2; 190 } __packed; 191 192 /* As per APMF spec 1.3 */ 193 struct apmf_sbios_req_v1 { 194 u16 size; 195 u32 pending_req; 196 u8 rsvd; 197 u8 cql_event; 198 u8 amt_event; 199 u32 fppt; 200 u32 sppt; 201 u32 sppt_apu_only; 202 u32 spl; 203 u32 stt_min_limit; 204 u8 skin_temp_apu; 205 u8 skin_temp_hs2; 206 u8 enable_cnqf; 207 u32 custom_policy[10]; 208 } __packed; 209 210 struct apmf_sbios_req_v2 { 211 u16 size; 212 u32 pending_req; 213 u8 rsd; 214 u32 ppt_pmf; 215 u32 ppt_pmf_apu_only; 216 u32 stt_min_limit; 217 u8 skin_temp_apu; 218 u8 skin_temp_hs2; 219 u32 custom_policy[10]; 220 } __packed; 221 222 struct apmf_fan_idx { 223 u16 size; 224 u8 fan_ctl_mode; 225 u32 fan_ctl_idx; 226 } __packed; 227 228 struct smu_pmf_metrics_v2 { 229 u16 core_frequency[16]; /* MHz */ 230 u16 core_power[16]; /* mW */ 231 u16 core_temp[16]; /* centi-C */ 232 u16 gfx_temp; /* centi-C */ 233 u16 soc_temp; /* centi-C */ 234 u16 stapm_opn_limit; /* mW */ 235 u16 stapm_cur_limit; /* mW */ 236 u16 infra_cpu_maxfreq; /* MHz */ 237 u16 infra_gfx_maxfreq; /* MHz */ 238 u16 skin_temp; /* centi-C */ 239 u16 gfxclk_freq; /* MHz */ 240 u16 fclk_freq; /* MHz */ 241 u16 gfx_activity; /* GFX busy % [0-100] */ 242 u16 socclk_freq; /* MHz */ 243 u16 vclk_freq; /* MHz */ 244 u16 vcn_activity; /* VCN busy % [0-100] */ 245 u16 vpeclk_freq; /* MHz */ 246 u16 ipuclk_freq; /* MHz */ 247 u16 ipu_busy[8]; /* NPU busy % [0-100] */ 248 u16 dram_reads; /* MB/sec */ 249 u16 dram_writes; /* MB/sec */ 250 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 251 u16 ipu_power; /* mW */ 252 u32 apu_power; /* mW */ 253 u32 gfx_power; /* mW */ 254 u32 dgpu_power; /* mW */ 255 u32 socket_power; /* mW */ 256 u32 all_core_power; /* mW */ 257 u32 filter_alpha_value; /* time constant [us] */ 258 u32 metrics_counter; 259 u16 memclk_freq; /* MHz */ 260 u16 mpipuclk_freq; /* MHz */ 261 u16 ipu_reads; /* MB/sec */ 262 u16 ipu_writes; /* MB/sec */ 263 u32 throttle_residency_prochot; 264 u32 throttle_residency_spl; 265 u32 throttle_residency_fppt; 266 u32 throttle_residency_sppt; 267 u32 throttle_residency_thm_core; 268 u32 throttle_residency_thm_gfx; 269 u32 throttle_residency_thm_soc; 270 u16 psys; 271 u16 spare1; 272 u32 spare[6]; 273 } __packed; 274 275 struct smu_pmf_metrics { 276 u16 gfxclk_freq; /* in MHz */ 277 u16 socclk_freq; /* in MHz */ 278 u16 vclk_freq; /* in MHz */ 279 u16 dclk_freq; /* in MHz */ 280 u16 memclk_freq; /* in MHz */ 281 u16 spare; 282 u16 gfx_activity; /* in Centi */ 283 u16 uvd_activity; /* in Centi */ 284 u16 voltage[2]; /* in mV */ 285 u16 currents[2]; /* in mA */ 286 u16 power[2];/* in mW */ 287 u16 core_freq[8]; /* in MHz */ 288 u16 core_power[8]; /* in mW */ 289 u16 core_temp[8]; /* in centi-Celsius */ 290 u16 l3_freq; /* in MHz */ 291 u16 l3_temp; /* in centi-Celsius */ 292 u16 gfx_temp; /* in centi-Celsius */ 293 u16 soc_temp; /* in centi-Celsius */ 294 u16 throttler_status; 295 u16 current_socketpower; /* in mW */ 296 u16 stapm_orig_limit; /* in W */ 297 u16 stapm_cur_limit; /* in W */ 298 u32 apu_power; /* in mW */ 299 u32 dgpu_power; /* in mW */ 300 u16 vdd_tdc_val; /* in mA */ 301 u16 soc_tdc_val; /* in mA */ 302 u16 vdd_edc_val; /* in mA */ 303 u16 soc_edcv_al; /* in mA */ 304 u16 infra_cpu_maxfreq; /* in MHz */ 305 u16 infra_gfx_maxfreq; /* in MHz */ 306 u16 skin_temp; /* in centi-Celsius */ 307 u16 device_state; 308 u16 curtemp; /* in centi-Celsius */ 309 u16 filter_alpha_value; 310 u16 avg_gfx_clkfrequency; 311 u16 avg_fclk_frequency; 312 u16 avg_gfx_activity; 313 u16 avg_socclk_frequency; 314 u16 avg_vclk_frequency; 315 u16 avg_vcn_activity; 316 u16 avg_dram_reads; 317 u16 avg_dram_writes; 318 u16 avg_socket_power; 319 u16 avg_core_power[2]; 320 u16 avg_core_c0residency[16]; 321 u16 spare1; 322 u32 metrics_counter; 323 } __packed; 324 325 enum amd_stt_skin_temp { 326 STT_TEMP_APU, 327 STT_TEMP_HS2, 328 STT_TEMP_COUNT, 329 }; 330 331 enum amd_slider_op { 332 SLIDER_OP_GET, 333 SLIDER_OP_SET, 334 }; 335 336 enum power_source { 337 POWER_SOURCE_AC, 338 POWER_SOURCE_DC, 339 POWER_SOURCE_MAX, 340 }; 341 342 enum power_modes { 343 POWER_MODE_PERFORMANCE, 344 POWER_MODE_BALANCED_POWER, 345 POWER_MODE_POWER_SAVER, 346 POWER_MODE_MAX, 347 }; 348 349 enum power_modes_v2 { 350 POWER_MODE_BEST_PERFORMANCE, 351 POWER_MODE_BALANCED, 352 POWER_MODE_BEST_POWER_EFFICIENCY, 353 POWER_MODE_ENERGY_SAVE, 354 POWER_MODE_V2_MAX, 355 }; 356 357 struct pmf_bios_inputs_prev { 358 u32 custom_bios_inputs[10]; 359 }; 360 361 struct amd_pmf_dev { 362 void __iomem *regbase; 363 void __iomem *smu_virt_addr; 364 void *buf; 365 u32 base_addr; 366 u32 cpu_id; 367 struct device *dev; 368 struct mutex lock; /* protects the PMF interface */ 369 u32 supported_func; 370 enum platform_profile_option current_profile; 371 struct device *ppdev; /* platform profile class device */ 372 struct dentry *dbgfs_dir; 373 int hb_interval; /* SBIOS heartbeat interval */ 374 struct delayed_work heart_beat; 375 struct smu_pmf_metrics m_table; 376 struct smu_pmf_metrics_v2 m_table_v2; 377 struct delayed_work work_buffer; 378 ktime_t start_time; 379 int socket_power_history[AVG_SAMPLE_SIZE]; 380 int socket_power_history_idx; 381 bool amt_enabled; 382 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 383 bool cnqf_enabled; 384 bool cnqf_supported; 385 struct notifier_block pwr_src_notifier; 386 /* Smart PC solution builder */ 387 struct dentry *esbin; 388 unsigned char *policy_buf; 389 resource_size_t policy_sz; 390 struct tee_context *tee_ctx; 391 struct tee_shm *fw_shm_pool; 392 u32 session_id; 393 void *shbuf; 394 struct delayed_work pb_work; 395 struct pmf_action_table *prev_data; 396 resource_size_t policy_addr; 397 void __iomem *policy_base; 398 bool smart_pc_enabled; 399 u16 pmf_if_version; 400 struct input_dev *pmf_idev; 401 size_t mtable_size; 402 struct resource *res; 403 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 404 struct mutex cb_mutex; 405 u32 notifications; 406 struct apmf_sbios_req_v1 req1; 407 struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */ 408 bool cb_flag; /* To handle first custom BIOS input */ 409 }; 410 411 struct apmf_sps_prop_granular_v2 { 412 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 413 } __packed; 414 415 struct apmf_sps_prop_granular { 416 u32 fppt; 417 u32 sppt; 418 u32 sppt_apu_only; 419 u32 spl; 420 u32 stt_min; 421 u8 stt_skin_temp[STT_TEMP_COUNT]; 422 u32 fan_id; 423 } __packed; 424 425 /* Static Slider */ 426 struct apmf_static_slider_granular_output { 427 u16 size; 428 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 429 } __packed; 430 431 struct amd_pmf_static_slider_granular { 432 u16 size; 433 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 434 }; 435 436 struct apmf_static_slider_granular_output_v2 { 437 u16 size; 438 struct apmf_sps_prop_granular_v2 sps_idx; 439 } __packed; 440 441 struct amd_pmf_static_slider_granular_v2 { 442 u16 size; 443 struct apmf_sps_prop_granular_v2 sps_idx; 444 }; 445 446 struct os_power_slider { 447 u16 size; 448 u8 slider_event; 449 } __packed; 450 451 struct amd_pmf_notify_smart_pc_update { 452 u16 size; 453 u32 pending_req; 454 u32 custom_bios[10]; 455 } __packed; 456 457 struct fan_table_control { 458 bool manual; 459 unsigned long fan_id; 460 }; 461 462 struct power_table_control { 463 u32 spl; 464 u32 sppt; 465 u32 fppt; 466 u32 sppt_apu_only; 467 u32 stt_min; 468 u32 stt_skin_temp[STT_TEMP_COUNT]; 469 u32 reserved[16]; 470 }; 471 472 /* Auto Mode Layer */ 473 enum auto_mode_transition_priority { 474 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 475 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 476 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 477 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 478 AUTO_TRANSITION_MAX, 479 }; 480 481 enum auto_mode_mode { 482 AUTO_QUIET, 483 AUTO_BALANCE, 484 AUTO_PERFORMANCE_ON_LAP, 485 AUTO_PERFORMANCE, 486 AUTO_MODE_MAX, 487 }; 488 489 struct auto_mode_trans_params { 490 u32 time_constant; /* minimum time required to switch to next mode */ 491 u32 power_delta; /* delta power to shift mode */ 492 u32 power_threshold; 493 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 494 u32 applied; 495 enum auto_mode_mode target_mode; 496 u32 shifting_up; 497 }; 498 499 struct auto_mode_mode_settings { 500 struct power_table_control power_control; 501 struct fan_table_control fan_control; 502 u32 power_floor; 503 }; 504 505 struct auto_mode_mode_config { 506 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 507 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 508 enum auto_mode_mode current_mode; 509 }; 510 511 struct apmf_auto_mode { 512 u16 size; 513 /* time constant */ 514 u32 balanced_to_perf; 515 u32 perf_to_balanced; 516 u32 quiet_to_balanced; 517 u32 balanced_to_quiet; 518 /* power floor */ 519 u32 pfloor_perf; 520 u32 pfloor_balanced; 521 u32 pfloor_quiet; 522 /* Power delta for mode change */ 523 u32 pd_balanced_to_perf; 524 u32 pd_perf_to_balanced; 525 u32 pd_quiet_to_balanced; 526 u32 pd_balanced_to_quiet; 527 /* skin temperature limits */ 528 u8 stt_apu_perf_on_lap; /* CQL ON */ 529 u8 stt_hs2_perf_on_lap; /* CQL ON */ 530 u8 stt_apu_perf; 531 u8 stt_hs2_perf; 532 u8 stt_apu_balanced; 533 u8 stt_hs2_balanced; 534 u8 stt_apu_quiet; 535 u8 stt_hs2_quiet; 536 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 537 u32 stt_min_limit_perf; 538 u32 stt_min_limit_balanced; 539 u32 stt_min_limit_quiet; 540 /* SPL based */ 541 u32 fppt_perf_on_lap; /* CQL ON */ 542 u32 sppt_perf_on_lap; /* CQL ON */ 543 u32 spl_perf_on_lap; /* CQL ON */ 544 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 545 u32 fppt_perf; 546 u32 sppt_perf; 547 u32 spl_perf; 548 u32 sppt_apu_only_perf; 549 u32 fppt_balanced; 550 u32 sppt_balanced; 551 u32 spl_balanced; 552 u32 sppt_apu_only_balanced; 553 u32 fppt_quiet; 554 u32 sppt_quiet; 555 u32 spl_quiet; 556 u32 sppt_apu_only_quiet; 557 /* Fan ID */ 558 u32 fan_id_perf; 559 u32 fan_id_balanced; 560 u32 fan_id_quiet; 561 } __packed; 562 563 /* CnQF Layer */ 564 enum cnqf_trans_priority { 565 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 566 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 567 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 568 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 569 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 570 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 571 CNQF_TRANSITION_MAX, 572 }; 573 574 enum cnqf_mode { 575 CNQF_MODE_QUIET, 576 CNQF_MODE_BALANCE, 577 CNQF_MODE_PERFORMANCE, 578 CNQF_MODE_TURBO, 579 CNQF_MODE_MAX, 580 }; 581 582 enum apmf_cnqf_pos { 583 APMF_CNQF_TURBO, 584 APMF_CNQF_PERFORMANCE, 585 APMF_CNQF_BALANCE, 586 APMF_CNQF_QUIET, 587 APMF_CNQF_MAX, 588 }; 589 590 struct cnqf_mode_settings { 591 struct power_table_control power_control; 592 struct fan_table_control fan_control; 593 u32 power_floor; 594 }; 595 596 struct cnqf_tran_params { 597 u32 time_constant; /* minimum time required to switch to next mode */ 598 u32 power_threshold; 599 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 600 u32 total_power; 601 u32 count; 602 bool priority; 603 bool shifting_up; 604 enum cnqf_mode target_mode; 605 }; 606 607 struct cnqf_config { 608 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 609 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 610 struct power_table_control defaults; 611 enum cnqf_mode current_mode; 612 u32 power_src; 613 u32 avg_power; 614 }; 615 616 struct apmf_cnqf_power_set { 617 u32 pfloor; 618 u32 fppt; 619 u32 sppt; 620 u32 sppt_apu_only; 621 u32 spl; 622 u32 stt_min_limit; 623 u8 stt_skintemp[STT_TEMP_COUNT]; 624 u32 fan_id; 625 } __packed; 626 627 struct apmf_dyn_slider_output { 628 u16 size; 629 u16 flags; 630 u32 t_perf_to_turbo; 631 u32 t_balanced_to_perf; 632 u32 t_quiet_to_balanced; 633 u32 t_balanced_to_quiet; 634 u32 t_perf_to_balanced; 635 u32 t_turbo_to_perf; 636 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 637 } __packed; 638 639 /* Smart PC - TA internals */ 640 enum system_state { 641 SYSTEM_STATE_S0i3, 642 SYSTEM_STATE_S4, 643 SYSTEM_STATE_SCREEN_LOCK, 644 SYSTEM_STATE_MAX, 645 }; 646 647 enum ta_slider { 648 TA_BEST_BATTERY, 649 TA_BETTER_BATTERY, 650 TA_BETTER_PERFORMANCE, 651 TA_BEST_PERFORMANCE, 652 TA_MAX, 653 }; 654 655 struct amd_pmf_pb_bitmap { 656 const char *name; 657 u32 bit_mask; 658 }; 659 660 static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = { 661 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(5)}, 662 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(6)}, 663 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(7)}, 664 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(8)}, 665 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(9)}, 666 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(10)}, 667 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(11)}, 668 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(12)}, 669 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(13)}, 670 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(14)}, 671 }; 672 673 static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = { 674 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(7)}, 675 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(8)}, 676 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(9)}, 677 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(10)}, 678 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(11)}, 679 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(12)}, 680 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(13)}, 681 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(14)}, 682 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(15)}, 683 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(16)}, 684 }; 685 686 enum platform_type { 687 PTYPE_UNKNOWN = 0, 688 LID_CLOSE, 689 CLAMSHELL, 690 FLAT, 691 TENT, 692 STAND, 693 TABLET, 694 BOOK, 695 PRESENTATION, 696 PULL_FWD, 697 PTYPE_INVALID = 0xf, 698 }; 699 700 /* Command ids for TA communication */ 701 enum ta_pmf_command { 702 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 703 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 704 }; 705 706 enum ta_pmf_error_type { 707 TA_PMF_TYPE_SUCCESS, 708 TA_PMF_ERROR_TYPE_GENERIC, 709 TA_PMF_ERROR_TYPE_CRYPTO, 710 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 711 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 712 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 713 TA_PMF_ERROR_TYPE_PB_CONVERT, 714 TA_PMF_ERROR_TYPE_PB_SETUP, 715 TA_PMF_ERROR_TYPE_PB_ENACT, 716 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 717 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 718 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 719 TA_PMF_ERROR_TYPE_MAX, 720 }; 721 722 struct pmf_action_table { 723 enum system_state system_state; 724 u32 spl; /* in mW */ 725 u32 sppt; /* in mW */ 726 u32 sppt_apuonly; /* in mW */ 727 u32 fppt; /* in mW */ 728 u32 stt_minlimit; /* in mW */ 729 u32 stt_skintemp_apu; /* in C */ 730 u32 stt_skintemp_hs2; /* in C */ 731 u32 p3t_limit; /* in mW */ 732 u32 pmf_ppt; /* in mW */ 733 u32 pmf_ppt_apu_only; /* in mW */ 734 }; 735 736 /* Input conditions */ 737 struct ta_pmf_condition_info { 738 u32 power_source; 739 u32 bat_percentage; 740 u32 power_slider; 741 u32 lid_state; 742 bool user_present; 743 u32 bios_input_1[2]; 744 u32 monitor_count; 745 u32 rsvd2[2]; 746 u32 bat_design; 747 u32 full_charge_capacity; 748 int drain_rate; 749 bool user_engaged; 750 u32 device_state; 751 u32 socket_power; 752 u32 skin_temperature; 753 u32 rsvd3[2]; 754 u32 platform_type; 755 u32 rsvd3_1[2]; 756 u32 ambient_light; 757 u32 length; 758 u32 avg_c0residency; 759 u32 max_c0residency; 760 u32 s0i3_entry; 761 u32 gfx_busy; 762 u32 rsvd4[7]; 763 bool camera_state; 764 u32 workload_type; 765 u32 display_type; 766 u32 display_state; 767 u32 rsvd5_1[17]; 768 u32 bios_input_2[8]; 769 u32 rsvd5[125]; 770 }; 771 772 struct ta_pmf_load_policy_table { 773 u32 table_size; 774 u8 table[POLICY_BUF_MAX_SZ]; 775 }; 776 777 /* TA initialization params */ 778 struct ta_pmf_init_table { 779 u32 frequency; /* SMU sampling frequency */ 780 bool validate; 781 bool sku_check; 782 bool metadata_macrocheck; 783 struct ta_pmf_load_policy_table policies_table; 784 }; 785 786 /* Everything the TA needs to Enact Policies */ 787 struct ta_pmf_enact_table { 788 struct ta_pmf_condition_info ev_info; 789 u32 name; 790 }; 791 792 struct ta_pmf_action { 793 u32 action_index; 794 u32 value; 795 u32 spl_arg; 796 }; 797 798 /* Output actions from TA */ 799 struct ta_pmf_enact_result { 800 u32 actions_count; 801 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 802 u32 undo_count; 803 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 804 }; 805 806 union ta_pmf_input { 807 struct ta_pmf_enact_table enact_table; 808 struct ta_pmf_init_table init_table; 809 }; 810 811 union ta_pmf_output { 812 struct ta_pmf_enact_result policy_apply_table; 813 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 814 }; 815 816 struct ta_pmf_shared_memory { 817 int command_id; 818 int resp_id; 819 u32 pmf_result; 820 u32 if_version; 821 union ta_pmf_output pmf_output; 822 union ta_pmf_input pmf_input; 823 }; 824 825 /* Core Layer */ 826 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 827 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 828 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 829 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 830 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 831 int amd_pmf_get_power_source(void); 832 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 833 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 834 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 835 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 836 u32 fixp_q88_fromint(u32 val); 837 int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev); 838 839 /* SPS Layer */ 840 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 841 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 842 struct amd_pmf_static_slider_granular *table); 843 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 844 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 845 struct apmf_static_slider_granular_output *output); 846 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 847 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 848 const char *amd_pmf_source_as_str(unsigned int state); 849 850 const char *amd_pmf_source_as_str(unsigned int state); 851 852 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 853 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 854 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 855 struct apmf_static_slider_granular_output_v2 *data); 856 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 857 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 858 859 /* Auto Mode Layer */ 860 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 861 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 862 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 863 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 864 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 865 int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v1 *req); 866 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 867 868 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 869 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 870 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 871 872 /* CnQF Layer */ 873 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 874 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 875 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 876 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 877 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 878 extern const struct attribute_group cnqf_feature_attribute_group; 879 880 /* Smart PC builder Layer */ 881 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 882 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 883 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 884 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 885 886 /* Smart PC - TA interfaces */ 887 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 888 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 889 int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev); 890 891 #endif /* PMF_H */ 892