1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/amd-pmf-io.h> 16 #include <linux/circ_buf.h> 17 #include <linux/compiler_attributes.h> 18 #include <linux/compiler_types.h> 19 #include <linux/input.h> 20 #include <linux/mutex_types.h> 21 #include <linux/platform_device.h> 22 #include <linux/platform_profile.h> 23 #include <linux/types.h> 24 25 #define POLICY_BUF_MAX_SZ 0x4b000 26 #define POLICY_SIGN_COOKIE 0x31535024 27 #define POLICY_COOKIE_OFFSET 0x10 28 29 /* List of supported CPU ids */ 30 #define AMD_CPU_ID_RMB 0x14b5 31 #define AMD_CPU_ID_PS 0x14e8 32 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 33 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 34 #define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b 35 36 /* Aliases required by PCI_DEVICE_DATA() macro naming convention */ 37 #define PCI_DEVICE_ID_AMD_CPU_ID_RMB AMD_CPU_ID_RMB 38 #define PCI_DEVICE_ID_AMD_CPU_ID_PS AMD_CPU_ID_PS 39 40 struct cookie_header { 41 u32 sign; 42 u32 length; 43 } __packed; 44 45 /* APMF Functions */ 46 #define APMF_FUNC_VERIFY_INTERFACE 0 47 #define APMF_FUNC_GET_SYS_PARAMS 1 48 #define APMF_FUNC_SBIOS_REQUESTS 2 49 #define APMF_FUNC_SBIOS_HEARTBEAT 4 50 #define APMF_FUNC_AUTO_MODE 5 51 #define APMF_FUNC_SET_FAN_IDX 7 52 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 53 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 54 #define APMF_FUNC_DYN_SLIDER_AC 11 55 #define APMF_FUNC_DYN_SLIDER_DC 12 56 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 57 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 58 59 /* Message Definitions */ 60 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 61 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 62 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 63 #define GET_SPL 0x0B 64 #define GET_SPPT 0x0D 65 #define GET_FPPT 0x0F 66 #define SET_DRAM_ADDR_HIGH 0x14 67 #define SET_DRAM_ADDR_LOW 0x15 68 #define SET_TRANSFER_TABLE 0x16 69 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 70 #define SET_STT_LIMIT_APU 0x19 71 #define SET_STT_LIMIT_HS2 0x1A 72 #define SET_SPPT_APU_ONLY 0x1D 73 #define GET_SPPT_APU_ONLY 0x1E 74 #define GET_STT_MIN_LIMIT 0x1F 75 #define GET_STT_LIMIT_APU 0x20 76 #define GET_STT_LIMIT_HS2 0x21 77 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 78 #define SET_PMF_PPT 0x25 79 #define SET_PMF_PPT_APU_ONLY 0x26 80 81 /* Message IDs for 1AH_M80H platform */ 82 #define GET_1AH_M80H_METRICS_TABLE_LOG_SAMPLE 0x0E 83 #define GET_1AH_M80H_METRICS_TABLE_DRAM_ADDR 0x0F 84 85 /* OS slider update notification */ 86 #define DC_BEST_PERF 0 87 #define DC_BETTER_PERF 1 88 #define DC_BATTERY_SAVER 3 89 #define AC_BEST_PERF 4 90 #define AC_BETTER_PERF 5 91 #define AC_BETTER_BATTERY 6 92 93 /* Fan Index for Auto Mode */ 94 #define FAN_INDEX_AUTO 0xFFFFFFFF 95 96 #define ARG_NONE 0 97 #define AVG_SAMPLE_SIZE 3 98 99 /* Policy Actions */ 100 #define PMF_POLICY_SPL 2 101 #define PMF_POLICY_SPPT 3 102 #define PMF_POLICY_FPPT 4 103 #define PMF_POLICY_SPPT_APU_ONLY 5 104 #define PMF_POLICY_STT_MIN 6 105 #define PMF_POLICY_STT_SKINTEMP_APU 7 106 #define PMF_POLICY_STT_SKINTEMP_HS2 8 107 #define PMF_POLICY_SYSTEM_STATE 9 108 #define PMF_POLICY_BIOS_OUTPUT_1 10 109 #define PMF_POLICY_BIOS_OUTPUT_2 11 110 #define PMF_POLICY_P3T 38 111 #define PMF_POLICY_PMF_PPT 54 112 #define PMF_POLICY_PMF_PPT_APU_ONLY 55 113 #define PMF_POLICY_BIOS_OUTPUT_3 57 114 #define PMF_POLICY_BIOS_OUTPUT_4 58 115 #define PMF_POLICY_BIOS_OUTPUT_5 59 116 #define PMF_POLICY_BIOS_OUTPUT_6 60 117 #define PMF_POLICY_BIOS_OUTPUT_7 61 118 #define PMF_POLICY_BIOS_OUTPUT_8 62 119 #define PMF_POLICY_BIOS_OUTPUT_9 63 120 #define PMF_POLICY_BIOS_OUTPUT_10 64 121 122 /* TA macros */ 123 #define PMF_TA_IF_VERSION_MAJOR 1 124 #define TA_PMF_ACTION_MAX 32 125 #define TA_PMF_UNDO_MAX 8 126 #define TA_OUTPUT_RESERVED_MEM 922 127 #define MAX_OPERATION_PARAMS 4 128 129 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 130 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 131 132 #define PMF_IF_V1 1 133 #define PMF_IF_V2 2 134 135 #define APTS_MAX_STATES 16 136 #define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7) 137 #define BIOS_INPUTS_MAX 10 138 #define CUSTOM_BIOS_INPUT_RING_ENTRIES 64 /* Must be power of two for CIRC_* macros */ 139 140 /* amd_pmf_send_cmd() set/get */ 141 #define SET_CMD false 142 #define GET_CMD true 143 144 #define METRICS_TABLE_ID 7 145 #define BIOS_OUTPUT_MAX 10 146 147 extern int metrics_table_loop_ms; 148 149 #define AMD_PMF_METRIC_CORE_TYPE_MAX 4 150 #define AMD_PMF_METRIC_CCX_MAX 4 151 #define AMD_PMF_NUM_CLK_DPM_LEVELS 8 152 #define AMD_PMF_NUM_MAX_CORES 12 153 154 typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data); 155 156 static const uuid_t amd_pmf_ta_uuid[] __used = { UUID_INIT(0xd9b39bf2, 0x66bd, 0x4154, 0xaf, 0xb8, 157 0x8a, 0xcc, 0x2b, 0x2b, 0x60, 0xd6), 158 UUID_INIT(0x6fd93b77, 0x3fb8, 0x524d, 0xb1, 0x2d, 159 0xc5, 0x29, 0xb1, 0x3d, 0x85, 0x43), 160 }; 161 162 /* APTS PMF BIOS Interface */ 163 struct amd_pmf_apts_output { 164 u16 table_version; 165 u32 fan_table_idx; 166 u32 pmf_ppt; 167 u32 ppt_pmf_apu_only; 168 u32 stt_min_limit; 169 u8 stt_skin_temp_limit_apu; 170 u8 stt_skin_temp_limit_hs2; 171 } __packed; 172 173 struct amd_pmf_apts_granular_output { 174 u16 size; 175 struct amd_pmf_apts_output val; 176 } __packed; 177 178 struct amd_pmf_apts_granular { 179 u16 size; 180 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 181 }; 182 183 struct sbios_hb_event_v2 { 184 u16 size; 185 u8 load; 186 u8 unload; 187 u8 suspend; 188 u8 resume; 189 } __packed; 190 191 enum sbios_hb_v2 { 192 ON_LOAD, 193 ON_UNLOAD, 194 ON_SUSPEND, 195 ON_RESUME, 196 }; 197 198 /* AMD PMF BIOS interfaces */ 199 struct apmf_verify_interface { 200 u16 size; 201 u16 version; 202 u32 notification_mask; 203 u32 supported_functions; 204 } __packed; 205 206 struct apmf_system_params { 207 u16 size; 208 u32 valid_mask; 209 u32 flags; 210 u8 command_code; 211 u32 heartbeat_int; 212 } __packed; 213 214 struct apmf_sbios_req { 215 u16 size; 216 u32 pending_req; 217 u8 rsd; 218 u8 cql_event; 219 u8 amt_event; 220 u32 fppt; 221 u32 sppt; 222 u32 fppt_apu_only; 223 u32 spl; 224 u32 stt_min_limit; 225 u8 skin_temp_apu; 226 u8 skin_temp_hs2; 227 } __packed; 228 229 /* As per APMF spec 1.3 */ 230 struct apmf_sbios_req_v1 { 231 u16 size; 232 u32 pending_req; 233 u8 rsvd; 234 u8 cql_event; 235 u8 amt_event; 236 u32 fppt; 237 u32 sppt; 238 u32 sppt_apu_only; 239 u32 spl; 240 u32 stt_min_limit; 241 u8 skin_temp_apu; 242 u8 skin_temp_hs2; 243 u8 enable_cnqf; 244 u32 custom_policy[BIOS_INPUTS_MAX]; 245 } __packed; 246 247 struct apmf_sbios_req_v2 { 248 u16 size; 249 u32 pending_req; 250 u8 rsd; 251 u32 ppt_pmf; 252 u32 ppt_pmf_apu_only; 253 u32 stt_min_limit; 254 u8 skin_temp_apu; 255 u8 skin_temp_hs2; 256 u32 custom_policy[BIOS_INPUTS_MAX]; 257 } __packed; 258 259 struct apmf_fan_idx { 260 u16 size; 261 u8 fan_ctl_mode; 262 u32 fan_ctl_idx; 263 } __packed; 264 265 struct amd_pmf_metrics_iod { 266 u32 counter_acc; 267 /* Set Voltage */ 268 u64 vddcr_set_voltage; 269 u64 vddcr_soc_set_voltage; 270 u64 vddcr_npu_set_voltage; 271 u64 vddcr_lp_set_voltage; 272 u64 vddcr_gfx_set_voltage; 273 u64 vdd_misc_set_voltage; 274 /* Telemetry Voltages */ 275 u64 vddcr_telemetry_voltage; 276 u64 vddcr_soc_telemetry_voltage; 277 u64 vddcr_npu_telemetry_voltage; 278 u64 vddcr_lp_telemetry_voltage; 279 u64 vddcr_gfx_telemetry_voltage; 280 u64 vdd_misc_telemetry_voltage; 281 /* Telemetry Powers */ 282 u64 vddcr_telemetry_power; 283 u64 vddcr_soc_telemetry_power; 284 u64 vddcr_npu_telemetry_power; 285 u64 vddcr_lp_telemetry_power; 286 u64 vddcr_gfx_telemetry_power; 287 u64 vdd_misc_telemetry_power; 288 /* Throttlers - Fast PPT */ 289 u32 fppt_fused_limit; 290 u32 fppt_max_irm_limit; 291 u32 fppt_max_pbo_limit; 292 u32 fppt_limit; 293 u64 fppt_value_acc; 294 u32 fppt_residency_acc; 295 /* Throttlers - Slow PPT */ 296 u32 sppt_fused_limit; 297 u32 sppt_max_irm_limit; 298 u32 sppt_max_pbo_limit; 299 u32 sppt_limit; 300 u64 sppt_value_acc; 301 u32 sppt_residency_acc; 302 /* Throttlers - STAPM */ 303 u32 spl_fused_limit; 304 u32 spl_max_irm_limit; 305 u32 spl_max_pbo_limit; 306 u32 spl_limit; 307 u64 spl_value_acc; 308 u32 spl_residency_acc; 309 /* Throttlers - TDC VDDCR */ 310 u32 tdc_vddcr_fused_limit; 311 u32 tdc_vddcr_max_irm_limit; 312 u32 tdc_vddcr_max_pbo_limit; 313 u32 tdc_vddcr_limit; 314 u64 tdc_vddcr_value_acc; 315 u32 tdc_vddcr_residency_acc; 316 /* Throttlers - TDC VDDCR_SOC */ 317 u32 tdc_vddcr_soc_fused_limit; 318 u32 tdc_vddcr_soc_max_irm_limit; 319 u32 tdc_vddcr_soc_max_pbo_limit; 320 u32 tdc_vddcr_soc_limit; 321 u64 tdc_vddcr_soc_value_acc; 322 u32 tdc_vddcr_soc_residency_acc; 323 /* Throttlers - TDC VDDCR_NPU */ 324 u32 tdc_vddcr_npu_fused_limit; 325 u32 tdc_vddcr_npu_max_irm_limit; 326 u32 tdc_vddcr_npu_max_pbo_limit; 327 u32 tdc_vddcr_npu_limit; 328 u64 tdc_vddcr_npu_value_acc; 329 u32 tdc_vddcr_npu_residency_acc; 330 /* Throttlers - TDC VDDCR_LP */ 331 u32 tdc_vddcr_lp_fused_limit; 332 u32 tdc_vddcr_lp_max_irm_limit; 333 u32 tdc_vddcr_lp_max_pbo_limit; 334 u32 tdc_vddcr_lp_limit; 335 u64 tdc_vddcr_lp_value_acc; 336 u32 tdc_vddcr_lp_residency_acc; 337 /* Throttlers - TDC VDDCR_GFX */ 338 u32 tdc_vddcr_gfx_fused_limit; 339 u32 tdc_vddcr_gfx_max_irm_limit; 340 u32 tdc_vddcr_gfx_max_pbo_limit; 341 u32 tdc_vddcr_gfx_limit; 342 u64 tdc_vddcr_gfx_value_acc; 343 u32 tdc_vddcr_gfx_residency_acc; 344 /* Throttlers - EDC VDDCR */ 345 u32 edc_vddcr_fused_limit; 346 u32 edc_vddcr_max_irm_limit; 347 u32 edc_vddcr_max_pbo_limit; 348 u32 edc_vddcr_limit; 349 /* Throttlers - Thermal */ 350 u32 thm_fused_limit; 351 u32 thm_limit; 352 u64 thm_value_acc; 353 u32 thm_residency_acc; 354 u32 prochot_residency_acc; 355 u64 gfx_temp_acc; 356 u64 soc_temp_acc; 357 u32 p3t_fused_limit; 358 u64 p3t_value_acc; 359 /* Power */ 360 u64 system_power_acc; 361 u64 apu_power_acc; 362 u64 dgpu_power_acc; 363 u64 npu_power_acc; 364 /* Frequencies */ 365 u64 fclk_freq_eff_acc; 366 u64 memclk_freq_eff_acc; 367 u64 lclk_freq_eff_acc; 368 u64 gfxclk_freq_eff_acc; 369 u64 socclk_freq_eff_acc; 370 u64 vclk_freq_eff_acc; 371 u64 vpeclk_freq_eff_acc; 372 u64 aieclk_freq_eff_acc; 373 u64 npuhclk_freq_eff_acc; 374 /* Bandwidth */ 375 u64 dram_read_bandwidth; 376 u64 dram_write_bandwidth; 377 /* Activity Monitors */ 378 u64 gfx_busy_acc; 379 u64 vcn_busy_acc; 380 u64 npu_busy_acc[3]; 381 /* STT Limits */ 382 u32 stt_min_limit; 383 u64 stt_apu_hotspot_temp_acc; 384 u64 stt_hs2_hotspot_temp_acc; 385 u32 stt_apu_temp_limit; 386 u64 stt_apu_skin_temp_acc; 387 /* Residencies */ 388 u64 cpuoff_residency_ccx0; 389 u64 cpuoff_residency_ccx1; 390 u64 cpuoff_residency_ccx2; 391 u64 cpuoff_residency_ccx3; 392 /* DF-pstates */ 393 u32 fclk_freq_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 394 u32 uclk_freq_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 395 u32 ddr_rate_table[AMD_PMF_NUM_CLK_DPM_LEVELS]; 396 u8 dfpstate_source[AMD_PMF_NUM_CLK_DPM_LEVELS]; 397 /* System */ 398 u8 gfx_disabled; 399 u8 spare2[3]; 400 u32 gfxclk_fmax; 401 u8 cclk_core_fuse_enable[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 402 u8 cclk_core_enabled[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 403 u32 cclk_fmax[AMD_PMF_METRIC_CORE_TYPE_MAX][AMD_PMF_NUM_MAX_CORES]; 404 /* Overclock Capable */ 405 u8 cpu_precise_and_direct_oc_capable; 406 u8 gfx_precise_and_direct_oc_capable; 407 u8 pbo_basic_oc_capable; 408 u8 pbo_advanced_oc_capable; 409 u8 pbo_nitro_oc_capable; 410 u8 memory_and_fabric_oc_capable; 411 u8 misc_oc_capable; 412 u8 extreme_cold_oc_capable; 413 u8 down_config_control_capable; 414 u8 spare0[3]; 415 /* Overclock Status */ 416 u32 fit_limit_scalar; 417 u8 ln2_enabled; 418 u8 cpu_precise_and_direct_oc_enabled; 419 u8 gfx_precise_and_direct_oc_enabled; 420 u8 spare1[2]; 421 /* Voltage Guardband in PSM count */ 422 s8 psm_guardband[5][5][3]; 423 s32 core_power_limit_offset; 424 u32 max_freq_offset[5]; 425 u64 npu_temp_acc; 426 u64 dfpstate_residency_acc[AMD_PMF_NUM_CLK_DPM_LEVELS]; 427 u32 cclk_fboost; 428 /* PMF */ 429 u32 pmf_fast_apu_ppt_limit; 430 u64 pmf_fast_apu_ppt_value_acc; 431 u32 pmf_fast_apu_ppt_residency_acc; 432 u32 pmf_slow_apu_ppt_limit; 433 u64 pmf_slow_apu_ppt_value_acc; 434 u32 pmf_slow_apu_ppt_residency_acc; 435 u32 pmf_fast_spm_limit; 436 u64 pmf_fast_spm_value_acc; 437 u32 pmf_fast_spm_residency_acc; 438 u32 pmf_slow_spm_limit; 439 u64 pmf_slow_spm_value_acc; 440 u32 pmf_slow_spm_residency_acc; 441 u32 spare3[5]; 442 } __packed __aligned(4); 443 444 struct amd_pmf_metrics_ccx { 445 u64 core_c0[AMD_PMF_NUM_MAX_CORES]; 446 u64 core_cc6[AMD_PMF_NUM_MAX_CORES]; 447 u64 core_freq[AMD_PMF_NUM_MAX_CORES]; 448 u64 core_freqeff[AMD_PMF_NUM_MAX_CORES]; 449 u64 core_temp[AMD_PMF_NUM_MAX_CORES]; 450 u64 core_power[AMD_PMF_NUM_MAX_CORES]; 451 } __packed __aligned(4); 452 453 struct amd_pmf_metrics_v3 { 454 struct amd_pmf_metrics_iod iod; 455 struct amd_pmf_metrics_ccx ccx[AMD_PMF_METRIC_CCX_MAX]; 456 } __packed __aligned(4); 457 458 struct smu_pmf_metrics_v2 { 459 u16 core_frequency[16]; /* MHz */ 460 u16 core_power[16]; /* mW */ 461 u16 core_temp[16]; /* centi-C */ 462 u16 gfx_temp; /* centi-C */ 463 u16 soc_temp; /* centi-C */ 464 u16 stapm_opn_limit; /* mW */ 465 u16 stapm_cur_limit; /* mW */ 466 u16 infra_cpu_maxfreq; /* MHz */ 467 u16 infra_gfx_maxfreq; /* MHz */ 468 u16 skin_temp; /* centi-C */ 469 u16 gfxclk_freq; /* MHz */ 470 u16 fclk_freq; /* MHz */ 471 u16 gfx_activity; /* GFX busy % [0-100] */ 472 u16 socclk_freq; /* MHz */ 473 u16 vclk_freq; /* MHz */ 474 u16 vcn_activity; /* VCN busy % [0-100] */ 475 u16 vpeclk_freq; /* MHz */ 476 u16 npuclk_freq; /* MHz */ 477 u16 npu_busy[8]; /* NPU busy % [0-100] */ 478 u16 dram_reads; /* MB/sec */ 479 u16 dram_writes; /* MB/sec */ 480 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 481 u16 npu_power; /* mW */ 482 u32 apu_power; /* mW */ 483 u32 gfx_power; /* mW */ 484 u32 dgpu_power; /* mW */ 485 u32 socket_power; /* mW */ 486 u32 all_core_power; /* mW */ 487 u32 filter_alpha_value; /* time constant [us] */ 488 u32 metrics_counter; 489 u16 memclk_freq; /* MHz */ 490 u16 mpnpuclk_freq; /* MHz */ 491 u16 npu_reads; /* MB/sec */ 492 u16 npu_writes; /* MB/sec */ 493 u32 throttle_residency_prochot; 494 u32 throttle_residency_spl; 495 u32 throttle_residency_fppt; 496 u32 throttle_residency_sppt; 497 u32 throttle_residency_thm_core; 498 u32 throttle_residency_thm_gfx; 499 u32 throttle_residency_thm_soc; 500 u16 psys; 501 u16 spare1; 502 u32 spare[6]; 503 } __packed; 504 505 struct smu_pmf_metrics { 506 u16 gfxclk_freq; /* in MHz */ 507 u16 socclk_freq; /* in MHz */ 508 u16 vclk_freq; /* in MHz */ 509 u16 dclk_freq; /* in MHz */ 510 u16 memclk_freq; /* in MHz */ 511 u16 spare; 512 u16 gfx_activity; /* in Centi */ 513 u16 uvd_activity; /* in Centi */ 514 u16 voltage[2]; /* in mV */ 515 u16 currents[2]; /* in mA */ 516 u16 power[2];/* in mW */ 517 u16 core_freq[8]; /* in MHz */ 518 u16 core_power[8]; /* in mW */ 519 u16 core_temp[8]; /* in centi-Celsius */ 520 u16 l3_freq; /* in MHz */ 521 u16 l3_temp; /* in centi-Celsius */ 522 u16 gfx_temp; /* in centi-Celsius */ 523 u16 soc_temp; /* in centi-Celsius */ 524 u16 throttler_status; 525 u16 current_socketpower; /* in mW */ 526 u16 stapm_orig_limit; /* in W */ 527 u16 stapm_cur_limit; /* in W */ 528 u32 apu_power; /* in mW */ 529 u32 dgpu_power; /* in mW */ 530 u16 vdd_tdc_val; /* in mA */ 531 u16 soc_tdc_val; /* in mA */ 532 u16 vdd_edc_val; /* in mA */ 533 u16 soc_edcv_al; /* in mA */ 534 u16 infra_cpu_maxfreq; /* in MHz */ 535 u16 infra_gfx_maxfreq; /* in MHz */ 536 u16 skin_temp; /* in centi-Celsius */ 537 u16 device_state; 538 u16 curtemp; /* in centi-Celsius */ 539 u16 filter_alpha_value; 540 u16 avg_gfx_clkfrequency; 541 u16 avg_fclk_frequency; 542 u16 avg_gfx_activity; 543 u16 avg_socclk_frequency; 544 u16 avg_vclk_frequency; 545 u16 avg_vcn_activity; 546 u16 avg_dram_reads; 547 u16 avg_dram_writes; 548 u16 avg_socket_power; 549 u16 avg_core_power[2]; 550 u16 avg_core_c0residency[16]; 551 u16 spare1; 552 u32 metrics_counter; 553 } __packed; 554 555 enum amd_stt_skin_temp { 556 STT_TEMP_APU, 557 STT_TEMP_HS2, 558 STT_TEMP_COUNT, 559 }; 560 561 enum amd_slider_op { 562 SLIDER_OP_GET, 563 SLIDER_OP_SET, 564 }; 565 566 enum power_source { 567 POWER_SOURCE_AC, 568 POWER_SOURCE_DC, 569 POWER_SOURCE_MAX, 570 }; 571 572 enum power_modes { 573 POWER_MODE_PERFORMANCE, 574 POWER_MODE_BALANCED_POWER, 575 POWER_MODE_POWER_SAVER, 576 POWER_MODE_MAX, 577 }; 578 579 enum power_modes_v2 { 580 POWER_MODE_BEST_PERFORMANCE, 581 POWER_MODE_BALANCED, 582 POWER_MODE_BEST_POWER_EFFICIENCY, 583 POWER_MODE_ENERGY_SAVE, 584 POWER_MODE_V2_MAX, 585 }; 586 587 struct pmf_bios_inputs_prev { 588 u32 custom_bios_inputs[BIOS_INPUTS_MAX]; 589 }; 590 591 /** 592 * struct pmf_bios_input_entry - Snapshot of custom BIOS input event 593 * @val: Array of custom BIOS input values 594 * @preq: Pending request value associated with this event 595 */ 596 struct pmf_bios_input_entry { 597 u32 val[BIOS_INPUTS_MAX]; 598 u32 preq; 599 }; 600 601 struct pmf_cbi_ring_buffer { 602 struct pmf_bios_input_entry data[CUSTOM_BIOS_INPUT_RING_ENTRIES]; 603 int head; 604 int tail; 605 }; 606 607 /* SoC-specific SMU mailbox register offsets */ 608 struct amd_pmf_smu_regs { 609 u32 msg_reg; 610 u32 resp_reg; 611 u32 arg_reg[3]; 612 }; 613 614 struct amd_pmf_arg_data { 615 u32 lo; 616 u32 hi; 617 u32 size; 618 }; 619 620 struct amd_pmf_dev { 621 void __iomem *regbase; 622 void __iomem *smu_virt_addr; 623 void *buf; 624 u32 base_addr; 625 u32 cpu_id; 626 struct device *dev; 627 struct mutex lock; /* protects the PMF interface */ 628 u32 supported_func; 629 enum platform_profile_option current_profile; 630 struct device *ppdev; /* platform profile class device */ 631 struct dentry *dbgfs_dir; 632 int hb_interval; /* SBIOS heartbeat interval */ 633 struct delayed_work heart_beat; 634 struct smu_pmf_metrics m_table; 635 struct smu_pmf_metrics_v2 m_table_v2; 636 struct delayed_work work_buffer; 637 ktime_t start_time; 638 int socket_power_history[AVG_SAMPLE_SIZE]; 639 int socket_power_history_idx; 640 bool amt_enabled; 641 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 642 bool cnqf_enabled; 643 bool cnqf_supported; 644 struct notifier_block pwr_src_notifier; 645 /* Smart PC solution builder */ 646 struct dentry *esbin; 647 unsigned char *policy_buf; 648 resource_size_t policy_sz; 649 struct tee_context *tee_ctx; 650 struct tee_shm *fw_shm_pool; 651 u32 session_id; 652 void *shbuf; 653 struct delayed_work pb_work; 654 struct pmf_action_table *prev_data; 655 resource_size_t policy_addr; 656 void __iomem *policy_base; 657 bool smart_pc_enabled; 658 u16 pmf_if_version; 659 struct input_dev *pmf_idev; 660 size_t mtable_size; 661 struct resource *res; 662 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 663 struct mutex cb_mutex; 664 u32 notifications; 665 struct apmf_sbios_req_v1 req1; 666 struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */ 667 bool cb_flag; /* To handle first custom BIOS input */ 668 struct pmf_cbi_ring_buffer cbi_buf; 669 struct mutex cbi_mutex; /* Protects ring buffer access */ 670 struct mutex metrics_mutex; 671 u32 bios_output[BIOS_OUTPUT_MAX]; 672 const struct amd_pmf_smu_regs *smu_regs; 673 void __iomem *metrics_table_virt; /* Mapped DRAM virtual address for metrics table */ 674 phys_addr_t metrics_table_phys; /* DRAM physical address for metrics table */ 675 struct amd_pmf_metrics_v3 mtable_v3; /* IOD and CCX */ 676 struct amd_pmf_arg_data dram_addr; 677 struct amd_pmf_metrics_v3 prev_metrics; /* Previous metrics for delta calculation */ 678 bool npu_metrics_have_prev; 679 }; 680 681 struct apmf_sps_prop_granular_v2 { 682 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 683 } __packed; 684 685 struct apmf_sps_prop_granular { 686 u32 fppt; 687 u32 sppt; 688 u32 sppt_apu_only; 689 u32 spl; 690 u32 stt_min; 691 u8 stt_skin_temp[STT_TEMP_COUNT]; 692 u32 fan_id; 693 } __packed; 694 695 /* Static Slider */ 696 struct apmf_static_slider_granular_output { 697 u16 size; 698 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 699 } __packed; 700 701 struct amd_pmf_static_slider_granular { 702 u16 size; 703 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 704 }; 705 706 struct apmf_static_slider_granular_output_v2 { 707 u16 size; 708 struct apmf_sps_prop_granular_v2 sps_idx; 709 } __packed; 710 711 struct amd_pmf_static_slider_granular_v2 { 712 u16 size; 713 struct apmf_sps_prop_granular_v2 sps_idx; 714 }; 715 716 struct os_power_slider { 717 u16 size; 718 u8 slider_event; 719 } __packed; 720 721 struct amd_pmf_notify_smart_pc_update { 722 u16 size; 723 u32 pending_req; 724 u32 custom_bios[BIOS_INPUTS_MAX]; 725 } __packed; 726 727 struct fan_table_control { 728 bool manual; 729 unsigned long fan_id; 730 }; 731 732 struct power_table_control { 733 u32 spl; 734 u32 sppt; 735 u32 fppt; 736 u32 sppt_apu_only; 737 u32 stt_min; 738 u32 stt_skin_temp[STT_TEMP_COUNT]; 739 u32 reserved[16]; 740 }; 741 742 /* Auto Mode Layer */ 743 enum auto_mode_transition_priority { 744 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 745 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 746 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 747 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 748 AUTO_TRANSITION_MAX, 749 }; 750 751 enum auto_mode_mode { 752 AUTO_QUIET, 753 AUTO_BALANCE, 754 AUTO_PERFORMANCE_ON_LAP, 755 AUTO_PERFORMANCE, 756 AUTO_MODE_MAX, 757 }; 758 759 struct auto_mode_trans_params { 760 u32 time_constant; /* minimum time required to switch to next mode */ 761 u32 power_delta; /* delta power to shift mode */ 762 u32 power_threshold; 763 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 764 u32 applied; 765 enum auto_mode_mode target_mode; 766 u32 shifting_up; 767 }; 768 769 struct auto_mode_mode_settings { 770 struct power_table_control power_control; 771 struct fan_table_control fan_control; 772 u32 power_floor; 773 }; 774 775 struct auto_mode_mode_config { 776 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 777 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 778 enum auto_mode_mode current_mode; 779 }; 780 781 struct apmf_auto_mode { 782 u16 size; 783 /* time constant */ 784 u32 balanced_to_perf; 785 u32 perf_to_balanced; 786 u32 quiet_to_balanced; 787 u32 balanced_to_quiet; 788 /* power floor */ 789 u32 pfloor_perf; 790 u32 pfloor_balanced; 791 u32 pfloor_quiet; 792 /* Power delta for mode change */ 793 u32 pd_balanced_to_perf; 794 u32 pd_perf_to_balanced; 795 u32 pd_quiet_to_balanced; 796 u32 pd_balanced_to_quiet; 797 /* skin temperature limits */ 798 u8 stt_apu_perf_on_lap; /* CQL ON */ 799 u8 stt_hs2_perf_on_lap; /* CQL ON */ 800 u8 stt_apu_perf; 801 u8 stt_hs2_perf; 802 u8 stt_apu_balanced; 803 u8 stt_hs2_balanced; 804 u8 stt_apu_quiet; 805 u8 stt_hs2_quiet; 806 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 807 u32 stt_min_limit_perf; 808 u32 stt_min_limit_balanced; 809 u32 stt_min_limit_quiet; 810 /* SPL based */ 811 u32 fppt_perf_on_lap; /* CQL ON */ 812 u32 sppt_perf_on_lap; /* CQL ON */ 813 u32 spl_perf_on_lap; /* CQL ON */ 814 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 815 u32 fppt_perf; 816 u32 sppt_perf; 817 u32 spl_perf; 818 u32 sppt_apu_only_perf; 819 u32 fppt_balanced; 820 u32 sppt_balanced; 821 u32 spl_balanced; 822 u32 sppt_apu_only_balanced; 823 u32 fppt_quiet; 824 u32 sppt_quiet; 825 u32 spl_quiet; 826 u32 sppt_apu_only_quiet; 827 /* Fan ID */ 828 u32 fan_id_perf; 829 u32 fan_id_balanced; 830 u32 fan_id_quiet; 831 } __packed; 832 833 /* CnQF Layer */ 834 enum cnqf_trans_priority { 835 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 836 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 837 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 838 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 839 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 840 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 841 CNQF_TRANSITION_MAX, 842 }; 843 844 enum cnqf_mode { 845 CNQF_MODE_QUIET, 846 CNQF_MODE_BALANCE, 847 CNQF_MODE_PERFORMANCE, 848 CNQF_MODE_TURBO, 849 CNQF_MODE_MAX, 850 }; 851 852 enum apmf_cnqf_pos { 853 APMF_CNQF_TURBO, 854 APMF_CNQF_PERFORMANCE, 855 APMF_CNQF_BALANCE, 856 APMF_CNQF_QUIET, 857 APMF_CNQF_MAX, 858 }; 859 860 struct cnqf_mode_settings { 861 struct power_table_control power_control; 862 struct fan_table_control fan_control; 863 u32 power_floor; 864 }; 865 866 struct cnqf_tran_params { 867 u32 time_constant; /* minimum time required to switch to next mode */ 868 u32 power_threshold; 869 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 870 u32 total_power; 871 u32 count; 872 bool priority; 873 bool shifting_up; 874 enum cnqf_mode target_mode; 875 }; 876 877 struct cnqf_config { 878 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 879 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 880 struct power_table_control defaults; 881 enum cnqf_mode current_mode; 882 u32 power_src; 883 u32 avg_power; 884 }; 885 886 struct apmf_cnqf_power_set { 887 u32 pfloor; 888 u32 fppt; 889 u32 sppt; 890 u32 sppt_apu_only; 891 u32 spl; 892 u32 stt_min_limit; 893 u8 stt_skintemp[STT_TEMP_COUNT]; 894 u32 fan_id; 895 } __packed; 896 897 struct apmf_dyn_slider_output { 898 u16 size; 899 u16 flags; 900 u32 t_perf_to_turbo; 901 u32 t_balanced_to_perf; 902 u32 t_quiet_to_balanced; 903 u32 t_balanced_to_quiet; 904 u32 t_perf_to_balanced; 905 u32 t_turbo_to_perf; 906 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 907 } __packed; 908 909 /* Smart PC - TA internals */ 910 enum system_state { 911 SYSTEM_STATE_S0i3, 912 SYSTEM_STATE_S4, 913 SYSTEM_STATE_SCREEN_LOCK, 914 SYSTEM_STATE_MAX, 915 }; 916 917 struct amd_pmf_pb_bitmap { 918 const char *name; 919 u32 bit_mask; 920 }; 921 922 static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = { 923 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(5)}, 924 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(6)}, 925 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(7)}, 926 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(8)}, 927 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(9)}, 928 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(10)}, 929 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(11)}, 930 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(12)}, 931 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(13)}, 932 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(14)}, 933 }; 934 935 static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = { 936 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(7)}, 937 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(8)}, 938 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(9)}, 939 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(10)}, 940 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(11)}, 941 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(12)}, 942 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(13)}, 943 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(14)}, 944 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(15)}, 945 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(16)}, 946 }; 947 948 /* Command ids for TA communication */ 949 enum ta_pmf_command { 950 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 951 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 952 }; 953 954 enum ta_pmf_error_type { 955 TA_PMF_TYPE_SUCCESS, 956 TA_PMF_ERROR_TYPE_GENERIC, 957 TA_PMF_ERROR_TYPE_CRYPTO, 958 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 959 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 960 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 961 TA_PMF_ERROR_TYPE_PB_CONVERT, 962 TA_PMF_ERROR_TYPE_PB_SETUP, 963 TA_PMF_ERROR_TYPE_PB_ENACT, 964 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 965 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 966 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 967 TA_PMF_ERROR_TYPE_MAX, 968 }; 969 970 struct pmf_action_table { 971 enum system_state system_state; 972 u32 spl; /* in mW */ 973 u32 sppt; /* in mW */ 974 u32 sppt_apuonly; /* in mW */ 975 u32 fppt; /* in mW */ 976 u32 stt_minlimit; /* in mW */ 977 u32 stt_skintemp_apu; /* in C */ 978 u32 stt_skintemp_hs2; /* in C */ 979 u32 p3t_limit; /* in mW */ 980 u32 pmf_ppt; /* in mW */ 981 u32 pmf_ppt_apu_only; /* in mW */ 982 }; 983 984 /* Input conditions */ 985 struct ta_pmf_condition_info { 986 u32 power_source; 987 u32 bat_percentage; 988 u32 power_slider; 989 u32 lid_state; 990 bool user_present; 991 u32 bios_input_1[2]; 992 u32 monitor_count; 993 u32 rsvd2[2]; 994 u32 bat_design; 995 u32 full_charge_capacity; 996 int drain_rate; 997 bool user_engaged; 998 u32 device_state; 999 u32 socket_power; 1000 u32 skin_temperature; 1001 u32 rsvd3[2]; 1002 u32 platform_type; 1003 u32 rsvd3_1[2]; 1004 u32 ambient_light; 1005 u32 length; 1006 u32 avg_c0residency; 1007 u32 max_c0residency; 1008 u32 s0i3_entry; 1009 u32 gfx_busy; 1010 u32 rsvd4[7]; 1011 bool camera_state; 1012 u32 workload_type; 1013 u32 display_type; 1014 u32 display_state; 1015 u32 rsvd5_1[17]; 1016 u32 bios_input_2[8]; 1017 u32 rsvd5[125]; 1018 }; 1019 1020 struct ta_pmf_load_policy_table { 1021 u32 table_size; 1022 u8 table[POLICY_BUF_MAX_SZ]; 1023 }; 1024 1025 /* TA initialization params */ 1026 struct ta_pmf_init_table { 1027 u32 frequency; /* SMU sampling frequency */ 1028 bool validate; 1029 bool sku_check; 1030 bool metadata_macrocheck; 1031 struct ta_pmf_load_policy_table policies_table; 1032 }; 1033 1034 /* Everything the TA needs to Enact Policies */ 1035 struct ta_pmf_enact_table { 1036 struct ta_pmf_condition_info ev_info; 1037 u32 name; 1038 }; 1039 1040 struct ta_pmf_action { 1041 u32 action_index; 1042 u32 value; 1043 u32 spl_arg; 1044 }; 1045 1046 /* Output actions from TA */ 1047 struct ta_pmf_enact_result { 1048 u32 actions_count; 1049 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 1050 u32 undo_count; 1051 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 1052 }; 1053 1054 union ta_pmf_input { 1055 struct ta_pmf_enact_table enact_table; 1056 struct ta_pmf_init_table init_table; 1057 }; 1058 1059 union ta_pmf_output { 1060 struct ta_pmf_enact_result policy_apply_table; 1061 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 1062 }; 1063 1064 struct ta_pmf_shared_memory { 1065 int command_id; 1066 int resp_id; 1067 u32 pmf_result; 1068 u32 if_version; 1069 union ta_pmf_output pmf_output; 1070 union ta_pmf_input pmf_input; 1071 }; 1072 1073 /* Core Layer */ 1074 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 1075 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 1076 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 1077 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 1078 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 1079 int amd_pmf_get_power_source(void); 1080 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 1081 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 1082 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 1083 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 1084 u32 fixp_q88_fromint(u32 val); 1085 int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev); 1086 void amd_pmf_set_device(struct device *p_device); 1087 1088 /* Metrics layer */ 1089 int amd_pmf_get_tbl_dram_addr(struct amd_pmf_dev *dev); 1090 1091 /* SPS Layer */ 1092 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 1093 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 1094 struct amd_pmf_static_slider_granular *table); 1095 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 1096 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 1097 struct apmf_static_slider_granular_output *output); 1098 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 1099 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 1100 const char *amd_pmf_source_as_str(unsigned int state); 1101 1102 const char *amd_pmf_source_as_str(unsigned int state); 1103 1104 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 1105 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 1106 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 1107 struct apmf_static_slider_granular_output_v2 *data); 1108 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 1109 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 1110 1111 /* Auto Mode Layer */ 1112 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 1113 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 1114 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 1115 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 1116 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 1117 int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v1 *req); 1118 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 1119 1120 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 1121 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 1122 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 1123 1124 /* CnQF Layer */ 1125 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 1126 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 1127 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 1128 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 1129 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 1130 extern const struct attribute_group cnqf_feature_attribute_group; 1131 1132 /* Smart PC builder Layer */ 1133 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 1134 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 1135 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 1136 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 1137 1138 /* Smart PC - TA interfaces */ 1139 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 1140 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 1141 int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev); 1142 u32 amd_pmf_get_ta_custom_bios_inputs(struct ta_pmf_enact_table *in, int index); 1143 1144 int amd_pmf_tee_init(struct amd_pmf_dev *dev, const uuid_t *uuid); 1145 void amd_pmf_tee_deinit(struct amd_pmf_dev *dev); 1146 int amd_pmf_start_policy_engine(struct amd_pmf_dev *dev); 1147 1148 /* Util Layer */ 1149 #if IS_ENABLED(CONFIG_AMD_PMF_UTIL_SUPPORT) 1150 int amd_pmf_cdev_register(struct amd_pmf_dev *dev); 1151 void amd_pmf_cdev_unregister(void); 1152 #else 1153 static inline int amd_pmf_cdev_register(struct amd_pmf_dev *dev) { return 0; } 1154 static inline void amd_pmf_cdev_unregister(void) {} 1155 #endif 1156 1157 #endif /* PMF_H */ 1158